CCD Delay ine Series MN38663S NTSC-Compatible CCD Video Delay Element Overview The MN38663S is a CCD signal delay element for video signal processing applications. It contains such components as a threefold-frequency circuit, a clock driver, charge I/O s, two CCD s switchable between 680.5 and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch is "" level, the MN38663S samples the using the supplied clock signal with a frequency of three times the NTSC color signal subcarrier frequency (3.579545 Mz) and, after adding in the attached filter delay, produces independent delays of 1 (the horizontal scan period) each for the two lines. When the switch is "" level, the MN38663S disables the threefold-frequency circuit and samples the with the image sensor drive frequency (9.545454 Mz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 (the horizontal scan period) each for the two lines. Features Single 4.4 V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38663S for signal processing Applications Video cameras Pin Assignment XIC V SS3 V DD3 VINC1 N.C. VINVC VGC1 VO1C V DD1 V SS1 ( TOP VIEW ) SOP020-P-0300 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 XIV PCOUT & VCOIN V BB V SS2 V DD2 VINVY SW VINC2 VGC2 VO2Y includes following four Product lifecycle stage. SDB00072BEM 1
MN38663S CCD Delay ine Series Block Diagram 9 10 16 17 3 2 14 7 12 V DD1 V SS1 V DD2 V SS2 V DD3 V SS3 SW VGC1 VGC2 VINVC 6 4 VINC1 15 VINVY 13 VINC2 XIV 20 XIC 1 Bias circuit Waveform amplifier Phase comparator 19 PCOUT & VCOIN Clamp circuit 1/3rd frequency divider VCO 78.5-stage 3-stage 78.5-stage 3-stage Mode switch Waveform Timing 602-stage V SS 602-stage Booster circuit ø1 driver ø2 driver detector detector Voltage generator Voltage generator Resampling output amplifier Resampling output amplifier øs driver ør driver øs driver Substrate bias generator 18 V BB 8 11 VO1C VO2Y includes following four Product lifecycle stage. 2
CCD Delay ine Series MN38663S Pin Descriptions Pin No. Symbol Pin Name Function Description 1 XIC 9.545454 Mz clock 2 V SS3 GND (3) Ground for clock multiplier circuit 3 V DD3 Power supply (3) Power supply for clock 4 VINC1 Camera signal (1) 5 N.C. No connection 6 VINVC Video signal (C) multiplier circuit 7 VGC1 Output gate connection (1) 8 VO1C output (1C) Output pin for signal fed to pin 4 or pin 6 9 V DD1 Power supply (1) Power supply for circuits 10 V SS1 GND (1) Ground for circuits 11 VO2Y output (2Y) Output pin for signal fed to pin 13 or pin 15 12 VGC2 Output gate connection (2) 13 VINC2 Power supply (2) 14 SW Camera/video mode switch 15 VINVY Video signal (Y) 16 V DD2 Power supply (2) Power supply for digital circuits other than frequency multiplier 17 V SS2 GND (2) Ground for digital circuits other than frequency multiplier 18 V BB Substrate connection Negative voltage pin 19 PCOUT&VCOIN Phase comparator output and voltage controlled oscillator 20 XIV 3.579545 Mz clock Notes 1: Always connect V DD1, V DD2, and V DD3 to the same voltage. 2: Always connect V SS1, V SS2, and V SS3 to ground. includes following four Product lifecycle stage. 3
MN38663S CCD Delay ine Series Electrical Characteristics V DD =4.4V, V ckv =0.3V P-P (sine wave), f ckv =3.579545Mz (Converted to 10.738635 Mz internally) V ckc =0.3V P-P (sine wave), f ckc =9.545454Mz, V in =0.5V P-P (sine wave), Ta=25 C Parameter Symbol Conditions min typ max Unit Power supply current Average current for 4.4-V power I DDV 30 48 (Video signal I/O) supply when SW is "" level ma Power supply current Average current for 4.4-V power I DDC 28 46 (Camera signal I/O) supply when SW is "" level bandwidth (Video signal I/O) bandwidth (Camera signal I/O) BWV BWC 3 db for 200 kz value when SW is "" level 3 db for 200 kz value when SW is "" level 3.0 4.2 2.7 3.7 Insertion gain IG f sig =200kz 1 4 7 db Total harmonic distortion TD f sig =200kz 1 4 % -to-noise ratio S/N output (V P-P )/noise output (rms) 50 56 db Clock leak (V1) Clock leak (C) Clock leak (V2) NCV1 NCC NCV2 3.579545-Mz component output/main output signal when SW is "" level 9.545454-Mz component output/main output signal when SW is "" level Mz 50 40 db 15 10 db 10.738635-Mz component output/main 15 10 db output signal when switch signal is "" level Crosstalk CT f sig =200kz 37 db Delay (Video signal I/O) τ DV When SW is "" level 63.40 Delay (Camera signal I/O) τ DC When SW is "" level 63.42 VO pin output impedance ZO 350 700 Ω Input bias voltage V BINC Applicable to signal pins VINC1 and VINC2 µs 2.20 2.50 2.80 V Input bias voltage V BINY Applicable to signal pin VINC1 2.10 2.40 2.70 V Input clamp voltage V CIN Applicable to signal pin VINVY 1.90 2.20 2.50 V Output bias voltage V BOC Applicable to signal output pins VO1C 1.30 2.30 3.30 V and VO2Y when SW is "" level Applicable to signal output pin Output bias voltage V BOY VO1C when SW is "" level Applicable to signal output pin Output clamp voltage V CO VO2Y when SW is "" level 1.35 2.35 3.35 V 1.05 2.05 3.05 V Substrate voltage V BB 2.5 V includes following four Product lifecycle stage. 4
CCD Delay ine Series MN38663S Application Circuit Example + 4.4V 10m 4.4V or GND 0.01µF 0.01µF 0.1µF 0.1µF 0.1µF 9 10 16 17 3 2 14 7 12 V DD1 V SS1 V DD2 V SS2 V DD3 V SS3 SW VGC1 VGC2 VINVC 6 + 0.47µF VINC1 4 + 0.47µF VINVY 15 0.47µF + VINC2 13 0.47µF + Clock XIV 20 Clock 1000pF 1000pF XIC 1 Bias circuit Waveform amplifier Phase comparator 19 PCOUT & VCOIN Clamp circuit 1/3rd frequency divider VCO 78.5-stage 3-stage 78.5-stage 3-stage Mode switch 602-stage 602-stage Waveform Timing Booster circuit ø1 driver detector detector Voltage generator Voltage generator Resampling output amplifier Resampling output amplifier øs driver ør driver ø2 driver øs driver Substrate bias generator 18 V BB 0.01µF 8 VO1C output (1C) 11 VO2Y output (2Y) includes following four Product lifecycle stage. 0.01µF 820Ω 1000pF Note: If the capacitor attached to pin 18 has a polarity, attach the negative pole to pin 18. 5
MN38663S CCD Delay ine Series Package Dimensions (Unit:mm) SOP020 P 0300 12.6±0.2 20 11 1 10 (0.6) 1.27 0.4±0.1 Seating plane 5.5±0.2 1.5±0.2 0.1±0.1 1.9 max. 7.7±0.3 1.1±0.2 0.30 min. Note) The package of this product will be changed to the following lead-free type (SOP020-P-0300D). includes following four Product lifecycle stage. 0.15 +0.10-0.05 6
CCD Delay ine Series MN38663S New Package Dimensions (Unit: mm) SOP020-P-0300D (ead-free package) 20 12.63±0.20 11 1.10±0.20 1 (0.60) 1.27 Seating plane 0.40 +0.10-0.05 10 5.50±0.20 1.50±0.20 0.10±0.10 7.70±0.30 1.90 max. 0.15 +0.10-0.05 0.30 min. 0 to 10 Seating plane includes following four Product lifecycle stage. 7
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