ELECTRICAL PERFORMANCE REPORT

CIRCUITS & DESIGN ELECTRICAL PERFORMANCE REPORT DENSIPAC 4 ROW Date: 06-12-2006 Circuits & Design EMEA Circuits & Design 1/21 06/12/2006

1 INTRODUCTION... 3 2 CONNECTORS, TEST BOARDS AND TEST EQUIPMENT... 3 2.1 CONNECTORS... 3 2.2 TEST EQUIPMENT... 3 2.3 TEST BOARDS... 3 2.4 MEASURED PIN ASSIGNMENTS... 4 3 MEASUREMENT RESULTS... 5 3.1 DIFFERENTIAL INSERTION LOSS SDD21... 5 3.2 PROPAGATION DELAY AND SKEW... 7 3.3 NOISE MEASUREMENT... 8 3.3.1 Noise measurement setup... 8 3.3.2 NeN and FeN results... 9 3.4 EYE PATTERN MEASUREMENT... 11 3.4.1 Measurement setup... 11 3.4.2 Eye pattern of the THRU connection (reference measurement)... 12 3.4.3 SMT version S/G =1:1 @ pair c7c8 with NeN @ b5b6... 13 3.4.4 SMT version S/G= 3:2 @ pair c8c9 with NeN @ b9b10... 14 3.4.5 PF version S/G =1:1 @ pair c7c8 with NeN @ b5b6... 15 3.4.6 Summary of eye measurements... 16 4 SYSTEM SIMULATION... 17 4.1 SYSTEM SETUP... 17 4.2 SYSTEM SIMULATION RESULTS... 18 4.2.1 SMT S/G=1:1 @ diff. pair c7c8 with NeN of the adjacent aggressors... 18 4.2.2 SMT S/G=3:2 @ diff. pair c8c9 with NeN of the adjacent aggressors... 19 4.2.3 PF S/G=1:1 @ diff. pair c7c8 with NeN of the adjacent aggressors... 20 4.3 SUMMARY OF SIMULATION RESULTS... 21 5 CONCLUSION... 21 Circuits & Design 2/21 06/12/2006

1 Introduction This document analyses the electrical performance of the DensiPac connector system for high data rates. The DensiPac connector system is a full SMT capable system with SMT on both backplane and daughtercard. This capability provides a number of electrical benefits and triggers the interest to also use the connector system for higher data rate transmission. Also the press-fit version of the DensiPac backplane connector was analyzed to check performance differences with the SMT backplane version. Measurements were done on component level for different pin assignments of the connector. In addition, a number of system simulations were done based on the measured component characteristics. 2 Connectors, test boards and test equipment 2.1 Connectors DensiPac Receptacle 4 row, Surface Mount (SMT) (p/n: 9-1393754-3) DensiPac Male 4 row, Surface Mount (SMT) (p/n: 9-1393754-9) DensiPac Male 4 row, Press-fit (PF) (p/n: 1393755-2) 2.2 Test equipment Agilent 8510 45MHz-26 GHz Vector Network Analyzer Agilent 54750A 50GHz bandwidth DSO Agilent 81134A 15MHz to 3.35GHz Pattern Generator Agilent 8111A Function Generator 2.3 Test boards The DensiPac evaluation boards are shown in figure 1. PCB material: FR4 (Dielektra, type 15193-50-DAT) PCB thickness:1.6mm Board stackup: 6 layers (2 signal routing layers) Trace length on female and male test board: 50mm All routed traces are matched length Figure 1: DensiPac evaluation boards Circuits & Design 3/21 06/12/2006

2.4 Measured pin assignments The DensiPac connector is an open pin field connector. This report describes the electrical performance of some specific differential pin assignments. See table 1 and 2 for an overview of the measured connector combinations and pin assignments. Female version Male version Pin assignment Differential pair orientation Signal/Ground ratio 1 SMT SMT See figure 2 Within row 1:1 2 SMT SMT See figure 3 Within row 3:2 3 SMT PF See figure 4 Within row 1:1 Table 1: Overview of the measured pin assignments Differential pin assignments Female SMT Male SMT 3 4 5 6 7 8 9 10 11 12 13 14 a T T X X a A X X a A X X b X X a A X X a A X X T T c T T X X a A X X a A X X d X X a A X X a A X X T T Figure 2: SMT S/G=1:1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a T T X a A X a A X a A X T T X b X T T X a A X a A X a A X T T c T T X a A X a A X a A X T T X d X T T X a A X a A X a A X T T Figure 3: SMT S/G=3:2 Female SMT Male PF 3 4 5 6 7 8 9 10 11 12 13 14 a T T X X a A X X a A X X b X X a A X X a A X X T T c T T X X a A X X a A X X d X X a A X X a A X X T T Figure 4: PF S/G=1:1 A a X T Active line Active inverted line Grounded Terminated to 50 Ohms Table 2: Overview of differential assignments Circuits & Design 4/21 06/12/2006

3 Measurement results 3.1 Differential insertion loss SDD21 Figure 5, 6 and 7 show the differential insertion loss SDD 21 of the connector + footprint. PCB traces and SMA connections are de-embedded from the measurement. SMT-SMT S/G=1:1 0 Differential Insertion Loss -0.5-1 -1.5 Insertion Loss [db] -2-2.5-3 -3.5 Figure 5: Differential insertion loss SMT S/G = 1:1 SMT-SMT S/G=3:2 0 Differential Insertion Loss -0.5-1 -1.5 Insertion Loss [db] -2-2.5-3 -3.5-4 a7+a8- c7+c8- -4.5 b9+b9- d9+d9- -5 0 0.5 1 1.5 2 2.5 3 Frequency [GHz] -4 a8+a9- b9+b10- -4.5 c8+c9- d9+d10- -5 0 0.5 1 1.5 2 2.5 3 Frequency [GHz] Figure 6: Differential insertion loss SMT S/G = 3:2 Circuits & Design 5/21 06/12/2006

PF-SMT S/G=1:1 0 Differential Insertion Loss -1-2 -3 Insertion Loss [db] -4-5 -6-7 -8 a7+a8- c7+c8- -9 b9+b9- d9+d9- -10 0 0.5 1 1.5 2 2.5 3 Frequency [GHz] Figure 7: Differential insertion loss PF S/G = 1:1 Circuits & Design 6/21 06/12/2006

3.2 Propagation delay and skew Table 3, 4 and 5 summarize delay, intra pair skew and the pair-to-pair skew. Propagation delay and skew values were measured at 50% level. PCB traces and connections are deembedded. Connector row SMT version S/G 1:1 Connector Pair Delay Within Pair Skew A a7-a8 149 ps <5 ps B b9-b10 165 ps <5 ps C c7-c8 182 ps <5 ps D d9-d10 203 ps <5 ps Max pair-to-pair skew 54 ps Table 3: Delay, intra pair skew end pair-to-pair skew for SMT S/G = 1:1 Connector row SMT version S/G 3:2 Connector Pair Delay Within Pair Skew a a8-a9 150 ps <5 ps b b9-b10 164 ps <5 ps c c8-c9 179 ps <5 ps d d9-d10 201 ps <5 ps Max pair-to-pair skew 51 ps Table 4: Delay, intra pair skew end pair-to-pair skew for SMT S/G = 3:2 Connector Row PF version S/G 1:1 Connector Pair Delay Within Pair skew A a7-a8 165 ps <10 ps B b9-b10 173 ps <10 ps C c7-c8 184 ps <10 ps D d9-d10 217 ps <10 ps Max pair-to-pair skew 51 ps Table 5: Delay, intra pair skew end pair-to-pair skew for PF S/G = 1:1 Circuits & Design 7/21 06/12/2006

3.3 Noise measurement 3.3.1 Noise measurement setup Table 6 describes the victim and aggressor pin assignment for the noise measurement. Both Near-end Noise (NeN) and Far-end-Noise (FeN) were measured. PCB traces and connections are de-embedded. Noise test setup: Victim and aggressor assignment Female SMT-Male SMT or PF S:G = 1:1 3 4 5 6 7 8 9 10 11 12 13 14 a a A X X q Q X X a A X X b X X a A X X a A X X T T c T T X X a A X X T T X X d X X T T X X T T X X T T Figure 8: noise setup victim = row a 3 4 5 6 7 8 9 10 11 12 13 14 a T T X X a A X X T T X X b X X a A X X a A X X T T c a A X X q Q X X a A X X d X X a A X X a A X X T T Figure 10: noise setup victim = row c 3 4 5 6 7 8 9 10 11 12 13 14 a T T X X a A X X a A X X b X X a A X X q Q X X a A c T T X X a A X X a A X X d X X a A X X a A X X T T Figure 9: noise setup victim = row b 3 4 5 6 7 8 9 10 11 12 13 14 a T T X X T T X X T T X X b X X T T X X a A X X T T c T T X X a A X X a A X X d X X a A X X q Q X X a A Figure 11: noise setup victim = row d Female SMT-Male SMT S:G = 3:2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a T T X a A X q Q X a A X T T X b X T T X a A X a A X T T X T T c T T X T T X a A X T T X T T X d X T T X T T X T T X T T X T T Figure 12: noise setup victim = row a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a T T X T T X a A X T T X T T X b X T T X a A X a A X T T X T T c T T X a A X q Q X a A X T T X d X T T X a A X a A X T T X T T Figure 14: noise setup victim = row c 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a T T X T T X a A X a A X T T X b X T T X a A X q Q X a A X T T c T T X T T X a A X a A X T T X d X T T X T T X a A X T T X T T Figure 13: noise setup victim = row b 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a T T X T T X T T X T T X T T X b X T T X T T X a A X T T X T T c T T X T T X a A X a A X T T X d X T T X a A X a A X a A X T T Figure 15: noise setup victim = row d Key A a X q Q T Active line Active inverted line Grounded Quiet line (victim) Quiet inverted line (victim) Terminated to 50 Ohms Table 6: Noise Test setup: victim and aggressor assignments Circuits & Design 8/21 06/12/2006

3.3.2 NeN and FeN results The reported noise values are total asynchronous noise values (worst case noise) measured on the worst case victim pair. (the victim pair which has the highest noise value) Figure 16, 17 and 18 show the NeN and FeN measured at different rise times (10%-90%) for the SMT S/G=1:1, SMT S/G=3:2 and PF S/G=1:1 versions. SMT-SMT S/G=1:1 Total asynchronous Noise SMT version S/G=1:1 7 6 5 Noise [%] 4 3 2 1 1.9 0.5 2.1 0.6 2.3 0.7 2.6 1.0 2.8 1.2 3.4 1.6 NeN FeN 0 275 250 225 200 175 150 125 100 75 50 25 risetime [ps] SMT-SMT S/G=3:2 Figure 16: Total asynchronous noise for SMT S/G=1:1 Total asynchronous Noise SMT version S/G=3:2 7 6 5 4.7 Noise [%] 4 3 2 1 1.9 0.8 2.1 1.0 2.5 1.2 3.2 1.6 3.8 2.0 2.7 NeN FeN 0 275 250 225 200 175 150 125 100 75 50 25 risetime [ps] Figure 17: Total asynchronousnnoise for SMT S/G=3:2 Circuits & Design 9/21 06/12/2006

PF-SMT S/G=1:1 Total asynchronous Noise PF version S/G=1:1 7 6.0 6 Noise [%] 5 4 3 2.2 2.6 3.1 4.2 3.7 4.9 4.7 5.9 NeN FeN 2 2.4 1 1.2 1.6 0 275 250 225 200 175 150 125 100 75 50 25 risetime [ps] Figure 18: Total asynchronous noise for PF S/G=1:1 Circuits & Design 10/21 06/12/2006

3.4 Eye pattern measurement 3.4.1 Measurement setup Figure 19 describes the setup for the eye pattern measurement. Included in the measurement are: female + male connector and footprint; test board traces, connections and measurement cables. A Near-end-Noise pattern is applied on the adjacent aggressor pair with the highest level of X-talk at an amplitude level of four times that of the signal pair. Stimulus signal: Data Pattern = Differential PRBS 2 23-1 Vpp = 1000 mv (-500mV to 500mV) Edge Rate = 75ps Data Rate = 0.5 Gbps- 3.35 Gbps Stimulus signal for NEXT: Data pattern = Differential PRBS 2 23-1 Vpp = 4000 mv (-2000mV to 2000mV) Edge Rate = 75ps Data Rate = 0.5 Gbps- 3.35 Gbps Delay for NEXT: Sine wave at 10kHz Phase modulation was applied to the NEXT stimulus signal to generate an asynchronous signal, this will lead to a worst case noise measurement. Daughtercard test board: Trace length: 50 mm Board material: FR4 Trace width: 0.1 mm Trace spacing: 0.15mm Board thickness: 1.6 mm Stackup: 6-layer (2 routing layers) Routing: on bottom signal layer Pattern Generator Agilent 81134A 15 MHz-3.35 GHz DELAY Function Generator Agilent 8111A DIFFERENTIAL PRBS DATA EYE MEASUREMENT DSO Agilent 54750A 50 GHz bandwidth TRIGGER NOISE ON AgGRESSOR PAIR DIFFERENTIAL PRBS DATA Backplane test board: Trace length: 50 mm Board material: FR4 Trace width: 0.1 mm Trace spacing: 0.15mm Board thickness: 1.6 mm Stackup: 6 layer (2 routing layers) Rouating: on bottom signal layer Figure 19: Eye pattern measurement setup Circuits & Design 11/21 06/12/2006

3.4.2 Eye pattern of the THRU connection (reference measurement) The differential eye diagram was measured of a 100mm PCB trace. (measurement cables and SMA connectors included) Eye Height @ 3.35 Gbps 740mV 27 ps p-p @ 2.5 Gbps 828mV 24 ps p-p @ 2 Gbps 864mV 27 ps p-p @ 1.5 Gbps 888mV 22 ps p-p @ 1 Gbps 900 mv 27 ps p-p @ 500 Mbps 928 mv 22 ps p-p Figure 20: Eye pattern of the THRU Circuits & Design 12/21 06/12/2006

3.4.3 SMT version S/G =1:1 @ pair c7c8 with NeN @ b5b6 Eye Height @ 3.35 Gbps 679 mv 29 ps p-p @ 2.5 Gbps 779 mv 26 ps p-p @ 2 Gbps 799 mv 30 ps p-p @ 1.5 Gbps 763 mv 20 ps p-p @ 1 Gbps 859 mv 23 ps p-p @ 500 Mbps 907 mv 28 ps p-p Figure 21: SMT version S/G =1:1 @ pair c7c8 with NeN @ b5b6 *The jitter was measured using a ±10 mv jitter box. Circuits & Design 13/21 06/12/2006

3.4.4 SMT version S/G= 3:2 @ pair c8c9 with NeN @ b9b10 Eye Height @ 3.35 Gbps 651 mv 30 ps p-p @ 2.5 Gbps 763 mv 31 ps p-p @ 2 Gbps 763 mv 28 ps p-p @ 1.5 Gbps 763 mv 22 ps p-p @ 1 Gbps 851 mv 27 ps p-p @ 500 Mbps 887 mv 22 ps p-p Figure 22: SMT version S/G= 3:2 @ pair c8c9 with NeN @ b9b10 *The jitter was measured using a ±10 mv jitter box. Circuits & Design 14/21 06/12/2006

3.4.5 PF version S/G =1:1 @ pair c7c8 with NeN @ b5b6 Eye Height @ 3.35 Gbps 615 mv 34 ps p-p @ 2.5 Gbps 751 mv 32 ps p-p @ 2 Gbps 751 mv 37 ps p-p @ 1.5 Gbps 751 mv 22 ps p-p @ 1 Gbps 823 mv 27 ps p-p @ 500 Mbps 883 mv 22 ps p-p Figure 23: PF version S/G =1:1 @ pair c7c8 with NeN @ b5b6 *The jitter was measured using a ±10 mv jitter box. Circuits & Design 15/21 06/12/2006

3.4.6 Summary of eye measurements Data Rate THRU (100mm) SMT S/G=1:1 SMT S/G=3:2 PF S/G=1:1 Eye Opening pk-pk @ c7c8 @ c8c9 @ c7c8 NeN @ b5b6 NeN @ b9b10 NeN @ b5b6 Eye Opening pk-pk Eye Opening pk-pk Eye Opening pk-pk 0.5 Gbps 93% 22 ps 91% 28 ps 89% 22 ps 88% 22 ps 1.0 Gbps 90% 27 ps 86% 23 ps 85% 27 ps 82% 27 ps 1.5 Gbps 89% 22 ps 76% 20 ps 76% 22 ps 75% 22 ps 2.0 Gbps 86% 27 ps 80% 30 ps 76% 28 ps 75% 37 ps 2.5 Gbps 83% 24 ps 78% 26 ps 76% 31 ps 75% 32 ps 3.35 Gbps 74% 27 ps 68% 29 ps 65% 30 ps 62% 34 ps See figure 21 See figure 22 See figure 23 See figure 24 Table 7: Summary of eye measurements Circuits & Design 16/21 06/12/2006

4 System simulation 4.1 System setup Figure 24 shows the setup of the system simulation. The signal passes through two daughtercards, two connectors and a backplane. Different trace lengths in the backplane are simulated (200, 300 and 400mm). The measured connector performance is used for this system simulation. All simulations were done with asynchronous Near-end Noise (NeN) aggressors on all adjacent lines. Stimulus signal: Date Pattern = Differential PRBS 2 7-1 Vpp = 1000 mv (-500mV to 500mV) Data Rate = 1 Gbps / 2.5 Gbps / 3.125 Gbps Daughtercard: Trace length: 100 mm Board material: FR4: Nelco 4000-6 Trace width: 0.1 mm Trace spacing: 0.15mm Board thickness: 1.6 mm Measured electrical performance of connector used for system simulation Backplane: Trace length: 200 mm 400 mm Board material: FR4: Nelco 4000-6 Trace width: 0.1 mm Trace spacing: 0.15mm Board thickness: 1.6 mm Figure 24: System simulation setup Circuits & Design 17/21 06/12/2006

4.2 System simulation results 4.2.1 SMT S/G=1:1 @ diff. pair c7c8 with NeN of the adjacent aggressors 3 4 5 6 7 8 9 10 11 12 13 14 a T T X X a A X X T T X X b X X a A X X a A X X T T c a A X X q Q X X a A X X d X X a A X X a A X X T T A a X q Q T Aggressor line Aggressor inverted line Grounded Signal line (victim) Signal inverted line (victim) Terminated to 50 Ohms @ 1.0 Gbps @ 2.5 Gbps @ 3.125 Gbps Backplane trace length=400mm Backplane trace length=300mm Backplane trace length=200mm Figure 25: System simulation results of SMT S/G=1:1 Circuits & Design 18/21 06/12/2006

4.2.2 SMT S/G=3:2 @ diff. pair c8c9 with NeN of the adjacent aggressors 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a T T X T T X a A X T T X T T X b X T T X a A X a A X T T X T T c a A X a A X q Q X a A X T T X d X T T X a A X a A X T T X T T A a X q Q T Aggressor line Aggressor inverted line Grounded Signal line (victim) Signal inverted line (victim) Terminated to 50 Ohms @ 1.0 Gbps @ 2.5 Gbps @ 3.125 Gbps Backplane trace length=400mm Backplane trace length=300mm Backplane trace length=200mm Figure 26: System simulation results of SMT S/G=3:2 Circuits & Design 19/21 06/12/2006

4.2.3 PF S/G=1:1 @ diff. pair c7c8 with NeN of the adjacent aggressors 3 4 5 6 7 8 9 10 11 12 13 14 a T T X X a A X X T T X X b X X a A X X a A X X T T c a A X X q Q X X a A X X d X X a A X X a A X X T T A a X q Q T Aggressor line Aggressor inverted line Grounded Signal line (victim) Signal inverted line (victim) Terminated to 50 Ohms @ 1.0 Gbps @ 2.5 Gbps @ 3.125 Gbps Backplane trace length=400mm Backplane trace length=300mm Backplane trace length=200mm Figure 27: System simulation results of PF S/G=1:1 Circuits & Design 20/21 06/12/2006

4.3 Summary of Simulation Results SMT S/G=1:1 SMT S/G=3:2 PF S/G=1:1 @ c7c8 @ c8c9 @ c7c8 With Async. NeN With Async. NeN With Async. NeN Backplane trace Data Rate Eye Opening pk-pk Eye Opening pk-pk Eye Opening pk-pk 200 mm 300 mm 400 mm 1.0 Gbps 75% 38 ps 73% 40 ps 64% 76 ps 2.5 Gbps 58% 51 ps 56% 53 ps 49% 78 ps 3.125 Gbps 48% 54 ps 48% 56 ps 34% 96 ps 1.0 Gbps 72% 46 ps 70% 48 ps 64% 77 ps 2.5 Gbps 51% 62 ps 50% 65 ps 43% 96 ps 3.125 Gbps 42% 72 ps 42% 72 ps 29% 105 ps 1.0 Gbps 66% 64 ps 65% 64 ps 59% 106 ps 2.5 Gbps 44% 80 ps 44% 80 ps 35% 114 ps 3.125 Gbps 34% 89 ps 34% 90 ps 20% 129 ps See figure 26 See figure 27 See figure 28 Table 8: Summary of simulation results 5 Conclusion The above analysis shows that the DensiPac connector system is capable to deal with data rates ranging from 2.5 Gbps to 3.125 Gbps, well above the currently specified data rate of 1.5 Gbps for the connecter system. The noise performance of the chosen pin assignments is excellent. The analysis also shows that the SMT backplane component has performance benefits over the press-fit version. This is caused by the different contact arrangement inside the male connector. Using the SMT backplane component, the backplane via array can be electrically optimized and the DensiPac connector system can remain a connector system with solid electrical performance while system data rates are being upgraded. Circuits & Design 21/21 06/12/2006