CMO VLI esign Circuits & Lyout Outline Brief History CMO Gte esign Pss Trnsistors CMO Ltches & Flip-Flops tndrd Cell Lyouts tick igrms lide 2
Brief History 958: First integrted circuit Flip-flop using two trnsistors Built y Jck Kily t Texs Instruments 23 Intel Pentium 4 μprocessor (55 million trnsistors) 52 Mit RM (>.5 illion trnsistors) 53% compound nnul growth rte over 45 yers No other technology hs grown so fst so long riven y minituriztion of trnsistors mller is cheper, fster, lower in power! Revolutionry effects on society lide 3 nnul les 8 trnsistors mnufctured in 23 million for every humn on the plnet Glol emiconductor Billings (Billions of U$) 2 5 5 982 984 986 988 99 992 994 996 998 2 22 er lide 4 2
Invention of the Trnsistor Vcuum tues ruled in first hlf of 2 th century Lrge, expensive, power-hungry, unrelile 947: first point contct trnsistor John Brdeen nd Wlter Brttin t Bell Ls Red Crystl Fire y Riordn, Hoddeson lide 5 Trnsistor Types Bipolr trnsistors npn or pnp silicon structure mll current into very thin se lyer controls lrge currents etween emitter nd collector Bse currents limit integrtion density Metl Oxide emiconductor Field Effect Trnsistors nmo nd pmo MOFET Voltge pplied to insulted gte controls current etween source nd drin Low power llows very high integrtion lide 6 3
MO Integrted Circuits 97 s processes usully hd only nmo trnsistors Inexpensive, ut consume power while idle Intel 256-it RM Intel 44 4-it μproc 98s-present: CMO processes for low idle power lide 7 Moore s Lw 965: Gordon Moore plotted trnsistor on ech chip Fit stright line on semilog scle Trnsistor counts hve douled every 26 months,,,,, Integrtion Levels Trnsistors,,,,, 8286 Intel386 Intel486 Pentium 4 Pentium III Pentium II Pentium Pro Pentium I: gtes MI: gtes 886,, 88 44 88 LI:, gtes 97 975 98 985 99 995 2 VLI: > k gtes er lide 8 4
Corollries Mny other fctors grow exponentilly Ex: clock frequency, processor performnce,, 44 88 Clock peed (MHz) 88 886 8286 Intel386 Intel486 Pentium Pentium Pro/II/III Pentium 4 97 975 98 985 99 995 2 25 er lide 9 CMO Gte esign ctivity: ketch 4-input CMO NN gte lide 5
CMO Gte esign ctivity: ketch 4-input CMO NOR gte B C lide Complementry CMO Complementry CMO logic gtes nmo pull-down network pmo pull-up network.k.. sttic CMO inputs pmo pull-up network output Pull-down OFF Pull-down ON Pull-up OFF Z (flot) Pull-up ON X nmo pull-down network lide 2 6
eries nd Prllel nmo: = ON pmo: = ON eries: oth must e ON Prllel: either cn e ON g g2 () g g2 OFF OFF OFF ON () ON OFF OFF OFF g g2 (c) OFF ON ON ON g g2 (d) ON ON ON OFF lide 3 Conduction Complement Complementry CMO gtes lwys produce or Ex: NN gte eries nmo: = when oth inputs re Thus = when either input is Requires prllel pmo B Rule of Conduction Complements Pull-up network is complement of pull-down Prllel -> series, series -> prllel lide 4 7
Compound Gtes Compound gtes cn do ny inverting function Ex: = B+ C (N-N-OR-INVERT, OI22) C C B B () () nmo network (c) B C (d) C B pmo network C B B C B C (f) (e) lide 5 = ( + B+ C) Exmple: O3I lide 6 8
= ( + B+ C) Exmple: O3I B C B C lide 7 ignl trength trength of signl How close it pproximtes idel voltge source V nd GN rils re strongest nd nmo pss strong But degrded or wek pmo pss strong But degrded or wek Thus nmo re est for pull-down network lide 8 9
Pss Trnsistors Trnsistors cn e used s switches g s d g s d lide 9 Pss Trnsistors Trnsistors cn e used s switches s g d s s g = d g = d Input g = Output strong g = degrded s g d s s g = d g = d Input g = Output degrded g = strong lide 2
Trnsmission Gtes Pss trnsistors produce degrded outputs Trnsmission gtes pss oth nd well lide 2 Trnsmission Gtes Pss trnsistors produce degrded outputs Trnsmission gtes pss oth nd well g g g =, g = g =, g = Input Output g =, g = strong g =, g = strong g g g g g g lide 22
Tristtes Tristte uffer produces Z when not enled lide 23 Tristtes Tristte uffer produces Z when not enled Z Z lide 24 2
Nonrestoring Tristte Trnsmission gte cts s tristte uffer Only two trnsistors But nonrestoring, i.e., the output is not driven y Vdd or GN Noise on is pssed on to lide 25 Tristte Inverter Tristte inverter produces restored output Violtes conduction complement rule Becuse we wnt Z output lide 26 3
Tristte Inverter Tristte inverter produces restored output Violtes conduction complement rule Becuse we wnt Z output = = 'Z' = = lide 27 Multiplexers 2: multiplexer chooses etween two inputs X X X X lide 28 4
Multiplexers 2: multiplexer chooses etween two inputs X X X X lide 29 Gte-Level Mux esign = + (too mny trnsistors) How mny trnsistors re needed? lide 3 5
Gte-Level Mux esign = + (too mny trnsistors) How mny trnsistors re needed? 2 2 4 4 2 2 4 2 lide 3 Trnsmission Gte Mux Nonrestoring mux uses two trnsmission gtes lide 32 6
Trnsmission Gte Mux Nonrestoring mux uses two trnsmission gtes Only 4 trnsistors lide 33 Inverting Mux Inverting multiplexer Use compound OI22 Or pir of tristte inverters Essentilly the sme thing Noninverting multiplexer dds n inverter lide 34 7
Ltch When =, ltch is trnsprent flows through to like uffer When =, the ltch is opque holds its old vlue independent of.k.. trnsprent ltch or level-sensitive ltch Ltch lide 35 Ltch esign Multiplexer chooses or old lide 36 8
Ltch Opertion = = lide 37 Flip-flop When rises, is copied to t ll other times, holds its vlue.k.. positive edge-triggered flip-flop, mster-slve flip-flop Flop lide 38 9
Flip-flop esign Built from mster nd slve ltches M Ltch M Ltch lide 39 Flip-flop Opertion M = M = lide 4 2
Rce Condition Bck-to-ck flops cn mlfunction from clock skew econd flip-flop fires lte (if no clock skew, nd 2 should rrive t the the sme time) sees first flip-flop chnge nd cptures its result Clled hold-time filure or rce condition 2 2 Flop Flop 2 2 lide 4 Nonoverlpping Clocks Nonoverlpping clocks cn prevent rces s long s nonoverlp exceeds clock skew Industry mnges skew more crefully insted φ 2 φ M φ 2 φ 2 φ φ φ 2 φ φ φ 2 lide 42 2
Gte Lyout Lyout cn e very time consuming esign gtes to fit together nicely Build lirry of stndrd cells tndrd cell design methodology V nd GN should ut (stndrd height) nd often clled supply rils djcent gtes should stisfy design rules nmo t ottom nd pmo t top ll gtes include well nd sustrte contcts lide 43 Exmple: Inverter lide 44 22
Exmple: NN3 Horizontl N-diffusion nd p-diffusion strips Verticl polysilicon gtes Metl V ril t top Metl GN ril t ottom 32 λ y 4 λ lide 45 tick igrms tick digrms help pln lyout quickly Need not e to scle rw with color pencils or dry-erse mrkers lide 46 23
Wiring Trcks wiring trck is the spce required for wire 4 λ width, 4 λ spcing from neighor = 8 λ pitch Trnsistors lso consume one wiring trck lide 47 Well spcing Wells must surround trnsistors y 6 λ Implies 2 λ etween opposite trnsistor flvors Leves room for one wire trck lide 48 24
re Estimtion Estimte re y counting wiring trcks Multiply y 8 to express in λ lide 49 Exmple: O3I ketch stick digrm for O3I nd estimte re = ( + B+ C) lide 5 25
Exmple: O3I ketch stick digrm for O3I nd estimte re = ( + B+ C) lide 5 Exmple: O3I ketch stick digrm for O3I nd estimte re = ( + B+ C) lide 52 26
HW#2 ue: eptemer clss time No lte homework ccepted Exercises:.8,.9,.,.2,.8 lide 53 27