QSFP+ 40GBASE-LR4 Fiber Transceiver Preliminary Features RoHS-6 compliant Hot pluggable QSFP+ form factor 40Gbps aggregate rate 4x10Gb/s CWDM transmitter Compliant to industrial standard SFF-8436 QSFP+ standard Power consumption <3.5W Duplex LC receptacle. I2C standard management interface Description The QCP-10G3B4QDR is a 40Gbps, hot pluggable fiber transceivers for 40G Ethernet data transmission. The module support 40Gbps links over single mode fiber for 10km. The module consist 4x10Gbps CWDM LDs and multiplex 4 CWDM signals on a 40Gbps optical transmission, and de-multiplex 40G receiver signals to 4 CWDM signals. 4 receiving data lanes and each lane at data rate up to 10.3125Gbps. QCP-10G3B4QDR is designed to meet the requirements of high speed, high density and low power consumption for applications in today s data center. Application 40G Ethernet Proprietary high speed, high density data transmission. Switch and router high speed backplane interconnect High performance computing, server and data storage. QCP-10G3B4QDR compliant with QSFP+ MSA and IEEE 802.3ba 40Gbase-LR4. 1 Revision: Draft
1. 1. Absolute Maximum Ratings Storage Temperature Ts -40 75 ºC Storage Ambient Humidity HA 5 85 % Power Supply Voltage VCC 0 3.6 V 2. Recommended Operating Conditions Operating Case Temperature TC 0 +70 ºC Ambient Humidity HA 5 85 % Non-condensing Power Supply Voltage VCC 3.13 3.3 3.47 V Total Power dissipation 3.5 W Data rate for transmitter per lane 10.3125-10.3125+ 10.3125 100ppm 100ppm Gbd Data rate for receiver per lane 10.3125-10.3125+ 10.3125 100ppm 100ppm Gbd Transmission Distance 10 km 3. Specification of Transmitter Total Average Launched Power P O +8.3 dbm Note (1) Optical Extinction Ratio ER 3.5 db Lane Center Wavelength(Range) λ C 1284.5 1304.5 1264.5 1324.5 1271 1291 1311 1331 1277.5 1297.5 1317.5 1337.5 Side Mode Suppression Ratio SMSR 30 db Transmitter OFF Output Power, each Lane P Off -30 dbm Tx OMA per Lane TxOMA -4.0 3.5 dbm Average Launched Power,per Lane -7 2.3 dbm Transmitter Reflectance -12 db Optical Return Loss Tolerance 20 db Relative Intensity Noise RIN 20 OMA -128 db/hz Output Eye Mask X1,X2,X3,Y1,Y2,Y3 Compliant with IEEE 802.3ba (0.25,0.4,0.45,0.25,0.28,0.4) Note (1). Total launch power consists 4 Channels operating at 10.3125Gbps. Note (2). Transmitter eye mask definition nm Note (2) 2 Revision: Draft
4. Specification of Receiver λ C Lane Center Wavelength(Range) 1284.5 1291 1297.5 1304.5 1311 1317.5 nm 1264.5 1271 1277.5 1324.5 1331 1337.5 Average Receiver Power per Lane P IN -13.7 +2.3 dbm Note(1) Damage Threshold, per lane P th +3.3 dbm Receiver Power OMA, per Lane RxOMA 3.5 dbm Receiver Sensitivity OMA, per lane S -11.5 dbm Stressed Receiver OMA, per lane SRS -9.6 dbm Return Loss -26 db Stressed Eye jitter, per lane 0.3 UI Note (1).The min. power is informative and not the principal indicator of signal strength. Note (2). Tested with PRBS 2 31-1, BER 1X10-12 Note(2) 3 Revision: Draft
5. Electrical Interface Characteristics Transmitter Total Supply Current I CC A ma Note (1) Differential line input Impedance R IN 90 100 110 Ohm Differential Data Input Swing VDT 200 800 mv p-p Note (2) Receiver Total Supply Current I CC B ma Note (1) Differential Data Output Swing VDR 200 800 mv p-p Note (2) Low speed signal Input Control Voltage LPMode, Reset and modseil VIL 0 0.8 V Input Control Voltage LPMode, Reset and modseil VIH 2 Vcc+0.3 V Output Voltage ModPrsL and IntL VOL 0 0.4 V Output Voltage ModPrsL and IntL VOH 2 Vcc+0.3 V Note (1). A (TX)+ B (RX) = 1.1A (Not include termination circuit) Note (2). CML Interface, AC coupled to 100ohm differential Load. 4 Revision: Draft
6. Pin Description QSFP Module Pad Layout (Top View) Host PCB Layout (Top View) 5 Revision: Draft
Module Electrical Pin Function Definition Pin Logic Symbol Name/Description Note 1 GND Ground [1] 2 CML-I Tx2n Transmitter Inverted Data Input 3 CML-I Tx2p Transmitter Non-inverted Data Input 4 GND Ground [1] 5 CML-I Tx4n Transmitter Inverted Data Input 6 CML-I Tx4p Transmitter Non-inverted Data Input 7 GND Ground [1] 8 LVTTL-I ModSelL Module Select 9 LVTTL-I ResetL Module Reset 10 Vcc Rx +3.3V Power Supply Receiver 11 LVCMOS-I/O SCL 2-Wire Serial Interface Clock [2] 12 LVCMOS-I/O SDA 2-Wire Serial Interface Data [2] 13 GND Ground [1] 14 CML-O Rx3p Receiver Non-Inverted Data Output 15 CML-O Rx3n Receiver Inverted Data Output 16 GND Ground [1] 17 CML-O Rx1p Receiver Non-Inverted Data Output 18 CML-O Rx1n Receiver Inverted Data Output 19 GND Ground [1] 20 GND Ground [1] 21 CML-O Rx2n Receiver Inverted Data Output 22 CML-O Rx2p Receiver Non-Inverted Data Output 23 GND Ground [1] 24 CML-O Rx4n Receiver Inverted Data Output 25 CML-O Rx4p Receiver Non-Inverted Data Output 26 GND Ground [1] 27 LVTTL-O ModPrsL Module Present [2] 28 LVTTL-O IntL Interrupt [2] 29 Vcc Tx +3.3V Power Supply Transmitter 30 Vcc1 +3.3V Power Supply 31 LVTTL-I LPMode Low Power Mode 32 GND Ground [1] 33 CML-I Tx3p Transmitter Non-inverted Data Input 34 CML-I Tx3n Transmitter Inverted Data Input 35 GND Ground [1] 36 CML-I Tx1p Transmitter Non-inverted Data Input 37 CML-I Tx1n Transmitter Inverted Data Input 38 GND Ground [1] Notes: 1. Module ground pins GND are isolated from the module case and chassis ground within the module. 2. Shall be pulled up with 4.7K-10Kohms to a voltage between 3.15V and 3.45V on the host board. 3. Please refer to SFF-8436 Fig. 3a for more information on interface circuit and power filtering network. 6 Revision: Draft
7. Low Speed Electrical Hardware Pins In addition to 2-wire serial interface, QCP-10G3B4QDR module has the following low speed pins for control and status: ModPrsL, IntL, LPMode, ModSelL, ResetL 7.1 ModPrsL ModPrsL is an output pin. When low, indicates the module is present. The ModPrsL is asserted Low when inserted and deasserted High when the module is physically absent from the host connector. 7.2 IntL IntL is an output pin. When Low, it indicates a possible module operational fault or a status critical to the host system. The source of the interrupt could be identified by using the 2-wire serial interface. 7.3 LPMode LPMode is a control pin. When High, it could be used to set the module in low power mode (<1.5W). This pin, along with Power_overide bit and Power_set bit in management interface could be used to avoid system power crash. QCP-10G3A4BDR, however consumes less than 1.5W. Therefore this pin takes no effect. 7.4 ModSelL ModSelL is an input signal. When held low by the host, the module responds to two-wire serial communication commands. The ModSelL signal allows multiple QSFP modules to be on a single two-wire interface bus. When the ModSelL signal is High, the module will not respond to or acknowledge any two-wire interface communication from the host. The ModSelL signal input pin is biased to a High state in the module. In order to avoid conflicts, the host system must not attempt two-wire interface communications within the ModSelL deassert time after any QSFP modules are de-selected. Similarly, the host must wait for the period of the ModSelL assert time before communicating with the newly selected module. The assert and deassert periods of different modules may overlap as long as the above timing requirements are met. 7.5 ResetL The ResetL signal is pulled to Vcc in the QSFP+ module. A logic low level on the ResetL signal for longer than the minimum pulse length (t_reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host will disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with the Data_Not_Ready bit negated. Note that on power-up (including hot insertion) the module will post this completion of reset interrupt without requiring a reset. 7 Revision: Draft
8. Outline Dimension 8 Revision: Draft
Appendix A. Document Revision Version No. Date Description Draft 2013-05-20 Preliminary datasheet 9 Revision: Draft