Is the Golden Age of Analog circuit Design Over? My answer: Yes, the golden age of pure analog circuit design is over. But, the golden age of mixed signal technology is coming. Some important works might be done in pure analog circuit design. performance increases in basic analog circuits. However, many important progresses will be accomplished by the mixed signal technology. ISSCC 2004 panel A. Matsuzawa 1
Current role of analog technology The current major role of analog is to sustain digital technologies. Digital communications, networkings, broadcastings, recordings, displays,.. Line I/F DAC DAC DAC DAC Pulse Shaping Side-stream Scramber & Trellis,Viterbi Symbol Encoder Gb Ethernet ADC ADC FFE Clock Recovery Slicer DFE Side-stream Descramber & Trellis, Viterbi decoder Analog circuit Digital circuit Echo Canceller 3-NEXTCanceller Variable Variable Gain Gain Amp. Amp. Analog Analog Filter Filter A to to D Converter Converter Digital Digital FIR FIR Filter Filter Viterbi Viterbi Error Error Correction Correction Data Out DVD recording Data In (Erroneous) Voltage Voltage Controlled Controlled Oscillator Oscillator Pickup signal Clock Clock Recovery Recovery Analog circuit Data Out (No error) Digital circuit ISSCC 2004 panel A. Matsuzawa 2
All systems will be integrated on mixed signal SoCs Global system design and optimization over digital and analog must be the most important works for the designer. The performance of SoC depends on it, greatly. Corroborations: Digital and analog System and circuit Global optimization: digital and analog Mixed signal SoC can integrate full DVD system K. Okamoto, et. al., ISSCC 2003. Encoder/Decoder Methods Analog Resolution # of Taps PRECODER ENCODER Digital Processing Method M-RANDOM BER Filter ADC PR EQUALIZER VITERBI DETECTOR DECODER NOISE Boost level # of Taps # of Path ISSCC 2004 panel A. Matsuzawa 3
Analog issue in mixed signal SoC 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 I/O Analog Digital 0.35um 0.25um 0.18um 0.13um If analog area can not be scaled along with digital, Chip cost will increase. Analog should be scaled! Otherwise, can t be integrated. Only the essential analog will survive Chip area Digital calibration realized drastic power and area saving! Wafer cost increases 1.3x 14b 100MS/s DAC 1.5V, 17mW, 0.1mm for one generation 2, 0.13um (0.35um : 1) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.35um 0.25um 0.18um 0.13um Chip cost Area: 1/50 Pd: 1/20 Y. Cong and R. L. Geiger, ISSCC 2003 ISSCC 2004 panel A. Matsuzawa 4
Digital give us the breakthrough of analog circuit Static accuracy: digital calibration Dynamic accuracy: timing adjustment High speed conv. : parallelism DLL timing adjustment Noise limitation 2 V n = kt C V kt 1 2 = n C M Conventional Over sampling M: over sampling ratio Enable low voltage operation 8bit, 20GHz, ADC 1.2V Dual-mode WCDMA/GPRS ΣΔ Modulator GPRS: 82dB, WCDMA: 70dB 0.13umCMOS, Pd=3mW K. Paulton, et al.,isscc 2003 A. Dezzani and E. Andre, ISSCC 2003 ISSCC 2004 panel A. Matsuzawa 5
Mixed signal egg Analog helps digital (digital network and storage ). Next step is digital should help analog. Mixed signal egg ( Analog yolk and white with digital shell) Digital shell Sustain the analog egg. Calibration and adjustment, Digital filtering Analog yolk and white Delicious and nutritious But, very delicate and fancy ISSCC 2004 panel A. Matsuzawa 6
Golden age designers for analog circuits will be over New golden designers age are expected They can work in; Digital technology and analog technology System, circuit, and device Electromagnetism as well as conventional circuit theory ISSCC 2004 panel A. Matsuzawa 7
Progress in A/D converter; video-rate 10b ADC ADC is a key for mixed signal technology. We have reduced the cost and power of ADC drastically; Power consumption: 1/2,000 Price: 1/200,000 1980 1982 1993 Now Conventional product World 1 st Monolithic World lowest power SoC Core Board Level (Disc.+Bip) 20W $ 8,000 Bipolar (3um) 2W $ 800 CMOS (1.2um) 30mW $ 2.00 CMOS (0.15um) 10mW $0.04 Our developed. Our developed. Our developed. ISSCC 2004 panel A. Matsuzawa 8
Progress in high-speed ADC High speed ADC has reduced its power and area down to be embedded. World fastest 6b ADC ISSCC 2000 ISSCC 2002 6b, 1GHz ADC 2W, 1.5um Bipolar 10 World fastest CMOS ADC 6b, 800MHz ADC 400mW, 2mm 2 0.25umCMOS ISSCC 1991 Pd/2 N [mw] World lowest Pd HS ADC 7b, 400MHz ADC 50mW, 0.3mm 2 0.18umCMOS 1 0.1 Reported Pd of CMOS ADCs 10mW/Gsps 1mW/Gsps This Work 1 order down 1 10 Conversion rate [x100msps] ISSCC 2004 panel A. Matsuzawa 9