April 2, 2004 STMicroelectronics L6262S BCD-MOS IC Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
STMicroelectronics L6262S BDC-MOS IC Structural Analysis Table of Contents 1 Overview 1.1 List of Figures and Tables 1.2 Introduction 1.3 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 Bond Pads 3.2 Passivation 3.3 Inter-Metal Dielectrics (IMD) and Pre-Metal Dielectric (PMD) 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors and Polysilicon 3.7 DMOS Transistors 3.8 Bipolar Transistors 3.9 Diode 3.10 Capacitors and Resistors 3.11 Isolation, Wells and Epi 4 Critical Dimensions 4.1 Horizontal Dimensions 4.2 Vertical Dimensions Report Evaluation Rev 1.0 April 2, 2004 09:48 \\vault-1\projwork\reports\stmicroelectronics\l6262s\sar\sar-0408-008
STMicroelectronics L6262S BCD-MOS IC Overview 1 Overview 1.1 List of Figures and Tables 2 Device Overview 2.1.1 Top and Bottom Package Photographs 2.1.2 Package X-Ray 2.1.3 Die Photograph 2.1.4 Die Markings 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Bond Pad 2.2.6 Gate Array 2.2.7 Bipolar Transistors 2.2.8 Single Poly MOS Capacitors 3 Process Analysis 3.0.1 General View of the STMicroelectronics L6262S 3.0.2 Die Edge 3.0.3 Die Seal 3.1.1 Bond Pad with Attached Bond 3.1.2 Bond Pad Edge 3.2.1 Passivation 3.3.1 Inter-Metal Dielectric 1 3.3.2 Inter-Metal Dielectric 2 3.3.3 Pre-Metal Dielectric 3.4.1 Minimum Pitch Metal 3 3.4.2 Minimum Metal 2 3.4.3 Minimum Pitch Metal 1 3.4.4 Metallization Vertical Dimensions Table 3.4.5 Metallization Horizontal Dimensions Table 3.5.1 Via 2 3.5.2 Via 1 and Contacts to Diffusion 3.5.3 Contacts to Polysilicon 3.5.4 Contacts to Diffusion 3.5.5 Via and Contact Dimensions Table 1-1 Rev 1.0 - Apr 2, 2004 10:24 \\edge\projwork\reports\stmicroelectronics\l6262s\sar\sar-0408-008.vsd
STMicroelectronics L6262S BCD-MOS IC Overview 3.6.1 NMOS Transistor 3.6.2 NMOS Transistor Close-Up 3.6.3 PMOS Transistor 3.7.1 Die Photograph Showing DMOS Transistor Locations 3.7.2 DMOS Transistor Cross-Section 1 3.7.3 DMOS Transistor Cross-Section 2 3.7.4 DMOS Transistor Highly Stained 3.7.5 DMOS Transistor Body Contact 3.8.1 Vertical NPN (Type 1) Transistors in Plan View 3.8.2 Vertical NPN (Type 2) Transistors in Plan View 3.8.3 Vertical NPN Transistors in Cross-Section (Type 1) 3.8.4 Base and Emitter Diffusions 1 3.8.5 Base and Emitter Diffusions 2 3.8.6 Emitter Contact and Diffusion 3.8.7 Base Contact and Diffusion 3.8.8 Collector Contact and Diffusion 3.8.9 NPN Transistor SCM Image 3.8.10 Emitter Base Region SCM Image 3.8.11 Vertical NPN Transistor in Cross-Section (Type 2) 3.8.12 Lateral PNP Transistors 3.8.13 Lateral PNP Transistor Cross-Section 3.8.14 Lateral PNP Emitter Collector 3.8.15 Lateral PNP Transistor Base and Collector 3.9.1 Diode Plan View 3.9.2 Diode Cross-Section 3.9.3 Diode Anode Region 3.9.4 Diode Anode Region Heavy Decoration Stain 3.10.1 Poly Capacitors in Plan View 3.10.2 Poly Capacitors Cross-Section 3.10.3 Diffusion Resistors in Plan View 3.10.4 Multi-Tapped P-Diffusion Resistors 3.11.1 LOCOS Isolation 3.11.2 Junction Isolation 3.11.3 Scanning Capacitance SCM Image 3.11.4 NMOS P-Well 1-2 Rev 1.0 - Apr 2, 2004 10:24 \\edge\projwork\reports\stmicroelectronics\l6262s\sar\sar-0408-008.vsd
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