New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links Min Wang, Intel Henri Maramis, Intel Donald Telian, Cadence Kevin Chung, Cadence 1
Agenda 1. Wide Eyes and More Bits 2. Interconnect Storage Potential (ISP) 3. Channel Analysis 4. PCI Express Case Study 5. Serial ATA Case Study 6. Summary & Conclusions 2
Agenda 1. Wide Eyes and More Bits 2. Interconnect Storage Potential (ISP) 3. Channel Analysis 4. PCI Express Case Study 5. Serial ATA Case Study 6. Summary & Conclusions 3
Serial Links: Changes and Challenges Embedded Clocks Eye Diagrams T_setup T_hold single cycle many cycles 4
But how many cycles? 260% error! 5
Do all links do that? No but it sure helps to find the ones that do! How can you find them? understand and quantify the link s Interconnect Storage Potential, or ISP 6
Agenda 1. Wide Eyes and More Bits 2. Interconnect Storage Potential (ISP) 3. Channel Analysis 4. PCI Express Case Study 5. Serial ATA Case Study 6. Summary & Conclusions 7
Interconnect Storage Imperfect Terminations Tx Rx Discontinuities All links must store a signal signals typically arrive at Rx 10 bit times after leaving Tx Unwanted energy often gets stored too this interferes with the SI of later bits (ISI) 8
Interconnect Storage Potential Unique for each interconnect Measures how long a bit s s energy stays in link Can be measured from pulse response Directly related to how many bits you need to simulate ISP Fingerprints an interconnect just like an I/V curve fingerprints a driver 9
ISP-based Design Methodology 1. Determine the ISP 2. Determine the Relevant Preamble 3. Calculate the Number of Bits 4. Perform High-Capacity Simulation We ll illustrate using both PCI Express and Serial ATA 10
1. Determine the ISP Model All effects Pulse Bit time, or less Plot Tx is best Model Pulse Plot Measure Fall to 5%, or mv tolerance 11
2. Determine Relevant Preamble Relevant if Bit here affects. bit here Preamble = ISP / bit_time In simple terms: how many bits fit in the ISP 12
3. Calculate Number of Bits Number of unique patterns: or #bits = (preamble) * 2 (preamble) #bits = (ISP*Gbps Gbps) ) * 2 (ISP* (ISP*Gbps) Pessimistic due to overlapping Encoding schemes reduce further 8b/10b removes power of 2 per 10 bits 13
4. High-Capacity Simulation Simulate #bits from step 3 For example, a 6 ns ISP on a 2.5 Gbps PCI Express link requires (6*2.5) * 2 (6*2.5) bits, or ~500k bits SPICE simulation typically used on these links does ~ 100 bits/hour would require over 200 days Hmm what good is a methodology like that!? 14
Agenda 1. Wide Eyes and More Bits 2. Interconnect Storage Potential (ISP) 3. Channel Analysis 4. PCI Express Case Study 5. Serial ATA Case Study 6. Summary & Conclusions 15
Introducing Channel Analysis New analysis capability in Allegro PCB SI FAST simulation of millions of bits Any differential topology, including pair-to to-pair crosstalk Tx/Rx can be DML, MacroModel,, IBIS, or Hspice Automatic PRBS, 8b/10b, random, or user-defined bits Tx Tx Rx Rx NOT typical circuit simulation 16
How Fast Is Channel Analysis? # bits CA * CA bits/sec SPICE + x faster 1,000 5 sec 200 10 hours 7,200 10,000 7 sec 1,400 4 days 51,000 100,000 20 sec 5,000 1.4 months 180,000 1,000,000 2.5 min 6,300 1 year 225,000 10,000,000 24.5 min 6,800 11 years 245,000 * PCI Express topology shown, IBM T41 laptop, Windows XP, 1.6 GHz Pentium M (proceeded by 7.5 min fingerprint characterization ) + SPICE simulation time of 100 bits/hour (0.03 bit/sec) based on sample transistor-level SerDes model in a typical 3.125 Gbps channel More tool detail at: http://www.cadence.com/webinars/webinars.aspx?xml=channel_analysis Alternative worst case pattern methodologies referenced in paper, not considered faster or as robust 17
What Mathematical Method Does CA Use? BIT PATTERN FFT ifft FFT Requires characterization of interconnect (its fingerprint ) Techniques have been used in other disciplines for years But new to digital PCB signal integrity 18
Agenda 1. Wide Eyes and More Bits 2. Interconnect Storage Potential (ISP) 3. Channel Analysis 4. PCI Express Case Study 5. Serial ATA Case Study 6. Summary & Conclusions 19
PCI Express Topology: 2.5 Gbps, SPICE Tx/Rx, cards & backplane, ~24 of trace, 2 connectors, 8- & 32-layer S-parameter vias 20
Methodology Steps ISP 1. Determine the ISP Simulation shows ISP = 9.6 ns 2. Determine Relevant Preamble 2.5 Gbps Preamble = 9.6 ns / 400 ps = 24 bits 3. Calculate Number of Bits For 8b/10b, #bits = 24x2 22 ~= 100 million 4. Perform High-Capacity Simulation Do Channel Analysis to see eye height 21
Verify Relevant Preamble Preamble Constant Test Pattern, 1 to 4 8b/10b pattern Preamble In which bit streams will the Test Pattern look the same? 22
24 Bits Confirms ISP Prediction 40 = 30, so 30 > Answer > 20, finding convergence yields 24 consistently 23
Eye Height vs Data Rate from CA eye eye height height (mv) (mv) 500 500 450 450 400 400 350 350 300 300 250 250 200 200 150 150 100 100 50 50 0 0 ISP ISP ISP ISP 1.E+02 1.E+02 1.E+03 1.E+03 1.E+04 1.E+04 1.E+05 1.E+05 1.E+06 1.E+06 1.E+07 1.E+07 1.E+08 1.E+08 1.E+09 1.E+09 1.E+10 1.E+10 # # bits bits simulated simulated Higher data rates take longer to converge Eye height stabilizes at #bits(isp# bits(isp) Significant error if ISP not reached 1.25 1.25 Gbps Gbps 2.5 2.5 Gbps Gbps 3.125 3.125 Gbps Gbps ISP ISP 24
Eye Height Error for 100 bits vs ISP 4 4 3 3 Eye Eye Height Height 2 Error 2 Error Factor Factor 1 1 0 0 1.25 1.25 2.5 2.5 Data Data Rate Rate (Gbps) (Gbps) 3.125 3.125 At 2.5 Gbps eye height at 100 bits is almost 2x wider than eye at ISP Error factor grows exponentially with increasing data rate Methodology is imperative at higher frequencies 25
But must we simulate to ISP? % Error in Eye Height % Error in Eye Height 50% 50% 45% 45% 40% 40% 35% 35% 30% 30% 25% 25% 20% 20% 15% 15% 10% 10% 5% 5% 0% 0% 1 2 3 4 5 6 7 1 2 3 4 5 6 7 % Error 0.5% 1.5% 2.5% 6.1% 13.9% 24.9% 48.4% % Error 0.5% 1.5% 2.5% 6.1% 13.9% 24.9% 48.4% Difference in orders of magnitude from #bits(isp) orders of magnitude from #bits(isp) At 2.5 Gbps,, eye height error is less than 3% within 3 orders of magnitude of #bits(isp# bits(isp) 26
Agenda 1. Wide Eyes and More Bits 2. Interconnect Storage Potential (ISP) 3. Channel Analysis 4. PCI Express Case Study 5. Serial ATA Case Study 6. Summary & Conclusions 27
Serial-ATA Simulation Topology Breakout MB trace Via Connector Cable measure here MacroModel Main & Boost Drivers P a c k a g e Caps not included in the simulation 3 differential pairs organized per spec; Gen I - 1.5 Gbps, Gen II - 3.0 Gbps 28
ISP Sim Shows Clean Channel Is Channel Analysis important on a channel like this? 29
Eye Contour Generated from CA and HSpice Simulations (@1.5 Gbps) 0.3 0.2 Eye contour (V) 0.1 0-0.1 CA 1000 PRBS (seconds simulation time) CA 10000 PRBS (seconds simulation time) CA 100000 PRBS (1 minute simulation time) CA 1000000 PRBS (3 minutes simulation time) CA 1000000 8b/10b pattern (3 minutes simulation time) 75-bit random pattern K28p5 pattern ( empirical WC pattern), repeat for 75 bits Lone-bit pattern (empirical WC pattern), repeat for 75 bits -0.2-0.3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 UI CA long PRBS simulations predict worse eye openings than short empirical WC pattern simulations 30
Eye Contour Generated from CA and HSpice Simulations (@3.0 Gbps) 0.3 0.2 Eye contour (V) 0.1 0-0.1 CA 1000 PRBS (seconds simulation time) CA 10000 PRBS (seconds simulation time) CA 100000 PRBS (1 minute simulation time) CA 1000000 PRBS (3 minutes simulation time) CA 1000000 8b/10b pattern (3 minutes simulation time) 75-bit random pattern K28p5 pattern ( empirical WC pattern), repeat for 75 bits Lone-bit pattern (empirical WC pattern), repeat for 75 bits -0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Higher frequency shows even greater difference between CA and empirical WC pattern simulations UI 31
Quantitative Difference: CA vs HSpice TD Fewer bits bits causes inside eye eye inaccuracy of of 50mV and and outside eye eye over 100 100 mv mv This quantifies the difference between two methodologies on S-ATA. However, do the tools correlate given the same input pattern? 32
Eye Correlation using CA and HSpice with same stimulus pattern (@1.5 Gbps) 0.4 0.3 0.2 Eye contour (volt) 0.1 0-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-0.2-0.3-0.4 Eye contour by CA UI Eye contour by HSpice TD sims Correlation based on 75-bit input pattern 33
Eye Correlation using CA and HSpice with same stimulus pattern (@3 Gbps) 0.3 0.2 Eye contour (volt) 0.1 0-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-0.2-0.3 Eye contour by CA UI Eye contour by HSpice TD sims Correlation based on 150-bit input pattern 34
Probability of Long Random Pattern Covering Worst-case Patterns 120% Coverage probability of long random pattern 100% 80% 60% 40% 20% 1000 bits 10000 bits 100000 bits 1000000 bits 0% 3 5 7 9 11 13 15 17 19 21 Worst case bit pattern length If WC pattern length <= 18 bits, the probability for a 1M bit PRBS pattern covering the WC pattern is 98.1% 35
Agenda 1. Wide Eyes and More Bits 2. Interconnect Storage Potential (ISP) 3. Channel Analysis 4. PCI Express Case Study 5. Serial ATA Case Study 6. Summary & Conclusions 36
Summary & Conclusions Introduced new methodologies and tools illustrated using PCI Express & S-ATAS Quantifying an ISP provides guidance on how to derive a meaningful eye diagram The speed of Channel Analysis allows more thorough pre-hardware link characterization improved results by 20% to 260% in cases shown Some correlation shown, more in Resources Many new discoveries still to come 37
Resources 11 items in Reference Materials section in paper Channel Analysis and MGH tools demo at Cadence booth 3 Agilent/Cadence CA correlation papers now available online at www.allegrosi.com Additional technical detail at http://www.allegrosi.com/optimize/advancedtechniques/mgh.asp 38
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