ECE 274 Digitl Logic Sequentil Logic Design Sequentil Logic Design Process Digitl Design 3.4 3.5 Digitl Design Chpter 3: Sequentil Logic Design -- Controllers Slides to ccompny the tetook Digitl Design, First Edition, y Frnk Vhid, John Wiley nd Sons Pulishers, 27. http://www.ddvhid.com Copyright 27 Frnk Vhid Instructors of courses requiring Vhid's Digitl Design tetook (pulished y John Wiley nd Sons) hve permission to modify nd use these slides for customry course-relted ctivities, suject to keeping this copyright notice in plce nd unmodified. These slides my e posted s unnimted pdf versions on pulicly-ccessile course wesites.. PowerPoint source (or pdf with nimtions) my not e posted to pulicly-ccessile wesites, ut my e posted for students on internl protected sites or distriuted directly to students y other electronic mens. Instructors my mke printouts of the slides ville to students for resonle photocopying chrge, without incurring roylties. Any other use requires eplicit permission. Instructors my otin PowerPoint source or otin specil use permissions from Wiley see http://www.ddvhid.com for informtion. Sequentil Logic Design Controller Design Five step controller design process Sequentil Logic Design Controller Design: Lser Timer Emple Step : Cpture the Alredy done Step 2: Crete rchitecture 2-it stte register (for 4 sttes) Input, output Net stte signls n, n Step 3: Encode the sttes Any encoding with ech stte unique will work Inputs: ; Outputs: = O ff = = = On On2 On3 inputs Comintionl s s Stte register n n outputs outputs 3 4
Sequentil Logic Design Controller Design: Lser Timer Emple (cont) Sequentil Logic Design Controller Design: Lser Timer Emple (cont) Step 4: Crete stte tle Inputs: ; Outputs: = O ff Step 5: Implement comintionl = = = On On2 On3 = s + s (note from the tle tht = if s = or s = ) n = s s + s s + ss + ss n = s s + ss n = s s + ss + ss n = s s + ss 5 6 Sequentil Logic Design Controller Design: Lser Timer Emple (cont) Sequentil Logic Design Understnding the Controller s Behvior Step 5: Implement comintionl (cont) Comintionl Logic inputs s s Stte register outp n n = O ff = = = On On2 On3 s s n n = O ff = = = On On2 On3 s s n n = O ff = = = On On2 On3 s s n n = s + s n = s s + ss n = s s + ss I nputs: st t e= st t e= st t e= 7 8 2
Sequentil Logic Design Simplifying Nottions s Assume unssigned output implicitly ssigned Sequentil circuits Assume unconnected clock inputs connected to sme eternl clock Sequentil Logic Design Controller Emple: Secure Cr Key Step Wit r= Inputs: ; Outputs: r K K2 K3 K4 r= r= r= r= Step 2 Comintionl (from erlier emple) r n2 n n s2 s s Stte register I nputs: ; O utputs: r r= Step 3 r= r= r= r= We ll omit Step 5 Step 4 9 Sequentil Logic Design Emple: Code Detector If we chnged the stte encoding for the secure cr key design to the following, would this ffect the finl output?. Yes 2. No Sequentil Logic Design In Clss Eercise: Button Press Synchronizer i Button press synchronizer controller o Step 3 I nputs: ; O utputs: r r= r= r= r= r= Wnt simple sequentil circuit tht converts utton press to single cycle durtion, regrdless of length of time tht utton ctully pressed We ssumed such n idel utton press signl in erlier emple, like the utton in the lser timer controller 2 3
Sequentil Logic Design Trnsitions Sequentil Logic Design Common Pitflls Regrding Trnsition Properties Is the following vlid?. Yes 2. No Only one condition should e true For ll trnsitions leving stte Else, which one? One condition must e true For ll trnsitions leving stte Else, where go? Cn verify using Boolen lger Only one condition true: AND of ech condition pir (for trnsitions leving stte) should equl proves pir cn never simultneously e true One condition true: OR of ll conditions of trnsitions leving stte) should equl proves t lest one condition must e true 3 4 Sequentil Logic Design Evidence tht Pitfll is Common Recll code detector We fied prolem with the trnsition conditions Do the trnsitions oey the two required trnsition properties? Consider trnsitions of stte Strt, nd the only one true property u= s u= r Wit Strt Red u= r * * (r ++g) r * (r ++g) = (* )r = ( *)*(r ++g) = (*)*r*(r ++g) = *r = *(r ++g) = *r*(r ++g) = = = rr +r+rg = + r+rg = r + rg = r(+g) Fils! Mens tht two of Strt s trnsitions could e true s g r Blue Green Red2 u= u= u= Intuitively: press red nd lue uttons t sme time: conditions r, nd (r ++g) will oth e true. Which one should e tken? Q: How to solve? A: r should e r g (likewise for, g, r) Note: As evidence the pitfll is common, we dmit the mistke ws not intentionl. A reviewer of the ook cught it. 5 Sequentil Logic Design Flip-Flop Set nd Reset Inputs Some flip-flops hve dditionl inputs Synchronous reset: clers Q to on net clock edge Asynchronous reset: cler Q to immeditely (not dependent on clock edge) Emple timing digrm shown 6 4
Sequentil Logic Design Initil Stte of Controller Sequentil Logic Design Non-Idel Flip-Flop Behvior All our s hd initil stte But our sequentil circuit designs did not Cn ccomplish using flip-flops with reset/set inputs Shown circuit initilizes flip-flops to Circuits typiclly hve power on reset circuitry to utomticlly reset circuit on power up Inputs: ; Outputs: = Off = On = On2 Comintionl s s Stte register n n = On3 Cn t chnge flip-flop input too close to clock edge Setup time: time tht D must e stle efore edge Else, stle vlue not present t internl ltch Hold time: time tht D must e held stle fter edge Else, new vlue doesn t hve time to loop round nd stilize in internl ltch Setup time violtion D Q D Q reset Q R Q S Leds to oscilltion! 7 8 Sequentil Logic Design Metstility Sequentil Logic Design Metstility Violting setup/hold time cn led to d sitution known s metstle stte Metstle stte: Any flip-flop stte other thn stle or Eventully settles to one or other, ut we don t know which For internl circuits, we cn mke sure oserve setup time But wht if input comes from eternl (synchronous) source, e.g., utton press? Prtil solution Insert synchronizer flip-flop for synchronous input Specil flip-flop with smll setup/hold time Doesn t completely prevent metstility One flip-flop doesn t completely solve prolem How out dding more synchronizer flip-flops? Helps, ut just decreses proility of metstility So how solve completely? Cn t! My e unsettling to new designers. But we just cn t gurntee design tht won t ever e metstle. We cn just minimize the men time etween filure (MTBF) -- numer often given long with circuit Proility of flip-flop eing metstle is i l o w low low incredily l o w synchronizers 9 2 5