All Devices Discontinued!

GAL RA Device Datasheet June All Devices Discontinued! Product Change Notification (PCN) #9- has been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN GALRA GALRAB-LP GALRAB-5LP GALRAB-LP GALRAB-3LP GALRAB-LP GALRAB-7LJ Discontinued PCN#9- GALRAB-LJ GALRAB-5LJ GALRAB-LJ GALRAB-3LJ GALRAB-LJ 5555 N.E. Moore Ct. Hillsboro, Oregon 97-6 Phone (53) 6- FAX (53) 6-37 nternet: http://www.latticesemi.com

GALRA High-Speed Asynchronous E CMOS PLD Generic Array Logic Features Functional Block Diagram HGH PERFORMANCE E CMOS TECHNOLOGY 7.5 ns Maximum Propagation Delay Fmax = 3.3 MHz 9 ns Maximum from Clock nput to Data Output TTL Compatible ma Outputs UltraMOS Advanced CMOS Technology 5% to 75% REDUCTON N POWER FROM BPOLAR 75mA Typical cc ACTVE PULL-UPS ON ALL PNS E CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells % Tested/% Yields High Speed Electrical Erasure (< ms) Year Data Retention TEN OUTPUT LOGC MACROCELLS ndependent Programmable Clocks ndependent Asynchronous Reset and Preset Registered or Combinatorial with Polarity Full Function and Parametric Compatibility with PALRA PRELOAD AND POWER-ON RESET OF ALL REGSTERS % Functional Testability APPLCATONS NCLUDE: State Machine Control Standard Logic Consolidation Multiple Clock Logic Designs ELECTRONC SGNATURE FOR DENTFCATON Description The GALRA combines a high performance CMOS process with electrically erasable (E ) floating gate technology to provide the highest speed performance available in the PLD market. Lattice Semiconductor s E CMOS circuitry achieves power levels as low as 75mA typical CC which represents a substantial savings in power when compared to bipolar counterparts. E technology offers high speed (<ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell () to be configured by the user. The GALRA is a direct parametric compatible CMOS replacement for the PALRA device. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. Therefore, Lattice Semiconductor delivers % field programmability and functionality of all GAL products. n addition, erase/write cycles and data retention in excess of years are specified. NC PL 5 7 9 PLCC PL NC GND NC Vcc OE GALRA Top View PROGRAMMABLE AND-ARRAY (X) Pin Configuration ALL DEVCES 6 5 9 6 3 NC PL GND 6 DP GAL RA DSCONTNUED OE 3 Copyright 997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTCE SEMCONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97, U.S.A. July 997 Tel. (53) 6-; --LATTCE; FAX (53) 6-556; http://www.latticesemi.com Vcc OE ra_

Specifications GALRA GALRA Ordering nformation Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # 7.5 3 9 GALRAB-7LJ GALRAB-LP GALRAB-LJ 5 7 5 GALRAB-5LP GALRAB-5LJ GALRAB-LP GALRAB-LJ 3 3 GALRAB-3LP ndustrial Grade Specifications GALRAB-3LJ T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GALRAB-LP Part Number Description GALRAB L = Low Power Device Name Speed (ns) Power GALRAB-LJ XXXXXXXX _ XX X X X -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC Package Package ALL DEVCES Grade Package Blank = Commercial = ndustrial P = Plastic DP J = PLCC DSCONTNUED

Specifications GALRA Output Logic Macrocell () Asynchronous Reset and Preset The GALRA consists of D flip-flops with individual asynchronous programmable reset, preset and clock product terms. The sum of four product terms and an Exclusive-OR provide a programmable polarity D-input to each flip-flop. An output enable term combined with the dedicated output enable pin provides tri-state control of each output. Each has a flip-flop bypass, allowing any combination of registered or combinatorial outputs. The GALRA has dedicated input pins and programmable /O pins, which can be either inputs, outputs, or dynamic / O. Each pin has a unique path to the logic array. All macrocells have the same type and number of data and control product terms, allowing the user to exchange /O pin assignments without restriction. ndependent Programmable Clocks An independent clock control product term is provided for each GALRA macrocell. Data is clocked into the flip-flop on the active edge of the clock product term. The use of individual clock control product terms allow up to ten separate clocks. These clocks can be derived from any pin or combination of pins and/or feedback from other flip-flops. Multiple clock sources allow a number of asynchronous register functions to be combined into a single GALRA. This allows the designer to combine discrete logic functions into a single device. Programmable Polarity The polarity of the D-input to each macrocell flip-flop is individually programmable to be active high or low. This is accomplished with a programmable Exclusive-OR gate on the D-input of each flipflop. The polarity of the pin is active low when XOR bit is programmed (or zero) and is active high when XOR bit is erased (or one). Because of the inverted output buffer, the XOR gate output node is opposite polarity from the pin. t should be noted that the programmable polarity only affects the data latched into the flip-flop on the active edge of the clock product term. The reset, preset and preload will alter the state of the flip-flop independent of the state of programmable polarity bit. The ability to program the active polarity of the D-inputs can be used to reduce the total number of product terms used, by allowing the DeMorganization of the logic functions. This logic reduction is accomplished by the logic compiler, and does not require the designer to define the polarity. Output Enable The output of each GALRA macrocell is controlled by the AND ing of an independent output enable product term and a common active low output enable pin (pin 3 on DP package / pin 6 on PLCC package). The output is enabled while the output enable product term is active and the output enable pin is low. This output control structure allows several output enable alternatives. Each GALRA macrocell has an independent asynchronous reset and preset control product term. The reset and preset product terms are level sensitive, and will hold the flip-flop in the reset or preset state while the product term is active independent of the clock or D-inputs. t should be noted that the reset and preset term alter the state of the flip-flop whose output is inverted by the output buffer. A reset of the flip-flop will result in the output pin becoming a logic high and a preset will result in a logic low. RESET PRESET FUNCTON Registered function of data product term Reset register to "" (device pin = "") Preset register to "" (device pin = "") Register-bypass (combinatorial output) Combinatorial Control The register in each GALRA macrocell may be bypassed by asserting both the reset and preset product terms. While both product terms are active the flip-flop is bypassed and the D- input is presented directly to the inverting output buffer. This provides the designer the ability to dynamically configure any macrocell as a combinatorial output, or to fix the macrocell as combinatorial only by forcing both reset and preset product terms active. Some logic compilers will configure macrocells as registered or combinatorial based on the logic equations, others require the designer to force the reset and preset product terms active for combinatorial macrocells. Parallel Flip-Flop Preload The flip-flops of a GALRA can be reset or preset from the /O pins by applying a logic low to the preload pin (pin on DP package / pin on PLCC package) and applying the desired logic level to each /O pin. The /O pins must remain valid for the preload setup and hold time. All flip-flops are reset or preset during preload, independent of all other inputs. ALL DEVCES A logic low on an /O pin during preload will preset the flip-flop, a logic high will reset the flip-flop. The output of any flip-flop to be preloaded must be disabled. Enabling the output during preload will maintain the current logic state. t should be noted that the preload alters the state of the flip-flop whose output is inverted by the output buffer. A reset of the flip-flop will result in the output pin becoming a logic high and a preset will result in a logic low. Note that the common output enable pin will disable all outputs of the GALRA when held high. DSCONTNUED 3

Specifications GALRA Output Logic Macrocell Diagram PL OE PL OE XOR (n) XOR (n) AR PL PD D AR PL PD Output Logic Macrocell Configuration (Registered With Polarity) ALL DEVCES Output Logic Macrocell Configuration (Combinatorial With Polarity) OE D AP AP Q Q DSCONTNUED XOR (n)

Specifications GALRA GALRA Logic Diagram DP (PLCC) Package Pinouts () (3) 3 () (5) 5 (6) 6 (7) 7 (9) () 9 () () (3) PL 3 6 6 9 96 56 6 9 5 56 36 6 3 36 XOR - 3 XOR - 3 XOR - 3 XOR - 33 XOR - 3 XOR - 35 XOR - 36 ALL DEVCES XOR - 37 XOR - 3 DSCONTNUED XOR - 39 3 (7) (6) (5) () 9 (3) () 7 () 6 (9) 5 () (7) 3 (6) 6-USER ELECTRONC SGNATURE FUSES 3, 3,...... 37, 373 Byte7 Byte6...... Byte Byte OE MSB LSB 5

Specifications GALRAB Absolute Maximum Ratings () Recommended Operating Conditions Supply voltage V CC... -.5 to +7V nput voltage applied... -.5 to V CC +.V Off-state output voltage applied... -.5 to V CC +.V Storage Temperature... -65 to 5 C Ambient Temperature with Power Applied... -55 to 5 C.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Commercial Devices: Ambient Temperature (T A )... to +75 C Supply voltage (V CC ) with Respect to Ground... +.75 to +5.5V ndustrial Devices: Ambient Temperature (T A )...- to +5 C Supply voltage (V CC ) with Respect to Ground... +.5 to +5.5V Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN. TYP. 3 MAX. UNTS VL nput Low Voltage Vss.5. V VH nput High Voltage. Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX.) - µa H nput or /O High Leakage Current 3.5V VN VCC µa VOL Output Low Voltage OL = MAX. Vin = VL or VH.5 V VOH Output High Voltage OH = MAX. Vin = VL or VH. V OL Low Level Output Current ma OH High Level Output Current -3. ma OS Output Short Circuit Current VCC = 5V VOUT =.5V T A = 5 C -5-35 ma COMMERCAL CC Operating Power VL =.5V VH = 3.V L -7/-/-5/-/-3 75 ma NDUSTRAL ALL DEVCES Supply Current ftoggle = 5MHz Outputs Open CC Operating Power VL =.5V VH = 3.V L - 75 ma Supply Current DSCONTNUED ftoggle = 5MHz Outputs Open ) The leakage current is due to the internal pull-up resistor on all pins. See nput Buffer section for more information. ) One output at a time for a maximum duration of one second. Vout =.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not % tested. 3) Typical values are at Vcc = 5V and TA = 5 C 6

Specifications GALRAB AC Switching Characteristics Over Recommended Operating Conditions PARAM. TEST COND. DESCRPTON tpd A nput or /O to Combinatorial Output 7.5 5 3 ns tco A Clock to Output Delay 9 5 3 ns tsu Setup Time, nput or Fdbk before Clk 3 7 ns th Hold Time, nput or Fdbk after Clk 3 3 3 ns fmax 3 A Maximum Clock Frequency with 3.3 66.7 5. 33.3. MHz External Feedback, /(tsu + tco) A Maximum Clock Frequency with 3.3 7. 5..7 5. MHz No Feedback twh Clock Pulse Duration, High 6 7 ns twl Clock Pulse Duration, Low 6 7 ns ten/tdis B,C or /O to Output Enabled / Disabled 7.5 5 3 ns ten/tdis B,C OE to Output Enabled / Disabled 5 9 5 ns tar/tap A nput or /O to Async. Reset / Preset 9 5 3 ns tarw/tapw Async. Reset / Preset Pulse Duration 6 5 ns tarr/tapr Async. Reset / Preset Recovery Time 7 7 ns twp Preload Pulse Duration 5 3 ns tsp Preload Setup Time 5 7 5 5 ns thp Preload Hold Time 5 7 5 5 ns ) Refer to Switching Test Conditions section. ) Refer to fmax Descriptions section. SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5.V, V =.V C /O /O Capacitance pf V CC = 5.V, V /O =.V *Characterized but not % tested. MN. COM COM COM COM / ND COM -7 MAX. MN. - MAX. MN. -5 MAX. MN. ALL DEVCES Capacitance (T A = 5 C, f =. MHz) - MAX. MN. -3 MAX. UNTS DSCONTNUED 7

Specifications GALRA Switching Waveforms NPUT or /O FEEDBACK COMBNATORAL OUTPUT NPUT or /O FEEDBACK OUTPUT CLK PL ALL /O PNS OE OUTPUT Combinatorial Output nput or /O to Output Enable/Disable twh Clock Width twp tsp Parallel Preload tdis tdis thp OE to Enable / Disable VALD NPUT tpd twl ten ten NPUT or /O FEEDBACK CLK REGSTERED OUTPUT NPUT or /O FEEDBACK DRVNG AP or AR CLK NPUT or /O FEEDBACK Q-OUTPUT OF REGSTER REGSTERED OUTPUT PN Q-OUTPUT OF REGSTER REGSTERED OUTPUT PN VALD CLOCK Registered Output Asynchronous Reset and Preset ALL DEVCES VALD NPUT VALD NPUT tsu tapw/arw tco tapr/arr Asynchronous Reset and Preset Recovery th VALD CLOCK VALD NPUT DSCONTNUED tar tap

Specifications GALRA fmax Descriptions CLK CLK LOGC ARRAY tsu fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. nput Pulse Levels GND to 3.V nput Rise and -7/- ns % 9% Fall Times -5/-/-3 3ns % 9% nput Timing Reference Levels.5V Output Timing Reference Levels.5V Output Load See Figure 3-state levels are measured.5v from steady-state active level. Output Load Conditions (see figure) REGSTER Switching Test Conditions tco Test Condition R R CL A 7Ω 39Ω 5pF B Active High 39Ω 5pF Active Low 7Ω 39Ω 5pF C Active High 39Ω 5pF Active Low 7Ω 39Ω 5pF LOGC ARRAY FROM OUTPUT (O/Q) UNDER TEST fmax with No Feedback Note: fmax with no feedback may be less than /(twh + twl). This is to allow for a clock duty cycle of other than 5%. ALL DEVCES R +5V REGSTER C * L TEST PONT *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE DSCONTNUED R 9

Specifications GALRA Electronic Signature Device Programming An electronic signature word is provided in every GALRA device. t contains 6 bits of reprogrammable memory that contains user defined data. Some uses include user D codes, revision numbers, pattern identification or inventory control codes. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature bits if programmed to any value other then zero() will alter the checksum of the device. Security Cell A security cell is provided in every GALRA device as a deterrent to unauthorized copying of the device pattern. Once programmed, this cell prevents further read access of the device pattern information. This cell can be only be reset by reprogramming the device. The original pattern can never be examined once this cell is programmed. The Electronic Signature is always available regardless of the security cell state. Latch-Up Protection GALRA devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching. GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. nput Buffers GALRA devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance and present a much lighter load to the driving logic than traditional bipolar devices. GALRA input buffers have active pull-ups within their input structure. As a result, unused inputs and /Os will float to a TTL high (logical ). Lattice Semiconductor recommends that all unused inputs and tri-stated /O pins be connected to another active input, Vcc, or GND. Doing this will tend to improve noise immunity and reduce cc for the device. nput Current (ua) - - -6 Typical nput Pull-up Characteristic.. 3.. 5. nput Voltage (Volts) ALL DEVCES DSCONTNUED

Specifications GALRA Power-Up Reset Vcc Vcc (min.) Circuitry within the GALRA provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, µs MAX). As a result, the state on the registered output pins (if they are enabled) will be high on power-up, because of the inverting buffer on the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown to the right. Because of the asynchronous PN PN Vcc ESD Protection Circuit ESD Protection Circuit Active Pull-up Circuit Vref Vcc CLK NTERNAL REGSTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGSTER nput/output Equivalent Schematics (Vref Typical = 3.V) Vcc tpr twl tsu nternal Register Reset to Logic "" Device Pin Reset to Logic "" nature of system power-up, some conditions must be met to provide a valid power-up reset of the GALRA. First, the Vcc rise must be monotonic. Second, the clock input must be at a static TTL level as shown in the diagram during power up. The registers will reset within a maximum of µs. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Feedback Tri-State Control Vcc Active Pull-up Circuit ALL DEVCES Data Output Vref Feedback (To nput Buffer) PN (Vref Typical = 3.V) DSCONTNUED PN Typical nput Typical Output

Specifications GALRA GALRAB-7/-: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc... Normalized Tpd Normalized Tpd..9..5.75 5. 5.5 5.5.3...9..7 Supply Voltage (V) Normalized Tpd vs Temp Temperature (deg. C) Normalized Tco Normalized Tco..9..5.75 5. 5.5 5.5.3...9..7 Supply Voltage (V) Normalized Tco vs Temp Temperature (deg. C) Normalized Tsu...6.5.75 5. 5.5 5.5 Supply Voltage (V) Normalized Tsu vs Temp -55-5 5 5 75 5-55 -5 5 5 75 5-55 -5 5 5 75 5 Delta Tpd (ns) Delta Tpd (ns) -.5 - Delta Tpd vs # of Outputs Switching -.5 3 5 6 7 9 6 Number of Outputs Switching Delta Tpd vs Output Loading RSE FALL - - 5 5 Delta Tco (ns) -.5 - -.5 Normalized Tsu Delta Tco vs # of Outputs Switching ALL DEVCES Delta Tco (ns).6....6-3 5 6 7 9 Number of Outputs Switching Delta Tco vs Output Loading 6 RSE FALL - - 5 5 Output Loading (pf) Output Loading (pf) Temperature (deg. C) DSCONTNUED

Specifications GALRA GALRAB-7/-: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh. 5 3.75 Vol (V) Normalized cc Delta cc (ma).6.. 3...9 ol (ma) Normalized cc vs Vcc..5.75 5. 5.5 5.5 6 Supply Voltage (V) Delta cc vs Vin ( input)..7..7..7 3. 3.7 Vin (V) Voh (V) Normalized cc ik (ma) 3 3 5 6 7.3...9..7 3 5-55 oh(ma) Normalized cc vs Temp -5 5 75 Temperature (deg. C) nput Clamp (Vik) ALL DEVCES 6 7 Vik (V) 5 9 -. -.5 -. -.5. Voh (V) Normalized cc 3.5 3.5 3... 3.. oh(ma) Normalized cc vs Freq...3....9. 5 5 75 Frequency (MHz) DSCONTNUED 3

Specifications GALRA GALRAB-5/-/-3: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd...9..5.75 5. 5.5 5.5.3...9..7-55 Supply Voltage (V) PT H->L PT L->H Normalized Tpd vs Temp -5 PT H->L PT L->H 5 5 Temperature (deg. C) Delta Tpd (ns) 75 -. -. -.6 -. - 9 5 Normalized Tco Normalized Tco..5.95.9.5.75 5. 5.5 5.5.3...9..7-55 Delta Tpd vs # of Outputs Switching Supply Voltage (V) RSE FALL Normalized Tco vs Temp -5 RSE FALL -. 3 5 6 7 9 Number of Outputs Switching RSE FALL 5 5 75 9 Temperature (deg. C) 5 Normalized Tsu Normalized Tsu.6....6..5.75 5. 5.5 5.5..3...9..7.6-55 Delta Tco vs # of Outputs Switching ALL DEVCES Delta Tpd (ns) 6 - Delta Tpd vs Output Loading RSE FALL - 5 5 5 3 Output Loading (pf) Delta Tco (ns) Delta Tco (ns) -. -. -.6 -. - RSE FALL Number of Outputs Switching Supply Voltage (V) Normalized Tsu vs Temp -5 -. 3 5 6 7 9 6 - - Delta Tco vs Output Loading RSE FALL 5 5 5 3 Output Loading (pf) 5 5 75 9 Temperature (deg. C) DSCONTNUED 5

Specifications GALRA GALRAB-5/-/-3: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh 3 5 3.75 Delta cc (ma) Normalized cc Vol (V).5.5.5... 6.. ol (ma) Normalized cc vs Vcc....9..5.75 5. 5.5 5.5 5 3 Supply Voltage (V) Delta cc vs Vin ( input)..5..5..5 3. 3.5. Vin (V) Voh (V) Normalized cc ik (ma) 3... 3.. 5. 6....9. 3 5-55 oh(ma) Normalized cc vs Temp -5 5 5 75 Temperature (deg. C) nput Clamp (Vik) ALL DEVCES 6 7 Vik (V) 5 9 -. -.. Voh (V) Normalized cc 3.65 3.5 3.375 3.5... 3....3....9 oh(ma) Normalized cc vs Freq.. 5 5 75 Frequency (MHz) DSCONTNUED 5