L4902A DUAL 5 REGULATOR WITH RESET AND DISABLE DOUBLE BATTERY OPERATING OUTPUT CURRENTS : I01 = 300 ma I02 = 300 ma FIXED PRECISION OUTPUT OLTAGE 5 ± 2 % RESET FUNCTION CONTROLLED BY INPUT OLTAGE AND OUTPUT 1 OLTAGE RESET FUNCTION EXTERNALLY PRO- GRAMMABLE TIMING RESET OUTPUT LEEL RELATED TO OUT- PUT 2 OUTPUT 2 INTERNALLY SWITCHED WITH ACTIE DISCHARGING OUTPUT 2 DISABLE LOGICAL INPUT LOW LEAKAGE CURRENT, LESS THAN 1µA AT OUTPUT 1 RESET OUTPUT NORMALLY HIGH INPUT OEROLTAGE PROTECTION UP TO 60 OUTPUT TRANSISTORS SOA PROTECTION SHORT CIRCUIT AND THERMAL OER- LOAD PROTECTION DESCRIPTION The L4902A is a monolithic low drop dual 5 regulator designed mainly for supplying microprocessor systems Reset and data save functions and remote switch on/off control can be realized PIN CONNECTION HEPTAWATT (ertical) ORDERING NUMBER : L4902A June 2000 1/9
PIN FUNCTIONS N Name Function 1 Input 1 Regulators Common Input 2 Timing Capacitor BLOCK DIAGRAM SCHEMATIC DIAGRAM If Reg 2 is switched-on the delay capacitor is charged with a 5µA constant current When Reg 2 is switched-off the delay capacitor is discharged 3 Disable Input A high level (> DT ) disable output Reg 2 4 GND Common Ground 5 Reset Output When pin 2 reaches 5 the reset output is switched high Therefore t RD = C t ( 5 10µA ) ; t RD (ms) = C t (nf) 6 Output 2 5 300mA Regulator Output Enabled if o 1 > RT DISABLE INPUT < DT and IN > IT If Reg 2 is switched-off the C 02 capacitor is discharged 7 Output 1 5 300mA Low leakage (in switch-off condition) output 2/9
ABSOLUTE MAXIMUM RATINGS Symbol Parameter alue Unit IN DC Input oltage Transient Input Overvoltage (t = 40ms) I o Output Current Internally Limited T stg, T j Storage and Junction Temperature 40 to 150 C 28 60 THERMAL DATA Symbol Parameter alue Unit R th j-case Thermal Resistance Junction-case Max 4 C/W ELECTRICAL CHARACTERISTICS (IN = 144, Tamb = 25 o C unless otherwise specified)) Symbol Parameter Test Conditions Min Typ Max Unit i DC Operating Input oltage 24 01 Output oltage 1 R Load 1kΩ 495 505 515 02 H Output oltage 2 HIGH R Load 1kΩ 01 01 5 01 02 L Output oltage 2 LOW I 02 = 5mA 01 I 01 Output Current 1 max 01 = 100m 300 ma I L01 Leakage Output 1 Current IN = 0, 01 3 1 µa I 02 Output Current 2 max 02 = 100m 300 ma i01 Output 1 Dropout oltage (*) I 01 = 10mA I 01 = 100mA I 01 = 300mA 07 08 11 08 1 14 IT Input Threshold oltage 01 + 12 64 01 + 17 ith Input Threshold oltage Hyst 250 m 01 Line Regulation 1 7 < IN < 24, I 01 = 5mA 5 50 m 02 Line Regulation 2 7 < IN < 24, I 02 = 5mA 5 50 m 01 Load Regulation 1 5mA < I 01 < 300mA 40 80 m 02 Load Regulation 2 5mA < I 02 < 300mA 50 80 m I Q Quiescent Current I 01 = I 02 5mA ma 0 < IN < 13 7 < IN < 13 02 LOW 7 < IN < 13 02 HIGH 45 27 16 65 45 35 RT Reset Threshold oltage 02 015 49 02 005 RTH Reset Threshold Hysteresis 30 50 80 m RH Reset Output oltage HIGH I R = 500µA 02 1 412 02 RL Reset Output oltage LOW I R = 1mA 025 04 t RD Reset Pulse Delay C t = 10nF 3 5 11 ms t d Timing Capacitor Discharge Time C t = 10nF 20 µs DT 02 Disable Threshold oltage 125 24 I D 02 Disable Input Current D 04 150 µa D 24 30 µa 01 T Thermal Drift 20 C T amb 125 C 02 T Thermal Drift 20 C T amb 125 C SR1 Supply oltage Rejection f = 100Hz R = 05 Io = 100mA 03 08 03 08 m/ C m/ C 50 84 db SR2 Supply oltage Rejection 50 80 db * The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25 m under constant output current condition 3/9
TEST CIRCUIT APPLICATION INFORMATION In power supplies for µp systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to save data when the primary supply is removed The L4902A makes it very easy to supply such equipments ; it provides two voltage regulators (both 5 high precision) with common inputs plus a reset output for the data save function and a Reg 2 disable input CIRCUIT OPERATION (see Figure 1) After switch on Reg 1 saturates until 01 rises to the nominal value When the input reaches IT and the output 1 is higher than RT the output 2 (02) switches on and the reset output (R) also goes high after a pro- Figure 1 grammable time TRD (timing capacitor) 02 and R are switched together at low level when one of the following conditions occurs : - a high level ( DT) is applied on pin 3 ; - an input overvoltage ; - an overload on the output 1 (01 RT) ; - a switch off (IN IT - ITH) ; and they start again as before when the condition is removed An overload on output 2 does not switch Reg 2, and does not influence Reg 1 The 01 output features : - 5 internal reference without voltage divider between the output and the error comparator - very low drop series regulator element utilizing current mirrors permit high output impedance and then very low leakage current even in power down condition 4/9
This output may therefore be used to supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery The 02 output can supply other non essential 5 circuits which may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value The reset output can be used as a "POWER DOWN INTERRUPT", permitting RAM access only in correct power conditions, or as a "BACK-UP ENABLE" to transfer data into in a N SHADOW MEMORY Figure 2 Figure 3 : PC Board Component Layout of Figure 2 when the supply is interrupted The disable function can be used for remote on/off control of circuits connected to the 02 output APPLICATION SUGGESTIONS Figure 2 illustrate how the L4902A s disable input may be used in a CMOS µcomputer application The 01 regulator (low consumption) supply permanently a CMOS time of day clock and a CMOS µcomputer chip with volatile memory 02 output, supplying non-essential circuits, is turned OFF under control of a µp unit 5/9
Figure 4 Figure 5 Configurations of this type are used in products where the OFF switch is part of a keyboard scanned by a micro which operates continuously even in the OFF state Another application for the L4902A is supplying a shadow-ram microcomputer chip (SGS M38SH72 for example) where a fast N memory is backed up on chip by a EEPROM when a low level on the reset output occurs By adding two CMOS-SCHMIDT-TRIGGER and few external components, also a watch dog function may be realized (see Figure 5) During normal operation the microsystem supplies a periodical pulse waveform ; if an anomalous condition occours (in the program or in the system), the pulses will be absent and the disable input will be activated after a settling time determined by R1 C1 In this condition all the circuitry connected to 02 will be disabled, the system will be restarted with a new reset front The disable of 02 prevent spurious operation during microprocessor malfunctioning 6/9
Figure 6 : Quiescent Current versus Output ICurrent Figure 7 : Quiescent Current versus Input oltage Figure 8 : Supply oltage Rejection Regulators 1 and 2 versus Input Ripple Frequence 7/9
DIM mm inch MIN TYP MAX MIN TYP MAX A 48 0189 C 137 0054 D 24 28 0094 0110 D1 12 135 0047 0053 E 035 055 0014 0022 E1 07 097 0028 0038 F 06 08 0024 0031 F1 09 0035 G 234 254 274 0095 0100 0105 G1 488 508 528 0193 0200 0205 G2 742 762 782 0295 0300 0307 H2 104 0409 H3 1005 104 0396 0409 L 167 169 171 0657 0668 0673 L1 1492 0587 L2 2124 2154 2184 0386 0848 0860 L3 2227 2252 2277 0877 0891 0896 L4 129 0051 L5 26 28 3 0102 0110 0118 L6 151 155 158 0594 0610 0622 L7 6 635 66 0236 0250 0260 L9 02 0008 M 255 28 305 0100 0110 0120 M1 483 508 533 0190 0200 0210 4 40 (typ) Dia 365 385 0144 0152 A C L5 D1 L L1 L2 L3 D Heptawatt H3 H1 OUTLINE AND MECHANICAL DATA E M1 M F E1 E G G1 G2 L9 H2 4 Dia L7 L4 H2 F1 F L6 HEPTAMEC 8/9
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