FACULTY OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING COURSE PLAN Course Code : CS0003 Course Title : DIGITAL COMPUTER FUNDAMENTALS Semester : III Course Time : Jun 204 to Nov 204 Period Timing 8.45 9.35 AM 2 9.35 0.25 AM 3 0.35.25 AM 4.25 AM 2.5 PM 5.30 2.20 PM 6 2.20 3.0 PM Location : SRM University, Kattankulathur (Annexure) Technology Park Faculty Details Sec. Name Day Period Mail id 3 3 4 A MRS.G.SIVAGAMI 5 3 sivagami.g@ktr.srmuniv.ac.in 3 2 B MS.TYN.NAGAMALLISWARI 4 3 nagamalleswari.t@ktr.srmuniv.ac.in 2,5 C MR.S.JAGADEESAN 5 3 jagadeesan.s@ktr.srmuniv.ac.in 2 D MS.JV.VIDHYA 5 5 vidhya.j@ktr.srmuniv.ac.in 3 E MS.C.SINDHU 5 4 sindhu.c@ktr.srmuniv.ac.in F MRS.S.SARANYA 3 2,4 saranya.s@ktr.srmuniv.ac.in
5 6 6 G H I J K L M MS.KIRUTHIKA DEVI MS.D.VANUSHA MRS.KANMANI SIVAGAR Mrs.A.JACKULIN MAHARIBA Mrs.C.JAYAVARTHINI MRS.G.ABIRAMI MR.T.SENTHIL KUMAR 2 4 4 2 6 5 3 2 5 3 4 2,6 3 3,3 2 4 4 6 2 2 4 3 kiruthikadevi.s@ktr.srmuniv.ac.in vanusha.d@ktr.srmuniv.ac.in kanmani.s@ktr.srmuniv.ac.in jackulin.a@ktr.srmuniv.ac.in jayavarthini.c@ktr.srmuniv.ac.in abirami.g@ktr.srmuniv.ac.in senthilkumar.t@ktr.srmuniv.ac.in Required Text Books:. Morris M. Mano and Michael Ciletti D., Digital Design: With an Introduction to the Verilog HDL, Pearson Education, 5/e, 203. [UNIT 5 - Chapter 3 & 4 ] 2. Morris Mano M., Digital Logic and Computer Design, Pearson Education, /e, 200. [ UNIT - Chapter, UNIT 2 Chapter 2 & 3, UNIT 3 Chapter 4 & 5, UNIT 4 Chapter 6 & 7 ] Web resources http://www.elec.gla.ac.uk/coursedb/7ltv.pdf Prerequisite : NIL Objectives. To identify various number systems and work with Boolean Algebra. 2. To understand various logic gates. 3. To simplify the Boolean expression using K-Map and Tabulation techniques. 4. To analyze various types of flip flops used for designing registers and counters and understand about the fundamental concepts of Hardware Description Language. Assessment Details Cycle Test I : 0 Marks Surprise Test I : 5 Marks Cycle Test II : 0 Marks Model Exam : 20 Marks Attendance : 5 Marks Test Schedule
S.No. DATE TEST TOPICS DURATION Cycle Test - I Unit I & II 2 periods 2 Cycle Test - II Unit III & IV 2 periods 3 Model Exam All 5 units 3 Hrs Course Objective. Students use mathematical symbols to represent different bases and will communicate concepts using different number systems. 2. Students will apply logic to design and create, using gates, solutions to a problem 3. Students will apply the rules of Boolean algebra to logic diagrams and truth tables to minimize the circuit size necessary to solve a design problem 4. Students will design, construct, build, troubleshoot, and evaluate a solution to a design problem 5. Students will gain knowledge in analyzing and designing Combinational and Sequential Circuits Course Outcomes Students who have successfully completed this course will have full understanding of the following concepts Course outcomes. Basics of Digital Fundamentals 2. Analysis and design of Combinational circuits 3. Analysis and design of Synchronous and asynchronous Sequential circuits 4. Hardware Description Language Program outcome. To be able to design and implement digital electronics concepts in engineering field. Detailed Session Plan NUMBER SYSTEMS AND CODES Digital Computers and digital systems Review of binary number systems Number Base conversions- Complements Signed Binary Numbers Binary Arithmetic Binary codes Error Detection codes Binary Logic Logic Gates. Sessi on No. Topics to be covered Time (min) Ref Teaching Method Digital Computers and digital systems 50 2 Testing Method 2 Review of binary number systems 50 2 3 Number conversion, Complements 50 2 4 Signed Binary Numbers 50 2 5 Binary Arithmetic 50 2,PPT 6 Binary codes 50 2 7 Error Detection codes 50 2,
8 Binary Logic, Logic Gates 50 2 BOOLEAN ALGEBRA & SIMPLIFICATION Boolean Algebra Basic Theorems and properties Boolean Functions Canonical and Standard Forms Karnaugh Map Simplification Two, Three,Four and Five Variables NAND and NOR Implementation Don t Care Conditions Quine McCluskey Method 9 Boolean Algebra,Basic Theorems and Properties 50 2 0 Boolean Functions 50 2 Brain storming Canonical and Standard Forms 50 2 Surprise Test 2 Karnaugh Map Simplification Two Variables 50 2 3 Karnaugh Map Simplification Three Variables 50 2 4 Karnaugh Map Simplification Four Variables 50 2, 5 Karnaugh Map Simplification Five Variables 50 2 6 NAND and NOR Implementation 50 2 7 Don t Care Conditions 50 2, 8 Quine McCluskey Method 50 2, COMBINATIONAL LOGIC CIRCUITS Combinational Circuits Adder - Subtractor Design and Analysis procedures Binary Parallel Adder Decimal Adder Encoder Decoder Multiplexer Demultiplexer Magnitude comparators Read Only Memory (ROM) Programmable Logic Array(PLA). 9 Combinational Circuits,Adder,Subtractor 50 2 20 Design and Analysis procedures 50 2 2 Binary Parallel Adder 50 2 22 Decimal Adder 50 2 23 Encoder 50 2 24 Decoder 50 2 25 Multiplexer 50 2 26 Demultiplexer,Magnitude Comparators 50 2 27 Read Only Memory (ROM) 50 2, Comparative study Surprise Test 28 Programmable Logic Array(PLA). 50 2 SEQUENTIAL LOGIC CIRCUITS Sequential circuits Latches Flip-flops Triggering of Flip-Flops Analysis of clocked sequential circuits State reduction and state assignment Design procedure of clocked sequential circuits Design of counters Registers Shift registers Ripple counter and Synchronous counter
29 Sequential circuits,latches 50 2 30 Flip-flops 50 2 3 Triggering of Flip-Flops 50 2 32 Analysis of clocked sequential circuits 50 2 33 State reduction and state assignment 50 2 34 35 Design procedure of clocked sequential circuits 50 2 Design procedure of clocked sequential circuits 50 2 36 Design of counters 50 2 37 Registers,Shift registers 50 2 38 Ripple counter and Synchronous counter 50 2 HARDWARE DESCRIPTION LOGIC Introduction to Hardware Description Language (HDL)-HDL for combinational circuits and Sequential Circuits 39 Introduction to Hardware Description Language (HDL) 40 HDL Register Transfer level 50 4 HDL of binary multiplier 50 42 Algorithmic state machines 50 50 Brain storming 43 Control Logic 50 44 HDL for combinational circuits 50 45 HDL for Sequential Circuits 50 Surprise test Black Board(Chalk & Board) PPT PowerPoint Presentation Name of the staffs : Mrs.G.Sivagami,Ms.TYN.Nagamalliswari,Mr,S.Jagadeesan,Ms.JV.Vidhya,Ms.C.Sindhu, Mrs.S.Saranya,Mrs.Kiruthikadevi,Ms.D.Vanusha,Mrs.Kanmanisivangar,Mrs.A.JackulinMahariba, Mrs.C.Jayavarthini,Mrs.G.Abirami,Mr.T.Senthil Kumar Prepared by Mr.T.SENTHIL KUMAR, AP(Sr.G),CSE Approved by HOD/CSE