TEA2037A HORIZONTAL & VERTICAL DEFLECTION CIRCUIT

APPLICATION NOTE HORIZONTAL & VERTICAL DEFLECTION CIRCUIT By B. D HALLUIN SUMMARY Page I INTRODUCTION....................................................... 2 II FUNCTIONAL DESCRIPTION OF................................ 2 II.1 GENERAL DESCRIPTION............................................... 2 II.1.1 Block Diagram......................................................... 2 II.1.2 Pin Descripion........................................................ 3 II.1.3 Package............................................................. 3 II.2 SYNC. PULSE SEPARATOR............................................. 3 II.2.1 Exracion of Sync. Pulses from he Composie Video Signal..................... 3 II.2.2 Negaive TTL Sync. (monior applicaion).................................... 3 II.2.3 Frame Sync Exracion.................................................. 4 II.3 LINE OSCILLATOR.................................................... 4 II.4 LINE OUTPUT STAGE.................................................. 5 II.5 PHASE COMPARATOR (PLL)............................................ 5 II.5.1 Funcional Descripion................................................... 5 II.5.2 Phase Comparaor Operaion............................................. 6 II.5.3 Oupu Filer.......................................................... 7 II.6 FRAME OSCILLATOR.................................................. 8 II.7 FRAME OUTPUT AMPLIFIER............................................ 8 II.8 FRAME FLYBACK GENERATOR.......................................... 9 II.9 SHUNT REGULATOR.................................................. 10 II.10 THERMAL CONSIDERATIONS........................................... 10 III APPLICATION EXAMPLES.............................................. 11 III.1 MONITOR APPLICATIONS.............................................. 11 III.1.1 Low-cos Monior (French Miniel).......................................... 11 III.1.2 Monior wih Geomery and Frequency Adjusmens........................... 12 III.1.3 High Frequency Monior................................................. 13 III.2 BLACK & WHITE APPLICATION.......................................... 14 III.3 USING COMPOSITE TTL SYNCHRONIZATION SIGNALS...................... III.4 DIRECT FRAME SYNCHRONIZATION..................................... III.5 CONSTANT AMPLITUDE 50/60Hz SWITCHING.............................. III.6 MODIFYING THE LINE OUTPUT DURATION................................ III.7 STARTING THE FROM +6V POWER SUPPLY...................... IV DESIGN CONSIDERATION.............................................. 17 IV.1 PRECAUTION FOR INTERLACED SCANNING.............................. 17 IV.2 PRINTED CIRCUIT BOARD LAYOUT...................................... 17 AN410/1293 1/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT I - INTRODUCTION The is a horizonal and verical deflecion circui for moniors and black and whie TV ses. This device includes all funcions required for deflecion, namely : - and frame sync separaion - oscillaor wih phase comparaor - Driver sage for line deflecion darlingon ransisor - Frame oscillaor - Frame amplifier wih flyback generaor for direc drive of he verical deflecion yoke. The is paricularly well-suied for lowcos moniors since i is cased in a low-cos package and requires a few number of exernal componens and hence opimized for small displays. However, applicaion areas are by no means limied. Sophisicaed applicaions requiring various adjusmen possibiliies such as for display geomery and cenering seings (ampliude, lineariy,...) and operaing a differen line and frame frequencies (line frequencies up o 64kHz), are readily configured around. In large screen applicaions, addiion of a heasink mouned on will enable he verical deflecion yoke curren o be boosed o 2A peako-peak. II - FUNCTIONAL DESCRIPTION OF II.1 - General Descripion The is a -pin DIP package. The 4 cener pins (2 on each side) are conneced ogeher and used as heasink. From composie video or TTL-compaible sync. signals, he device will exrac and generae all signals required for he line scanning darlingon ransisor and direc drive of he frame yoke. The following funcional blocks are implemened on-chip : - and frame sync. separaor - oscillaor - phase comparaor - oupu sage - Frame oscillaor - Frame amplifier - Frame flyback generaor - Shun regulaor The common device power supply is implemened by he on-chip shun regulaor. In order o opimize he drive o frame deflecion yoke and also enable appropriae use of he flyback generaor, he frame amplifier is powered by an independen supply. The ground is conneced o he 4 cener pins of he device. II.1.1 - Block Diagram Figure 1 1 7 3 2 4 5 12 13 FRAME OSCILLATOR FRAME FRAME-SYNC. OSCILLATOR SEPARATOR + POWER STAGE - FLYBACK GENERATOR 8 6 Yoke INPUT STAGE PHASE DETECTOR LINE OSCILLATOR OUTPUT STAGE 14 11 10 9 2037A-02.EPS 2/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT II.1.2 - Pin Descripion Figure 3 1 Frame Oscillaor 2 2 (Flyback generaor power supply) 3 Flyback Generaor Oupu 4, 5 Ground 6 Frame Feed-back (frame amplifier invering inpu) VIDEO LEVEL 0 1 line (64µs) 7 2 (posiive power supply for frame oupu sage) 8 Frame Oupu (direc drive o frame yoke) 9 Oscillaor 10 Phase Comparaor Oupu 11 Phase Comparaor Inpu (line flyback) 14 Oupu (drive o line darlingon ransisor) Video Inpu (or TTL-compaible sync.) (shun regulaor) II.1.3 - Package Bawing DIP (plasic package) PIN VOLTAGE (V) 1.6 0 - The sync. deecion level is se a 1.6V. - The value of R2 is ypically 1MΩ (fixed for a good inernal bias). - Resisor R1 limis he oupu curren of Pin. As illusraed in he Figure 4, i is recommended o employ a low-pass filer which will suppress highfrequency harmonics suscepible o produce jiers on line sync signal in composie video TV applicaions. 2037A-12.EPS Figure 4 II.2 - Sync. Pulse Separaor The exracs, firs he line and frame sync. pulses from he composie video signal and hen he larges pulses, i.e., he frame syncs. II.2.1 - Exracion of Sync. Pulses from he Composie Video Signal (TV applicaion) Figure 2 : Synchronizaion Separaor Circui Composie Video Figure 5 1.5kΩ 220pF 100nF 1MΩ II.2.2 - Negaive TTL Sync. (Monior applicaion) 2037A-13.EPS V R Video V R R1 R2 SL1 SL2 2037A-03.EPS TTL Sync In monior applicaion, he sync. signal is generally separaed from he video signal. In his case, he sync. signal is applied o Pin hrough a single limiing resisor. Similar o he former case, he sync. is deeced when he inpu volage falls below 1.6V level. 2037A-14.EPS 3/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT Figure 6 II.3 - Oscillaor TTL SYNC LEVEL (V) 5 1.6 Figure 9 R 9 C PIN VOLTAGE (V) 5 1.6 2037A-.EPS 1.4kΩ II.2.3 - Frame Sync. Exracion Figure 7 : Frame Separaor V Z 2037A-17.EPS Q3 Q4 Figure 10 SL1 I ST1 ST2 3I V / 2 Z This funcion is processed inernally and hence does no require any exernal componen. and frame sync. pulses are disinguished by an inegraed capacior which is more or less discharged during each sync. pulse inerval as follows : - if he sync pulse duraion is shor, i.e. i is line sync, hen he capacior is slighly discharged - on he oher hand, if he pulse widh is larger, he capacior is fully discharged and an inernal frame signal is hus generaed. Figure 8 SYNC PULSE INTEGRATED CAPACITOR VOLTAGE (V) V Z V Z /2 2037A-04.EPS 2037A-.EPS PIN 9 VOLTAGE (V) 6.6 3.2 Period This funcion is processed inernally and hence does no require any exernal componen. and frame sync. pulses are disinguished by an inegraed capacior which is more or less discharged during each sync. pulse inerval as follows : - if he sync pulse duraion is shor, i.e. i is line sync, hen he capacior is slighly discharged - on he oher hand, if he pulse widh is larger, he capacior is fully discharged and an inernal frame signal is hus generaed. The line saw-ooh is generaed by charging an exernal capacior on Pin 9 via a resisor conneced o VCC1 (Pin ). The capacior is discharged via an inernal 1.4kΩ resisor. The saw-ooh ampliude is se by wo on-chip hreshold levels : - lower hreshold : 3.2V - higher hreshold : 6.6V The free-running period is approximaely given by he following relaionship : T OSC 0.85 RC 2037A-18.EPS 4/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT The phase comparaor will modify he capacior charge by injecing a posiive or negaive curren so as o produce correc phase and frequency relaionships wih respec o he synchronizaion signal. II.4 - Oupu Sage The line oupu sage has been designed for direc base drive of he horizonal scanning darlingon ransisor. The low level inerval on Pin 14, i.e. he power line ransisor blocking period, is deermined by he ime when he volage of he line oscillaor capacior (Pin 9) is below 4.8V (inernally se hreshold level). In a ypical applicaion, his inerval corresponds o 22µs a 64µs free-running period. Figure 11 6.6V 3.2V Sawooh 14 R2 R1 C D T LINE YOKE R3 V REF = 4.8V T1 = 470Ω R2 = 10Ω R3 = 47Ω C = 2.2µF D : 1N4148 T : BU184 2037A-19.EPS Figure 12 PIN9 VOLTAGE (V) 6.6 4.8 3.2 II.5 - Phase Comparaor (PLL) II.5.1 - Funcional Descripion The duy of phase comparaor is o synchronize he horizonal scanning wih he line sync pulse and ensure correc line flyback during he horizonal blanking phase. Figure 13 PIN14 VOLTAGE (V) V (sa) 22µs 64µs VIDEO SIGNAL DARLINGTON V CE YOKE CURRENT 2037A-20.EPS LINE FLYBACK The line flyback signal (i.e. he pulse on he collecor of he line scanning ransisor) is compared wih he line sync. signal issued by sync. separaor. If he deeced coincidence is incorrec, he comparaor will hen generae an appropriae posiive or negaive curren so as o charge or discharge he line oscillaor capacior hereby providing for frequency and phase locking. 2037A-21.EPS 5/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT II.5.2 - Phase Comparaor Operaion Figure 14 C2 C1 11 LS FS Figure : Phase Comparaor Flyback Inegraed Flyback Sync Pulse Oupu Curren R1 I 3 T6 T3 T4 I 1 I 2 T1 T5 I T2 V REF I OUT 10 9 R3 R4 R5 C3 C4 C5 Oscillaor V C 2037A-22.EPS 2037A-06.EPS The line flyback signal goes hrough inegraor nework R1C1 he oupu of which, a saw-ooh signal, is applied o comparaor inpu (Pin 11) via capacior C2. The comparaor inpu sage is formed by he differenial pair T1 and T2. T3 and T4 ransisors are arranged in curren mirror configuraion and hus : i 3 = i 2 The sum of currens going hrough T1 and T2 ransisors is deermined by he curren generaor "I" so ha : I = i 1+ i 2 The comparaor oupu curren is he difference curren hrough he differenial pair, i.e. : i OUT = i 2 - i 1 The comparaor is enabled by T5 ransisor only during he line sync. inerval. Transisor T6 inhibis he phase comparison during he frame sync. inerval. During he firs porion of he flyback, he volage a comparaor inpu (Pin 11) is lower han he reference volage. T1 is off and T2 conducs ; consequenly he comparaor oupu goes posiive : i OUT = + I During he second porion, he inpu volage exceeds he reference volage and as a resul, he comparaor oupu falls o negaive level : i OUT = - I If he line flyback is in reard wih respec o he horizonal sync. pulse (which is he case of oo long line periods), he inerval for which he phase comparaor s oupu curren is posiive would increase. This curren is hen filered and applied o he line oscillaor capacior (C5) hereby acceleraing is charge-up phase and hence reducing he line period. Inverse acion akes place if he line flyback is in advance - he negaive curren a comparaor s oupu will rise, C5 is charged more slowly and he line period is hus increased. 6/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT Figure LINE FLYBACK V REF SAWTOOTH (Pin 11) V REF INTERNAL LINE SYNC PULSE OUTPUT CURRENT (Pin 10) The line flyback in reard wih respec o he line sync pulse The line flyback in advance wih respec o he line sync pulse 2037A-23.EPS II.5.3 - Oupu Filer Figure 17 Figure 18 GAIN 10 R3 R4 R5 C3 C4 C5 f 2 = FILTER f1 f2 f3 f 1 = 1 2πR3C3 FREQUENCY 9 1 2π (R3 + R4) C3 f 3 = R3 + R4 2πR3R4C4 2037A-24.EPS 2037A-25.EPS The duy of he oupu filer is o ensure he sabiliy of he locked loop and is characerisics will have a parial influence on capure range and also on capure ime. The holding range, which is larger han he capure range, depends on he raio of he curren available a he comparaor oupu and he charging curren of he line oscillaor. The holding range does no depend direcly on he cu-off frequencies of he oupu filer. Bu, as he volage range a he comparaor oupu is limied, a oo high value for R4 will limi he holding range. The sync. pulse duraion has significan influence on capure range and also on he holding range of he device. The oupu curren duraion is direcly relaed o synchronizaion pulse widh. - Firs he R5 x C5 produc is seleced o yield he required free-running line oscillaor frequency. - Then, he value of C5 capacior is seleced as follows : for monior applicaions (large holding range) low value; e.g. : 2.2nF @ khz, 1nF @ 32kHz for TV applicaions higher value; e.g. : 4.7nF @ khz - Finally, he filer componens are seleced o mach he required capure range. (R4 100kΩ o preven comparaor oupu sauraion) 7/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT II.6 - Frame Oscillaor Similar o line oscillaor, he frame saw-ooh is generaed by charging an exernal capacior on Pin 1 hrough a resisor conneced o VCC1. Figure 19 Frame Sync Pulse Figure 20 PIN 1 VOLTAGE (V) PIN 1 VOLTAGE (V) INTERNAL FRAME SYNC 3.1 2 3.1 2 Frame Free-running period R Sync Period 9 C 500Ω Ampliude Ampliude The capacior is discharged via an inernal 500Ω resisor. The saw-ooh ampliude is se a wo on-chip hreshold levels. 2037A-26.EPS 2037A-27.EPS The free-running period is approximaely given by : T OSC 0. RC Synchronizaion is achieved by period reducion. The frame sync. pulse issued by he sync. separaor will modify he curren hrough he resisor bridge which is used o se he saw-ooh hreshold levels. The minimum synchronized frame period (MSFP) is given by : MSFP TOSC 1.8 II.7 - Frame Oupu Amplifier The frame saw-ooh generaed by frame oscillaor is firs invered (Gain : - 0.4) and hen applied o he non-invering inpu of he frame amplifier. The oupu curren capabiliy of his amplifier is as high as ± 1A hus enabling o drive verical deflecion yokes requiring 2A peak-o-peak. As a funcion of dissipaed power, he device may require he addiion of a heasink. A feed-back loop is conneced o he invering inpu of he frame amplifier (Pin 6). As he CRT screen is no par of a sphere cenered on he deflecion cener poin, if he yoke is acually driven by a saw-ooh waveform, he image is expanded a he op and boom. The yoke mus herefore be provided wih an "S" waveform curren, by applying lineariy correcion. Figure 21 Frame Sawooh 6 2 5 R4 R5 4 7 12 13 C2 P 8 R2 R3 C3 R6 FRAME YOKE C1 R1 2037A-28.EPS 8/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT Figure 22 FRAME SAWTOOTH (non-invering inpu) The configuraion of he flyback generaor is depiced in Figure 23. Figure 23 D1 C D2 OUTPUT VOLTAGE (Pin 8) YOKE CURRENT The circui configuraion depiced above does no require any lineariy adjusmen - only an ampliude adjusmen poeniomeer "P" has been provided for. - D.C. Feedback : The C1 capacior is charged o approximaely 1/2 x 2. Divider bridge formed by R2 + R4 and R5 neworks will se he d.c. feedback. The componen values of his divider nework will be choosen o avoid sauraion a op and boom of he oupu volage (Pin 6 biasing volage is approximaely 0.6V). - ariy Correcion : A parabolic signal a frame frequency is available on "+" erminal of he C1 capacior. This signal is inegraed by R2, C2 nework. An "S" waveform is hus obained, which is applied o Pin 6 via resisor R4. Any correcion o his "S" waveform depends on C1 and C2 values. The lineariy correcion depends on raio : R2/R4 - Verical Ampliude : Frame curren ampliude is deermined by he value of measuremen resisor "R1", poeniomeer "P" seings and he value of "R5" resisor. II.8 - Frame Flyback Generaor The oupu sage of he verical amplifier includes a frame flyback generaor conneced o pin 3. During he verical scanning flyback ime, he value of he yoke inducance "L" mus be aken ino accoun since he ime consan L/R is no longer negligible. In elevision applicaions, he frame blanking ime is 1.6ms. Thus when L/R > 1.6 x 10-3, i is necessary o increase he supply volage o he frame oupu amplifier so as o reduce he flyback ime. This surplus is required only for he frame flyback and energy is wased by boosing he supply o he amplifier a all imes (during he frame scanning ime, he minimum volage is subsanially RI, where I is peak-o-peak frame curren). 2037A-29.EPS 2 7 T1 T2 K 3 8 Frame Amplifier Oupu L, R During he second half of he verical scanning ime, ransisor T2 conducs and capacior C is charged o VCC hrough D1, D2, R3 and T2. (Swich K open) On flyback, swich K closes and Pin 3 is conneced o. The volage a Pin 7 (2), which was equal o - V D1, is almos doubled during he flyback ime. The only exernal componens required are herefore D1, D2 and C. In addiion o reducing he flyback ime, he flyback generaor reduces he power consumed by he power sage, and can in cerain cases avoid he need o use a heasink. Figure 24 AMPLIFIER SUPPLY 2 AMPLIFIER OUTPUT VOLTAGE (Pin 8) OUTPUT CURRENT (Yoke Curren) Diode D2 is a low-signal diode (1N4148) bu diode D1 mus be appropriaely raed since he posiive curren in he firs par of he saw-ooh is supplied o he yoke hrough D1 and T1. A 1N4001 is generally used. 2037A-30.EPS 2037A-31.EPS 9/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT II.9 - The shun regulaor The incorporaes an inernal shun regulaor which delivers he common supply volage VCC o various blocks such as oscillaors, comparaor, sync separaor and so on. The volage on Pin is 9.7V (9V min, 10.5V max). The value of he series resisor R mus be so calculaed o obain a ma curren on Pin - his curren can be 10mA min. and 20mA max. Figure 25 R The exernal curren supply from o boh oscillaors (i.e. line and frame) can be negleced in majoriy of cases. The resisor value is found o be 1.2kΩ a VCC = +28V. A VCC = + 12V, and aking ino accoun he volage olerance on Pin, a 0Ω series resisor mus be used. II.10 - Thermal Consideraions In order o ensure reliable device operaion, he dissipaed power should be accuraely deermined. Calculaion will allow an evaluaion of he dissipaed power and should be compleed by package emperaure measuremens in acual applicaions. According o resuls obained, a heasink may or may no be required. Power drawn from supply : 2037A-32.EPS Where : - Ipp = peak-o-peak curren hrough he verical deflecion yoke. -I2 = Pin 7 quiescen curren. -2 = Pin 7 volage. Power dissipaed in deflecion yoke and he measuremen resisor : P Y = (R Y + R M) I2 pp 12 Where : -Ry = Frame deflecion yoke resisance -R M = Measuremen resisor value Thus, he overall power dissipaed in he inegraed circui is : P D = P1 + P2 - P Y P D = V CC1 I 1 + V Ipp CC2 8 + I2 (R Y + R M) I2 pp 12 In applicaion using he flyback generaor, he VCC2 specified above becomes "2 - V D", where V D is he volage drop across he series diode. Figure 26 Figure 27 13 2 I 1 I 2 12 FRAME YOKE CURRENT 5 4 7 8 R M Frame Yoke Ly, Ry 2037A-33.EPS P1 = VCC1. I1 Where I 1 is he curren hrough he shun regulaor (Pin ). Power drawn from 2 supply : P2 = 2 I PP 8 + I2 I PP 2037A-34.EPS 10/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT III - APPLICATIONS III.1 - Monior Applicaions III.1.1 - Low-cos monior (French Miniel Type) (see Figure 28) CHARACTERISTICS - Screen : 9" Monochrome - Frame deflecion yoke : 72mH, 40Ω, 220mA peak-o-peak -VCC = + 25V wihou flyback generaor - Frame flyback ime : 1.2ms - Verical frequency : 50Hz (20ms) - Verical free-running period : 24.5ms - Horizonal frequency : 625Hz - Capure range : ±5µs - Holding range : ±10µs - Inpu signal : composie video - Dissipaed power : 1.W - Only one adjusmen : verical ampliude Figure 28 This is a low-cos applicaion used in French Miniel ype configuraions and requires minimum number of addiional componens and adjusmens. The inpu is a composie video signal a line frequency = 625Hz and frame frequency of 50Hz. The free-running horizonal frequency is deermined by he componen values of RC nework on Pin 9. Since no adjusmen is available, precision componens mus be used o ensure correc synchronizaion : [R = 35.7kΩ, 1% and C = 2.2nF, 2% for fh = 625Hz] The capure range is large enough o compensae for possible variaions. - Synchronizaion range of he verical oscillaor is quie large which consequenly allows use of less accurae componens : [R = 910 kω, 5 % and C = 180 nf, 5 %] - Since he frame flyback ime is shor enough a supply volage used here, he flyback generaor is no used in his applicaion. 1k Ω +25V 100µF 9 5% 100nF Video Inpu Flyback 100nF 1.5k Ω k Ω 1MΩ 180nF 5% 22nF 11 1 2 7 3 8 6 470kΩ Frame Yoke 72mH, 40Ω 470kΩ 2.2kΩ 1kΩ 47nF 10 9 4 5 12 13 14 220nF 470µF 1µF 3.9kΩ 22nF 100kΩ 2.2nF 2% 35.7kΩ 1% 10Ω 470Ω 1W 47Ω 2.2µF 1N4148 56k Ω 100Ω Verical Ampliude Adjus Darlingon 4.7kΩ 2037A-35.EPS 11/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT III.1.2 - Monior wih Geomery and Frequency Adjusmens (see Figure 29) CHARACTERISTICS - Screen : 12" Colour - Frame deflecion yoke : 18mH, 10Ω, 500mA peak-o-peak - = + 12V wih flyback generaor - Frame flyback ime : 0.7ms - Verical frequency : 50/60Hz - Verical free-running period : 23ms (adjusable) - Horizonal frequency :.7kHz (adjusable) Figure 29 - Capure range : = ±5µs - Holding range : ±10µs - Inpu signal : negaive TTL sync (line + frame) - Dissipaed power : 0.9W - Adjusmens : Verical ampliude Verical lineariy Verical frequency Horizonal frequency Horizonal phase-shif +12V 0Ω 100µF P3 470kΩ 470k Ω 1N4002 P1 : Verical Ampliude P2 : Verical ariy P3 : Verical Frequency P4 : Horizonal Frequency P5 : Horizonal Shif 1-2-3 swiching : Verical Posiion 100nF 180nF 47µF 1N4148 2.2Ω TTL Sync Flyback kω 47kΩ 100kΩ P5 22nF 47nF 1µF 3.9kΩ 11 22nF 1 2 7 3 10 100kΩ 9 22nF 22kΩ 4 5 22kΩ P4 12 13 14 10Ω 8 6 180Ω 1/2W 47Ω 680pF 2.2µF 1N4148 18kΩ 39kΩ 470nF 100kΩ P1 Darlingon Frame Yoke 18mH, 10Ω P2 100Ω 180kΩ 1000µF 1.2kΩ 220Ω 330Ω 330Ω 1 2 3 2037A-36.EPS 12/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT III.1.3 - High Frequency Monior (see Figure 30) CHARACTERISTICS - Screen : 14" Colour - Frame deflecion yoke : 11mH, 7Ω, 750mA peak-o-peak - = + 14 V wih flyback generaor - Frame flyback ime : 0.6ms - Verical frequency : 72Hz - Verical free-running period : ms (adjusable) - Horizonal frequency : 35kHz (adjusable) - flyback ime : 5.5µs - Capure range : 5µs (@sync pulse = 4.7µs) - Inpu signal : negaive TTL sync (line + frame) - Dissipaed power : 1.4W (heasink required) - Adjusmens : Verical ampliude Verical lineariy Verical frequency Horizonal frequency Figure 30 2.2Ω +14V 170Ω 100µF P3 470kΩ 1000µF 1N4002 P1 : Verical Ampliude P2 : Verical ariy P3 : Verical Frequency P4 : Horizonal Frequency 470kΩ 100nF 0nF 47µF 1N4148 2.2Ω TTL Sync Flyback kω 22nF 47nF 11 1 2 7 3 10 9 4 5 12 13 14 8 6 680pF 39kΩ 330nF 47kΩ Frame Yoke 18mH, 10Ω P2 68kΩ 180Ω 2200µF 1µF 3.9kΩ 6.8nF 4.7kΩ 1nF 22kΩ 22kΩ P4 10Ω 220Ω 1/2W 47Ω 2.2µF 1N4148 18kΩ P1 Darlingon 100Ω 1Ω 2037A-37.EPS 13/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT III.2 - Black & Whie TV Applicaion (see Figure 31) CHARACTERISTICS - Screen : 20" B & W 110 o - Frame yoke : 30mH, 12Ω, 850mA peak-o-peak -VCC = + 24 V wih flyback generaor - Frame flyback ime : 1ms - Verical frequency : 50Hz - Verical free-running period : 24.5ms - Horizonal frequency : 625Hz (adjusable) - Capure range : ±2 µs - Holding range : ±4.5 µs - Inpu signal : composie video - Dissipaed power : 2.3W (10 o C/W - heasink required) - Adjusmens : Verical ampliude Verical lineariy Horizonal frequency Figure 31 +24V 1kΩ 100µF 4.7Ω 9 5% 470µF 1N4002 24V 2.2kΩ Frame Blanking P1 : Verical Ampliude P2 : Verical ariy P3 : Horizonal Frequency Video Inpu 1.5kΩ 100nF 180nF 5% 47µF 1N4148 2.2Ω 100nF Flyback 220pF kω 1MΩ 22nF 11 47nF 1 2 7 3 8 6 10 9 4 5 12 13 14 100kΩ 680pF 100kΩ 680nF 680nF 220kΩ 33kΩ P2 Frame Yoke 30mH, 12Ω 47kΩ 470µF 680Ω 4.7kΩ 22nF 4.7nF kω kω P1 100Ω 1Ω 2.2µF 4.7kΩ P3 10Ω 470Ω 1W 2.2µF 47Ω Darlingon 1N4148 2037A-38.EPS 14/17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT III.3 - Using Composie TTL Synchronizaion Since he hreshold level on inpu Pin is inernally se a 1.6V, he device can direcly accep TTL signals. However, a series resisor is required o limi he curren sunk by he on-chip ransisor (Pin ). Figure 32 III.4 - Direc Frame Synchronizaion The verical scanning can be direcly synchronized by he frame oscillaor (Pin 1) and wihou any need of using he synchronizaion inpu (Pin ). Figure 35 illusraes an example : In his case, only he line sync pulse is applied o Pin. Figure 35 Reference Figure 33 Sync Inpu Frame Sync Inpu If composie sync signal is no available, line and frame sync signals can be recombined a circui inpu as illusraed in Figure 33. Figure 34 : Applicaion Example 2037A-39.EPS 2037A-40.EPS Posiive Frame Sync Negaive Sync 680kΩ 220nF 1 III.5 - Consan Ampliude 50/60Hz Swiching In applicaions requiring 50/60Hz sandard swiching feaure, he arrangemen shown below allows o mainain he ampliude of he oscillaor saw-ooh (Pin 1) consan hus yielding uniform verical scanning. Figure 36 2037A-42.EPS Sync Inpu 60Hz Ampliude Adjus Frame Sync Inpu 33nF 330Ω 60Hz 50Hz Noe : 47kΩ Specified componen values are purely heoreical and mus be calculaed o mee specific applicaion requiremens. This arrangemen is paricularly ineresing in applicaions where he available signals differ from hose commonly used. An example is he case where he frame signal is of quie long duraion (someimes as long as frame blanking period). In such case, efficien synchronizaion can be achieved by differeniaing he signal so ha i will behave as a signal of only few lines duraion which is he condiion required for appropriae frame and line sync separaion and also a picure wihou flag effec. 2037A-41.EPS Figure 37 PIN 11 VOLTAGE (V) 3.1 2 60Hz 50Hz 60Hz Sync 1 Verical Oscillaor Upper Threshold 50Hz Sync Lower Threshold Consan Ampliude 2037A-43.EPS 2037A-44.EPS /17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT A pracical applicaion configuraion is illusraed in Figure 38. Figure 38 scanning a a reduced supply volage (e.g. +6V) and hen supply he overall configuraion by he power available on he line ransformer (see Figure 41). Figure 39 2.2kΩ 9 R1 50Hz Ampliude Adjus 0nF 1 R2 9 14 T 50Hz : T conducs 60Hz : T urnedoff III.6 - Modifying he Oupu Duraion (see Figures 39 and 40) The line oupu pulse duraion is deermined by wo inernally se hreshold levels. This inerval can be alered by modifying he charge curren of he line oscillaor (Pin 9). III.7 - Saring he from a +6V Power Supply The line oscillaor of is capable of saring a a low supply volage (< 6V). The period of oscillaion is pracically he same as a nominal operaion. I is hus possible o iniiae he line 2037A-45.EPS Figure 40 PIN 9 VOLTAGE (V) PIN 14 VOLTAGE (V) 6.6 4.8 3.2 C R3 2037A-46.EPS 2037A-47.EPS Figure POWER SUPPLY +6V... +12V +25V EHT TRANSFORMER EHT 100µF 1kΩ 2 7 14 LINE YOKE 2037A-48.EPS /17

- HORIZONTAL & VERTICAL DEFLECTION CIRCUIT IV - DESIGN CONSIDERATIONS IV.1 - Precauions for Inerlaced Scanning - The links inerconnecing he ground erminals of and power supplies, as well as hose of device decoupling capaciors, mus be kep o as shor as possible - A high value decoupling capacior can be used for supply, provided ha a good qualiy low series resisance capacior is employed. Inerlacing is very sensiive o decoupling qualiy. The value of he decoupling capacior can vary from 22µF o 100µF. - The inerconnecing links beween he frame oscillaor capacior, he line oscillaor capacior and grounds mus be kep o as shor as possible. Perfec line and frame synchronizaion is achieved by observing he above guidelines and recommendaions. IV.2 - Prined Circui Board Layou The usual precauions observed in design of TV imebase pc boards mus be employed The line oupu sage handles high amouns of volage and curren. Componens employed mus herefore be appropriaely raed, he widh of and he clearance beween he wiring racks should be carefully seleced. All connecions mus be as shor as possible and all signals a he line frequency gahered a his secion. The supply o he frame scanning secion of he circui mus no be influenced by he horizonal scanning funcion, paricularly when inerlaced scanning is used. Generally speaking, ineracions on he pc board beween he high-gain/low-level and he high-curren secions of he oupu sages mus be minimized by as much as possible. As indicaed in previous chapers, he four cener pins of he device mus be earhed. The pad used for his purpose mus be as large as possible since i acs as he heasink for he device. A cruciform pad underlying he circui should be employed. There should be a single connecion o he chassis earh erminal. Informaion furnished is believed o be accurae and reliable. However, SGS-THOMSON Microelecronics assumes no responsibiliy for he consequences of use of such informaion nor for any infringemen of paens or oher righs of hird paries which may resul from is use. No licence is graned by implicaion or oherwise under any paen or paen righs of SGS-THOMSON Microelecronics. Specificaions menioned in his publicaion are subjec o change wihou noice. This publicaion supersedes and replaces all informaion previously supplied. SGS-THOMSON Microelecronics producs are no auhorized for use as criical componens in life suppor devices or sysems wihou express wrien approval of SGS-THOMSON Microelecronics. 1994 SGS-THOMSON Microelecronics - All Righs Reserved Purchase of I 2 C Componens of SGS-THOMSON Microelecronics, conveys a license under he Philips I 2 C Paen. Righs o use hese componens in a I 2 C sysem, is graned provided ha he sysem conforms o he I 2 C Sandard Specificaions as defined by Philips. SGS-THOMSON Microelecronics GROUP OF COMPANIES Ausralia - Brazil - China - France - Germany - Hong Kong - Ialy - Japan - Korea - Malaysia - Mala - Morocco The Neherlands - Singapore - Spain - Sweden - Swizerland - Taiwan - Thailand - Unied Kingdom - U.S.A. 17/17