Serial Digital Interface II Reference Design for Stratix V Devices

Serial Digital Interface II Reference Design for Stratix V Devices AN-673 Application Note This document describes the Altera Serial Digital Interface (SDI) II reference design that demonstrates how you can transmit and receive video data using the Altera SDI II MegaCore function, as well as to replace the external voltage controlled crystal oscillator (VCXO) circuits in the Stratix V GX FPGA development kit. Overview f Conventionally, a design needs an external clock or VCXO, and PLL components to generate a high quality, low jitter reference clock for the transmitter phase-locked-loop (PLL). The system described in this reference design provides a method to effectively replace these external clock components using a combination of fractional PLL (fpll) features and a soft logic based control loop. This reference design also describes how to use the serial digital interface of different variants with the Stratix V GX FPGA development kit. The reference design uses three instances of the SDI II MegaCore function in the Stratix V GX FPGA development kit. The SDI II MegaCore function consists of a standard definition (SD-SDI), high definition (HD-SDI), and a 3 gigabits per second (3G-SDI) standards. For more information about the MegaCore function and the development kit, refer to their respective documents: SDI II MegaCore Function User Guide Stratix V GX FPGA Development Board Reference Manual SDI HSMC Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered December 2012 Altera Corporation Feedback Subscribe

Page 2 Functional Description Functional Description Figure 1. Block Diagram This reference design provides a general platform for you to control, test, and monitor different speeds of the SDI operation. Figure 1 shows the SDI II reference design block diagram. Stratix V FPGA 125 MHz Osc Osc Ch0 SDI Reclock fpll Design Example Loopback Path 148.5 MHz/ 148.35 MHz Ch0 SDI TR Duplex CDR HSSI SDI_IN_1 (J9) SDI_OUT_1 (J8) 156.25 MHz PLL Reconfiguration Controller Transceiver Reconfiguration Controller PHY IP Core Reconfiguration Management/Router 148.5 MHz Ch1 SDI TR Rx SDI_RX (J16) Osc CDR Video Pattern Generator Ch1 SDI TR Tx SDI_TX (J17) HSSI Legend Video Data Control Signal Status Signal Clock Input (125 MHz) Clock Input (156.25 MHz) Clock Input (148.5 MHz) Clock Input (148.5/148.35 MHz) SDI II MegaCore Function PLL ALTPLL_RECONFIG Megafunction The following sections describe the functional blocks in Figure 1. SDI II MegaCore Function This reference design contains multiple instances of triple rate SDI occupying two transceiver channels. A triple rate SDI configured in duplex mode occupies transceiver channel 0, while a pair of triple rate SDI configured in transmitter and receiver mode occupy transceiver channel 1. Serial Digital Interface II Reference Design for Stratix V Devices December 2012 Altera Corporation

Functional Description Page 3 SDI TR Duplex (Channel 0) The triple rate SDI provides a full-duplex SD/HD/3G-SDI interface. This channel demonstrates a receiver-to-transmitter loopback by decoding, buffering, recoding, and retransmitting the received data. A SDI reclocking soft logic includes the fpll to replace the VCXO which provides a low jitter reference clock for the transmitter PLL ( in this instance). The generated low jitter output clock (148.5- or 148.35-MHz) of the fpll is cascaded to the transceiver's PLL. Thus, the fpll approach is a simplified alternative of the transmitter clock multiplexer feature to support both 1/1.000 and 1/1.001 data rate factors without the need of two reference clock inputs. SDI TR Tx (Channel 1) The triple rate SDI provides a simplex SD/HD/3G-SDI interface. The SDI Tx in channel 1 functions as a video source and generates an output of 270 Mbps (SD), 1.485 Gbps (HD), or 2.97 Gbps (3G) video stream. This channel receives input from the video pattern generator. SDI TR Rx (Channel 1) The SDI Rx in channel 1 demonstrates an SD/HD/3G-SDI receiver interface. This channel uses an external clock source of 148.5 MHz as the transceiver reference clock. Video Pattern Generator The video pattern generator generates colorbar or pathological test patterns. The colorbar pattern is for image generation while the pathological pattern is to stress the PLL and cable equalizer of the attached video equipment. You can configure the video pattern generator to output various video formats at SD/HD/3G rates. Transceiver Reconfiguration Controller and Reconfiguration Management/Router These blocks reconfigure the receiver part of the SDI TR duplex and the SDI TR Rx instance in this reference design. f For more information about the transceiver reconfiguration, refer to the Transceiver Reconfiguration Controller section in the Altera Transceiver PHY IP Core User Guide. Loopback Path The loopback path contains a phase compensation FIFO buffer for handling data transmission across asynchronous clock domains (the receiver recovered clock and the transmitter clock out). The FIFO buffer connects the decoded receiver data to the transmitter input. The SDI II MegaCore function writes the receiver data to the FIFO buffer when the receiver is in the lock position. When the FIFO buffer is half full, the transmitter starts to read, encode, and transmit the data. December 2012 Altera Corporation Serial Digital Interface II Reference Design for Stratix V Devices

Page 4 Functional Description SDI Reclock Figure 2. SDI Reclock Block Diagram This block consists of an fpll, PLL reconfiguration controller (ALTPLL_RECONFIG Megafunction), and soft IP logic that work together with DSP resources to serve as a functional replacement for the VCXO. Figure 2 shows the SDI reclock block diagram. XO Reference Fixed 156.25 MHz External to FPGA Stratix V PLL in Fractional Mode (altera_pll) Divide Ref FB PFD Charge Pump Loop Filter VCO Cascade to TX PLL 148.5 MHz/148.35 MHz or Divide Delta Sigma Modulator and ECN 1485 MHz/1483.5 MHz Direct to TX HSSI Channel reconfig_to_pll reconfig_from_pll XO Reference Fixed 125 MHz External to FPGA PLL Reconfiguration Controller (alterapll_reconfig) M Counter Fractional Value (K) DPRIO Access CSR Avalon-MM Slave Extracted H-sync from the Incoming Video Incoming Video Format Soft IP (PFD/PI Loop Filter) Ref Divide FB PFD Update Rate = H-Sync Rate SD =~ 15 khz HD =~ 33kHz 3G =~ 67 khz Loop Filter (PI Control) Initial Kp, Ki Steady- State Kp TX Clock Out 148.5 MHz/ 148.35 MHz A delta-sigma fpll architecture is introduced in addition to the existing integer PLL to allow integer and fraction multiplications for the output frequency. A delta-sigma modulator shifts the fractional noise to high frequencies and the PLL filters out the noise. The fpll uses divide counters and different VCXO taps to perform frequency synthesis and phase shift. The counter settings can be configured to adjust the fpll output clock in real time without reconfiguring the entire FPGA device. In an environment without a VCXO, only the M counter fractional value (K or Mfrac) needs to be configured by the PLL reconfiguration controller for the delta-sigma modulator. The soft IP logic is a phase-frequency detector (PFD) based PLL that compares the reference and feedback signals. Reference signal (ref) the horizontal sync pulse (HSYNC) signal that is extracted from the incoming video stream. Serial Digital Interface II Reference Design for Stratix V Devices December 2012 Altera Corporation

Functional Description Page 5 Feedback signal (FB) the divided value of the transmitter clock out, which is typically the fpll output clock. The PFD is a flip-flop that compares both the reference and feedback signals to generate up and down pulse width. The loop filter receives the pulses and counts them on fast clock to generate the phase error signal. The loop filter implements the proportional-integral (PI) control algorithm. The phase error drives the proportional and integral elements of the PI controller. The resulting signal is the Mfrac value that is used to update the fpll dynamically. 1 For a desired control response, tune the control loop to adjust the parameters such as proportional (Kp) and integral (Ki) gains to the optimum values. Stability is a basic requirement, but beyond that, different systems have different behaviors, different applications have different requirements, and the requirements may conflict with one another. These gain values are predefined and work well in this reference design. The tables below list the characterization data for the fpll cascading to the ATX or PLL in Stratix V devices using normal compensation mode. The jitter specification meets the SDI requirement in Stratix V devices. Table 1 lists the characterization data for fpll cascade in a quiet condition (SDI only). Table 1. fpll Cascade to ATX or PLL in Quiet Condition Characterization Data Rate SD-SDI HD-SDI 3G-SDI Timing (UI) 0.2 1.0 2.0 Jitter Specification Alignment (UI) 0.2 0.2 0.3 Slow Device (-40 C, low V CC ) ATX Timing (UI) 0.05 0.06 0.14 0.16 0.25 0.33 Alignment (UI) 0.04 0.05 0.09 0.10 0.16 0.17 Timing (UI) 0.05 0.06 0.15 0.17 0.26 0.35 Alignment (UI) 0.04 0.05 0.09 0.10 0.17 0.18 Fast Device (-40 C, low V CC ) ATX Timing (UI) 0.05 0.06 0.13 0.14 0.26 0.30 Alignment (UI) 0.04 0.05 0.08 0.09 0.18 0.20 Timing (UI) 0.05 0.06 0.12 0.14 0.26 0.30 Alignment (UI) 0.04 0.05 0.08 0.09 0.18 0.19 Fast Device (25 C, high V CC ) ATX Timing (UI) 0.05 0.06 0.13 0.15 0.26 0.30 Alignment (UI) 0.04 0.05 0.05 0.06 0.12 0.13 Timing (UI) 0.04 0.05 0.11 0.13 0.22 0.26 Alignment (UI) 0.04 0.05 0.06 0.14 0.15 December 2012 Altera Corporation Serial Digital Interface II Reference Design for Stratix V Devices

Page 6 Getting Started Table 2 lists the characterization data for fpll cascade in a noisy condition (SDI + adjacent HSSI channels toggling at 3 Gbps + 70% core noise). Table 2. fpll Cascade to ATX or PLL in Noisy Condition Characterization Data Rate SD-SDI HD-SDI 3G-SDI Timing (UI) 0.2 1 2 SMPTE Specification Alignment (UI) 0.2 0.2 0.3 Slow Device (-40 C, low V CC ) ATX Timing (UI) 0.05 0.06 0.15 0.17 0.31 0.37 Alignment (UI) 0.05 0.10 0.11 0.22 0.24 Timing (UI) 0.05 0.06 0.19 0.21 0.37 0.43 Alignment (UI) 0.05 0.12 0.13 0.23 0.25 Fast Device (-40 C, low V CC ) ATX Timing (UI) 0.05 0.06 0.17 0.20 0.34 0.41 Alignment (UI) 0.04 0.05 0.10 0.11 0.22 0.24 Timing (UI) 0.05 0.06 0.17 0.21 0.35 0.41 Alignment (UI) 0.04 0.05 0.10 0.11 0.21 0.24 Fast Device (25 C, high V CC ) ATX Timing (UI) 0.05 0.06 0.18 0.20 0.35 0.39 Alignment (UI) 0.04 0.05 0.07 0.09 0.16 0.17 Timing (UI) 0.04 0.05 0.17 0.19 0.32 0.36 Alignment (UI) 0.04 0.05 0.08 0.18 0.19 Getting Started This section discusses the following topics to help you execute the reference design: Software Requirements Hardware Requirements Compiling the Design in the Quartus II Software Setting Up the Board Configuring the FPGA Using the Quartus II Programmer Running the Design Software Requirements The reference design requires the following software and IP: Quartus II software SDIIIMegaCore function Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction Transceiver Reconfiguration Controller PHY IP Core Serial Digital Interface II Reference Design for Stratix V Devices December 2012 Altera Corporation

Getting Started Page 7 Hardware Requirements The reference design requires the following hardware: Stratix V GX FPGA development kit SDI High-Speed Mezzanine Card (HSMC) BNC cables Mini SMB cables Compiling the Design in the Quartus II Software To compile the design, perform the following steps: 1. Download and unzip the reference design file (s5gx_sdi_ii.zip) in your local project directory. 2. Launch the Quartus II software. 3. On the File menu, click Open Project. Select the s5_golden_top.qpf project file from the project directory and click Open. 4. On the Processing menu, click Start Compilation. Setting Up the Board To set up the board, perform the following steps: 1. Connect the SDI HSMC to the HSMC port B of the Stratix V GX FPGA development board. Refer to Figure 3. 2. Set the board settings DIP switch (SW5), JTAG DIP switch (SW3), and FPGA mode select DIP switch (SW4). Refer to Table 3 for the switch settings. 3. Connect the development board to the power supply. DIP Switch Settings Table 3 lists the switch settings and descriptions. Table 3. DIP Switch Settings (Part 1 of 2) Schematic Signal Switch Name Board Settings DIP Switch 1 CLK_SEL 2 CLK_ENABLE 3 FACTORY_LOAD 4 SECURITY_MODE Description ON: SMA input clock select. OFF: Programmable oscillator input clock select (default 100 MHz). ON: On-Board oscillator enabled. OFF: On-Board oscillator disabled. ON: Load user 1 design from flash at power up. OFF: Load factory design from flash at power up. ON: Do not send FACTORY command at power-up. OFF: Send FACTORY command at power-up. Default OFF ON ON ON December 2012 Altera Corporation Serial Digital Interface II Reference Design for Stratix V Devices

Page 8 Getting Started Table 3. DIP Switch Settings (Part 2 of 2) Switch Schematic Signal Name Description Default JTAG DIP Switch (1) 1 5M2210_JTAG_EN 2 HSMA_JTAG_EN 3 HSMB_JTAG_EN 4 PCIE_JTAG_EN FPGA Mode Select DIP Switch (2) ON: Bypass MAX V CPLD System Controller. OFF: MAX V CPLD System Controller in-chain. ON: Bypass HSMC port A. OFF: HSMC port A in-chain. ON: Bypass HSMC port B. OFF: HSMC port B in-chain. ON: Bypass PCI Express edge connector. The on-board USB-Blaster II or external USB-Blaster is the chain master. OFF: PCI Express edge connector in-chain. 1 MSEL0 Configuration setting 0 ON 2 MSEL1 Configuration setting 1 ON 3 MSEL2 Configuration setting 2 ON 4 MSEL3 Configuration setting 3 OFF 5 MSEL4 Configuration setting 4 ON 6 ON Notes to Table 3: (1) If you plug in an external USB-Blaster cable to the JTAG header (J10) on the board, the on-board USB-Blaster II is disabled. The JTAG chain is normally mastered by the on-board USB-Blaster II. (2) Set MSEL[4:0] to valid configuration schemes as listed in the Stratix V Device Handbook. OFF ON OFF ON f For more information about the switch settings, refer to the Stratix V GX FPGA Development Board User Guide. Serial Digital Interface II Reference Design for Stratix V Devices December 2012 Altera Corporation

Getting Started Page 9 Figure 3 shows how to connect the SDI HSMC to the Stratix V GX FPGA development board. Figure 3. Board Setup User LEDs (D7-D10, D18-D21) User DIP Switch (SW1) SDI HSMC Video Ports (Channel 0) SDI Video Ports (Channel 1) Stratix V FPGA Development Kit SDI HSMC Table 4 lists the physical ports for each SDI channel. Table 4. Physical Ports Physical Port SDI Channel Hardware Rx Tx 0 Stratix V GX FPGA development board SDI_IN_1 (J9) SDI_OUT_1 (J8) 1 SDI HSMC SDI_RX (J16) SDI_TX (J17) Table 5 lists the function of the push buttons on the development board. Table 5. Push Buttons Push Button Function CPU_RST Global reset PB2 PB1 Resets transceiver channel 1 PB0 Resets transceiver channel 0 December 2012 Altera Corporation Serial Digital Interface II Reference Design for Stratix V Devices

Page 10 Getting Started Table 6 lists the functions of the user-defined DIP switch (SW1) on the development board. Use this DIP switch to configure the video pattern generator. Table 6. User-Defined DIP Switch (SW1) Switch Function 0: 75% colorbars 7 1: 100% colorbars 0: Generate colorbars 6 1: Generate pathological pattern 5 LED indication. Refer to Table 7. 3 0 0000: SD - 525i 0001: SD - 625i 0010: HD - 1080i60 0011: HD - 1080i50 0100: HD - 1080p24 0101: HD - 720p60 0110: HD - 720p30 0111: HD - 1080p30 1000: HD - 1080p25 1001: 3Ga - 1080p60 1010: 3Ga - 1080p50 1011: 3Gb - 2x1080i60 1100: 3Gb - 2x720p30 1101: 3Gb - 2x1080p30 1110: 3Gb - 1080p60 1111: 3Gb - 1080p50 Others: Invalid Table 7 lists the function of each user-defined LED on the development board. Table 7. User-Defined LED Indication (Part 1 of 2) User LED D7 D8 D9 D10 SW1.5 = ON Indicates the heartbeat of the transmitter clock out (channel 0) Indicates that the receiver is TRS locked (channel 0) Indicates that the receiver is frame locked (channel 0) Indicates the heartbeat of the receiver recovered clock out (channel 0) Description SW1.5 = OFF Indicates the heartbeat of the transmitter clock out (channel 1) Indicates that the receiver is TRS locked (channel 1) Indicates that the receiver is frame locked (channel 1) Indicates the heartbeat of the receiver recovered clock out (channel 1) Serial Digital Interface II Reference Design for Stratix V Devices December 2012 Altera Corporation

Getting Started Page 11 Table 7. User-Defined LED Indication (Part 2 of 2) User LED D18, D19 D20, D21 SW1.5 = ON Transmitted signal in the SDI HSMC video port, SDI_OUT_1 (channel 0) [D19, D18]: 00: SD 01: HD 10: 3Gb 11: 3Ga Received signal in the SDI HSMC video port, SDI_IN_1 (channel 0) [D21, D20]: 00: SD 01: HD 10: 3Gb 11: 3Ga Description SW1.5 = OFF Video pattern generator signal in the development board s SDI video port, SDI_TX (channel 1) [D19, D18]: 00: SD 01: HD 10: 3Gb 11: 3Ga Received signal in the development board s SDI video port, SDI_RX (channel 1) [D21, D20]: 00: SD 01: HD 10: 3Gb 11: 3Ga Configuring the FPGA Using the Quartus II Programmer You can use the Quartus II Programmer to configure the FPGA with a specific.sof file. 1 Before configuring the FPGA, ensure that the Quartus II Programmer and the USB-Blaster II driver are installed on the host computer, power to the board is on, and no other applications that use the JTAG chain are running. To configure the FPGA on the development board, perform the following steps: 1. Connect the USB cable to the board. 2. Launch the Quartus II software. 3. On the Tools menu, click Programmer. 4. Click Auto Detect to display the devices in the JTAG chain. 5. Click Add File. Select the s5_golden_top.sof file from the project directory and click Open. 6. Turn on the Program/Configure option for the added file. 7. Click Start to download the selected file to the FPGA. Configuration is complete when the progress bar reaches 100%. 1 This design is volatile and must be reloaded each time you power on the board. December 2012 Altera Corporation Serial Digital Interface II Reference Design for Stratix V Devices

Page 12 Getting Started Running the Design Run the design variants in the following sections to view the example test results. Test Pattern Transmitter To run the test pattern demonstration, follows these steps: 1. Connect an SDI signal analyzer to the channel 1 transmitter output, SDI_TX (J17). 2. Check the result on the SDI signal analyzer. LEDs D18 and D19 indicate the internal video pattern generator signal, which transmits through the SDI_TX port in the transmitter. Figure 4 shows the LED indication. Figure 4. LED Indication for Test Pattern Demonstration D7 D8 D9 D10 D18 D19 D20 D21 User LEDs Stratix V GX Development Kit Receiver To run the receiver demonstration, follow these steps: 1. Connect an SDI signal generator to the channel 1 receiver input, SDI_RX (J16). The LEDs indicate the following conditions: LEDs D20 and D21 indicate the receiver signal. LED D8 illuminates when the received line format is stable at the SDI_RX port. LED D9 illuminates when the receiver frame format is stable at the SDI_RX port. Figure 5 shows the LED indication. Figure 5. LED Indication for Receiver Demonstration D7 D8 D9 D10 D18 D19 D20 D21 User LEDs Stratix V GX Development Kit Serial Digital Interface II Reference Design for Stratix V Devices December 2012 Altera Corporation

Getting Started Page 13 Serial Loopback To run the serial loopback demonstration, follow these steps: 1. Connect the channel 1 transmitter output, SDI_TX (J17) to the channel 1 receiver input, SDI_RX (J16). The LEDs indicate the following conditions: LEDs D18 and D19 indicate the internal video pattern generator signal, which transmits through the SDI_TX port in the transmitter. LEDs D20 and D21 indicate the receiver signal standard. LED D8 illuminates when the received line format is stable at the SDI_RX port. LED D9 illuminates when the receiver frame format is stable at the SDI_RX port. Figure 6 shows the LEDs indication. Figure 6. LED Indication for Serial Loopback Demonstration D7 D8 D9 D10 D18 D19 D20 D21 User LEDs Stratix V GX Development Kit (SW1.5 = OFF) Parallel Loopback To run the parallel loopback demonstration, perform the following steps: 1. Connect an SDI signal generator to the channel 0 receiver input, SDI_IN_1 (J9). 2. Connect an SDI signal analyzer to the channel 0 transmitter output of SDI_OUT_1 (J8). The LEDs indicate the following conditions: LEDs D20 and D21 indicate the receiver signal. LED D8 illuminates when the received line format is stable at the SDI_IN_1 port. LED D9 illuminates when the receiver frame format is stable at the SDI_IN_1 port. December 2012 Altera Corporation Serial Digital Interface II Reference Design for Stratix V Devices

Page 14 Document Revision History Figure 7 shows the LEDs indication. Figure 7. LED Indication for Parallel Loopback Demonstration D7 D8 D9 D10 D18 D19 D20 D21 User LEDs Stratix V GX Development Kit (SW1.5 = ON) Document Revision History Table 8 lists the revision history for this document. Table 8. Document Revision History Date Version Changes December 2012 1.0 Initial release. Serial Digital Interface II Reference Design for Stratix V Devices December 2012 Altera Corporation