Final Exam CPSC/ECEN 680 May 2, 2008 Name: UIN: Instructions This exam is closed book. Provide brief but complete answers to the following questions in the space provided, using figures as necessary. Show your work for partial credit. 1. (10 pts) In a regular SOC, a TAM is used to deliver test patterns and collect test results from the cores. Suppose you have a TAM that has 10 data lines, and all cores have MISRs so that test results do not have to be read while the test patterns are delivered. We will ignore the time to read back the MISRs. Consider an SOC with 4 cores. Core 1 has test patterns that can be delivered on 3 lines in 10000 cycles, 6 lines in 5000 cycles or 10 lines in 3000 cycles. Core 2 has test patterns that can be delivered on 3 lines in 20000 cycles, 4 lines in 15000 cycles or 5 lines in 12000 cycles. Cores 3 and 4 have test patterns that can be delivered on 2 lines in 20000 cycles or 4 lines in 10000 cycles. Draw the shortest test schedule.
2. PODEM Algorithm i. (12 pts) In the figure below, use the PODEM algorithm to test for a SA1 on the output of gate 6. Write on the figure and explain the sequence of decisions. ii. (3 pts) The algorithm will not select A=0 and B=0. Why not? SA1
3. (15 pts) For the circuit below, the flip-flops numbered 7 and 8 are connected together in a scan chain (assume the scan chain is from 7 to 8). Their D inputs can be directly observed as pseudoprimary outputs (PPOs). The flip-flop outputs Q1 and Q2 can be directly controlled as pseudoprimary inputs (PPIs). Compute the combinational SCOAP testability measures on all lines - both controllability and observability, including the clock CL. The flip-flops do not have a set/reset line. Write your SCOAP measures on the figure using standard notation. Extra copies of the circuit are attached to the exam to aid you in working out your solution. Do you need to compute the sequential SCOAP measures? Why or why not?
4. You have a chip with yield Y and a test set with fault coverage T. i. (3 pts) For Y=90% and T=99%, what is the defect level in DPM? ii. (4 pts) Your customer complains that the defect level is too high. They want you to reduce it to 100 DPM. What yield Y would be necessary to achieve this, given T=99%? iii. (3 pts) What fault coverage T would be necessary to achieve this 100 DPM, given Y=90%?
5. You wish to implement an LFSR using the characteristic polynomial x 6 + x 5 + x 3 + x 2 + 1. i. (5 pts) Draw the schematic for a modular LFSR (XOR gates between the flip-flops). Show a signal to initialize the LFSR via the flip-flop set/reset pins. The pins are active low. ii. (5 pts) Draw the schematic for an external LFSR (XOR gates on the feedback path). Show a signal to initialize the LFSR via the flip-flop set/reset pins. The pins are active low. The starting state does not have to be the same as the internal LFSR above.
6. (10 pts) For a modular LFSR implementing the primitive polynomial x 6 + x 5 + x 3 + x 2 + 1, add minimal hardware to the LFSR so that it will also generate the all-zero state, while also generating all of its previous states. Between which two states will the all-zero state be inserted? Remember that the flip-flop outputs have true and complement values available. Draw the schematic of the LFSR with all-zero logic. Do not show the set/reset logic.
7. A test set achieves 100% toggle coverage. That is, it sets every line in the circuit to both a 0 and a 1 at least once in the test set. i. (5 pts) Does such a test set achieve 100% stuck-at fault coverage? Explain your answer. Use examples as needed. ii. (5 pts) Why will a toggle test have relatively high bridge fault coverage in an I DDQ test? Explain your answer. Use examples as needed.
8. (5 pts) Give an example of how scan test can have higher power dissipation than functional operation. 9. (5 pts) Suppose that the maximum data rate of a link using embedded clock to connect CPU to memory is 10 Gbps, but you need a bandwidth of 40 Gbps. How would you solve this problem?
10. (10 pts) Show input and line values for a delay test along one of the longest robustly-testable paths in the circuit below. Assume each gate has unit delay. Remember that a robust test is one that will detect a delay fault independent of other delays in the circuit, so it should still work correctly even if the gates have arbitrary delays.
Extra sheets for Problem 3.
Extra sheets for Problem 3.