Engineer To Engineer Note EE-203 Technicl Notes on using Anlog Devices' DSP components nd development tools Contct our technicl support by phone: (800) ANALOG-D or e-mil: dsp.support@nlog.com Or visit our on-line resources http://www.nlog.com/dsp nd http://www.nlog.com/dsp/ezanswers Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port Contributed by Thorsten Lorenzen September 1, 2003 Introduction The purpose of this note is to describe how to hook up video devices such s the ADV7183 NTSC/PAL Video Decoder to the externl bus of the ADSP-BF535 Blckfin Processor. Becuse of its rchitecture nd video processing cpbilities, Blckfin will interfce with video devices. The ADSP-BF535 s the first prt of the Blckfin Processor fmily is not equipped with stndrd interfce tht glueless intercts with video devices, but s this EE-Note shows, the Asynchronous Interfce cn be used to receive video dt in ITU-656 formt. Future Blckfin derivtives will be equipped with interfces designed to support video devices (PPI interfce). ADV7183 NTSC/PAL Video Decoder The ADV7183 is n integrted video decoder tht utomticlly detects nd converts stndrd nlog bse bnd television signl comptible with world wide stndrds NTSC or PAL into 4:2:2 or 4:1:1 component video dt comptible with 16-bit/8-bit CCIR601/CCIR656 or 10/20-bit extended stndrds. The dvnced nd highly flexible digitl output interfce enbles performnce video decoding nd conversion in both frme buffer bsed nd line locked bsed systems LLC Mode. This mkes the device idelly suited for brod rge of pplictions with diverse nlog video chrcteristics including tpe bsed sources, brodcst sources, security/surveillnce cmers nd professionl systems. Bsics of nlog video composite signls To fully understnd the decoders digitl output it is helpful to review the bckground of the NTSC stndrd nd how it cme long. If you re fmilir with it lredy plese go to the next chpter. The first color television system ws developed in the United Sttes nd begn brodcsting in 1954. For economic resons, requirement ws mde tht monochrome receivers must be ble to disply the blck nd white portion of color brodcst nd tht color receivers must be ble to disply monochrome brodcst. For brodcsting purposes ll required signls must be fitted into single line. However, the CVBS signl looks still s yers go for comptibility purposes. The nlog composite video signl ws designed wy it is shown s follows. Imgine, CRT (Cthode Ry Tube) of TV such s shown in Figure 1 hs been designed to disply video imge bsed on N lines in the visul re ctive video of the monitors surfce. In generl, the ry of the CRT strts t the top left side nd goes to the right. After reching the right end it turns off nd goes bck Copyright 2003, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.
to the left, line below. Reching the left side it turns on gin nd drws the next line on the screen. By repeting this the monitor will lwys be drwn with the help of the CRTs ry. Wht kind of signls re required to fully drive the CRT? In Figure 1 NTSC Video Composite Signl cn be seen. It drives the CRT in sense tht it runs s discussed bove. Even Field Odd Field Line 1 Line 3.. Lst Line Line 2 Line 4.. Lst Line Line 1 Line 3.. Lst Line Blnk CVBS Figure 1: Multiple lines of n nlog video composite signl (CVBS) In generl the video composite signl hs two mjor tsks. First, the CRT (Figure 1) runs from the left to the right, from the top to the bottom controlled by its own oscilltors nd sidetrck units. But it must be controlled (triggered) by signls tht comes long (is ligned to) with the signl tht holds the imge dt. Otherwise the imge cn never be plced on the screen in correct order. Such signls re clled: Horizontl Sync (Line Blnking Signl), to force the CRT to turn off the ry nd strt with the next line. The Line Blnking re in Figure 2 shows such signl. Verticl Sync, to force the CRT to turn off the ry t the end of frme/field nd strt with the next frme/field. The right end of the CVBS signl on Figure 1 Blnk shows such signl. Second, the imge dt is split into prts of luminnce nd chrominnce informtion s (Y) Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 2 of 12
(C). Figure 2 shows the two informtion s combined with the syncs in single line. Luminnce: As it cn be seen in the re of Active Video Line the steps show different levels of luminnce displying br of different vlues in brightness. Chrominnce: The gry squres in Figure 2 represents 9 cycles of 3.58MHz frequency s shown underneth the signl. The cycles re crrying the color informtion. The first gry squre in the re of Color Burst drives n extr oscilltor build into the video receiver nd holds the cycles s reference. The following squres cycles will be compred with the reference (Color Burst). The phse shift between these determines the hue. Color sturtion is implemented by the cycles mplitude. Line Blnking Color Burst Active Video Line Figure 2: One line of Video Composite Video Signl As mny s lines the video resolution includes s mny line signls must be implemented in the video composite signl. Decoding the nlog composite video signl by the ADV7183 in LLC mode It hs been discussed how the nlog composite video signl looks like. This section is dedicted to understnd the signl pth of the decoder when in CVBS mode. Just one of the two ADCs re used for conversion After the nlog signl hs pssed the ADC it goes into luminnce pth to seprte the luminnce informtion. Also, it goes into chrominnce pth to seprte the chrominnce informtion. In the luminnce pth the 10-bit dt from the ADC is pplied to n ntilising low pss filter tht is designed to bnd-limit the input video signl such tht ntilising does not occur. In CVBS mode notch filter must be used to remove the unwnted chrominnce dt tht lies round the subcrrier. The next step is peking filter. This filter offers shrpness function on the luminnce pth. The dt is then pssed through resmpler to correct for linelength vritions in the input video. The resmpler is designed to lwys output 720 pixels per line. In the chrominnce pth the 10-bit dt from the ADC is first demodulted s it is chieved by multiplying the loclly generted qudrture subcrrier, where the sign of the cos subcrrier is inverted from line to line ccording to the PAL switch. The low pss filter is pplied to remove components t twice the subcrrier frequency. The chrominnce dt is then pssed through n bnd-pss filter to remove unwnted luminnce dt. After shping filter is pplied the dt is pssed through resmpler to correct for line length vritions in the input video. It lwys outputs 720 pixels per line. The output formtter block does tke the luminnce nd chrominnce dt nd put it in the order s it is shown in Figure 3. Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 3 of 12
As is cn be seen the ctul video dt hs been embedded in the dt block (Active Video). Active video dt is seprted by blnking nd synchroniztion. Due to the ITU-656 recommendtion it lwys begins nd ends with the premble ( FF 00 00 DA 10 80 10 80 10 80 10 80 FF 00 00 C7 ). Figure 13 shows video strem blnking nd the premble included. Alterntively, the synchroniztion vlues embedded in the dt strem cn lso be provided with the help of externl lines pins. Figure 3 show such lines DV, VREF, HREF. Even Field Odd Field Line 1 Line 2.. Lst Line Line 1 Line 2.. Lst Line Blnk CVBS 16-bit BUS HREF Video Blnk Video Blnk Video Blnk Video Blnk Video Blnk DV VREF t Figure 3: Anlog input nd digitl output of n video decoder Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 4 of 12
Asynchronous Interfce of the ADSP-BF535 The processors synchronous interfce is used to receive the video dt. 32-bit dt cn be fetched in mnner it is shown in Figure 4. DMA is set up to red 32x32-bit dt words (shown s Chnnel 2, the /ARE signl). However, the DMA chnnel cn be progrmmed to mximum number of 64k words. The gp between these 32 words is required for loding the next DMA descriptor. Chnnel 2 Figure 4: ADSP-BF535 Asynchronous Timing As mentioned in the ADSP-BF535 Blckfin Hrdwre Reference Mnul fter red cycle is initited the Async Memory Select line (/AMSx), Async Output Enble line (/AOE) nd the Async Red Enble line (/ARE) become sserted. After multicycle Red Access dely (Configured by the Async Interfce Bnk Control Register), the /ARE pin normlly de-ssert to complete the red opertion. As the processors externl memory mp is split into four bnks of synchronous memory regions there re four seprte select lines AMS[3:0] dedicted to ech memory bnk. The timing is equivlent to the red enble line /ARE unless dditionl hold cycles re inserted. The /AMSx lines cn be tken to ct s chip select CS to different devices by ccessing different memory bnks. Due to the rchitecture of the ADSP-BF535, DMA-controlled dt downlod is somewht non-intuitive. Ech DMA dt trnsfer is split into bursts of eight red ccesses. After the burst, gp ppers becuse of internl bus ctivity. Figure 5 illustrtes this. As shown below the first Figure 5: ADSP-BF535 DMA Red Bursts Becuse of ech DMA trnsfer is split into bursts of eight ccesses (in this configurtion, four bursts per DMA execution) the understnding of this behvior is crucil for developing proper DMA interfce. Figure 6 zooms into one of these burst ptterns to nlyze how mny cycles re tken for ech ccess. Figure 6: ADSP-BF535 DMA Red Accesses Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 5 of 12
The peripherl clock SCLK is displyed in chnnel 1 nd chnnel 2 shows the /ARE pin. After eight red strobes re done nine extr SCLK cycles re tken to plce the dt into internl memory. Interfce the ADSP-BF535 into the ADV7183 The ADSP-BF535 synchronous interfce is configured to mke full use of its 32-bit externl memory interfce, in order to gin mximum throughput. As the ADV7183 is configured to run in 16-bit LLC synchronous mode its output does not meet the timing requirements of the processors synchronous interfce in more thn one topic. 1. The 16-bit bus must be extended to gin mximum throughput over the 32-bit bus. 2. As discussed in the chpter before, due to the descriptor relod the processor is not ble to receive dt while it is in the reloding process. Dt of the ADV7183 would get lost without the use of ny hold mechnism. 3. SDRAM could never be ccessed without the use of externl buffers s long s the video decoder trnsfers dt sequentilly (Dt/Address busses re multiplexed). 4. Without ny logic ctive video dt s well s control informtion s Blnking embedded in the dt would be received. Although, the control informtion s re not needed it would be trnsferred nd wste memory spce. All these topics hs been tken to design n interfce tht serves these. In this ppliction exmple the decision ws mde to tke FIFOs of IDT. The IDT72V06 is dul port FIFO memory tht opertes t power supply voltge between 3.0V nd 3.6V. It lods nd empties dt on first-in/first-out bsis. It uses Full, Hlf Full nd Empty flgs to prevent dt overflow nd underflow. The reds nd writes re internlly sequentil through the use of ring pointers, with no ddress informtion required to lod nd unlod dt. Dt is toggled in nd out of the devices through the use of the Write (/W) nd Red (/R) pins. The IDT72V06 FIFO incorportes 9-bit dt pth. In order to tke it four of them must be connected in prllel to mke it comptible to the ADSP-BF535 32-bit interfce. Figure 7: Picture of the ctul ppliction Figure 7 shows the ctul ppliction. Its designed s dughter crd tht fits on the ADSP-BF535 EZ-KIT Bord. As it cn be seen on top is the ADV7183 evlution bord connected. Both bords re prt of Anlog Devices evlution environments. IDT tody offers more enhnced FIFOs s it hs been tken in this EE-Note. The chpter Design Improvements shows n lterntive prt tht fits better with less glue logic Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 6 of 12
As it cn be seen in Figure 8 the FIFOs re designed in between the processor nd the video decoder. Lets strt with the connections to the Blckfin ADSP-BF535. As discussed erlier the ADSP-BF535 is fitted with the 32-bit synchronous interfce. The 32-bit dt bus is linked to the FIFOs output Q[7:0]. The Asynchronous Memory Select Line 1 /AMS1 is linked to the Red Line /R of the FIFOs. Tking /AMS1 indictes tht the processors Memory Bnk 1 must be ccessed to ctivte the FIFOs. The FIFOs Hlf Full Flg /HF indictes hlf full nd the ADSP-BF535 should strt downlod to prevent dt overflow. Tht s why its connected to progrmmble flg GPIO1. A processor interrupt driven by the progrmmble flg GPIO1 strts the downlod. In generl, there is no connections of the Blckfin to the video device. It just wits until it indictes tht the FIFO must be emptied. The key point cn be found between the Video Decoder nd the DATA /AMS1 D[31:0] Q[7:0] /R /HF /W /RS P[7:0] FIFOs. Two min functions must be implemented. First: Automticlly, it should be detected the strt of the first frme otherwise the frmes cn not be reconstructed. Second: The FIFOs should not be filled with blnk dt. Blnk dt just wstes memory. The D-Flip Flop 74LV74D t the bottom of Figure 8 is designed in to detect the strt of the first frme fter power up or mnully reset ctivted by progrmmble flg. With the help of the signl VREF nd FIELD supplied by the video decoder the Dt trnsfer will be enbled t the first stge. The Dt Vlid signl DV indictes frctions of ctive video. With the help of logicl AND the DV signl nd the Flip Flop output of VREF nd FIELD defines signl tht enbles trnsfer t the second stge. P[15:0] Video Source P[15:0] ADSP- BF535 D[15:8] D[23:16] Q[7:0] /R /HF Q[7:0] /R /HF /W /RS /W /RS P[15:8] P[7:0] 74LV74D D CK0< / CLR 74LV74D 74LV08D DV LLC2 ADV 7183 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 74LV02D < 1 D[31:24] Q[7:0] /R /HF /W /RS 4 X FIFO IDT 72V06 P[15:8] ADM 708 SAR /RESET /MR SCCB Interfce to configure the device / D CK0< CLR =1 74LV08D VREF FIELD /OE SCL SDA Figure 8: ADSP-BF535 video connection block digrm Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 7 of 12
To extend the 16-bit bus of the Video Decoder to become 32-bit bus comptible with the ADSP- BF535 second Flip Flop is used t the finl stge. As it cn be seen on top of Figure 8 the second Flip Flop hlf s the frequency. It links the output line to the top FIFOs write line nd links the output line / to the bottom FIFOs write line. Alterntely, the 16-bit bus will be linked to both FIFO pirs. Due to this logic the FIFOs will just be filled with video dt. Dt Downlod Procedure With regrds to the discussion bove the norml procedure to receive video dt in this system is s follows. After power up the FIFOs will be filled with dt when strt of field occurred. All this will be ignored becuse the processor is not redy to run. The first ction of the Blckfin softwre is to ssert GPIO2 in order to reset the system mnully. The progrmmble flg drives supervisory circuit effecting the Flip Flops nd FIFOs to reset. The first video field fter reset fills the FIFOs. After the FIFOs re hlf full the /HF pin will be sserted. The ssertion of /HF genertes n processors interrupt vi GPIO1. The interrupt service routine includes instructions to strt descriptor bsed DMA. The IDT72V06 includes 16k ddress spce so tht the /HF pin sserts fter it hs been filled with 8k of dt. To prevent memory underflow the mximum number of DMA trnsfers must be limited to 8k. When the DMA trnsfer is finished the next descriptor will be loded utomticlly but the trnsfer will not continue. The dt lredy received cn be processed. As soon s the FIFOs indicte been hlf full gin the next DMA trnsfer is ctivted. LLC2 VDt Y[7:0] /MLW /MHW DV VREF Field /Reset FF Strt Figure 9: ADV7183 output nd video system timing This process repets s long s it is not turned off by softwre. Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 8 of 12
In generl DMA engine is designed to trnsmit dt independently of core ctivities. While the first portion of dt will be processed the next portion cn be received without interrupting the core. Figure 9 shows the timing from ADV7183 to the FIFOs. After RESET hs been de-sserted VREF will ssert t the beginning of the next field. The pin DV will remin de-sserted s long s just blnking goes over the bus. At the beginning of the first visul line (ctive video) DV will ssert nd remin sserted while ctive video is trnsmitted in the ctul line. At the end of the line DV will de-ssert nd remin until the next visul line. While DV remins sserted lterntively the FIFOs gets filled triggered by the top Flip Flop (/MLW nd /MHW). As its output nd inverted output re tken ( nd /) the top FF expends the 16-bit bus to n 32- bit bus. Design Performnce. As in the chpter Interfce the ADSP-BF535 into the ADV7183 covered the SDRAM could never be ccessed if the bus would be tken for the video downlod lredy. Due to the fct tht the Blckfin Processor empties the FIFO much fster thn it is filled by the video decoder the bus remin idle in between. Figure 10 (chnnel 1) shows blocks of memory strobes (/AMS1). If the processors peripherl clock (SCLK) runs t 120MHz nd the externl port is set to run t mximum speed it tkes 400µs to downlod 8k words (32-bit). After ech downlod the bus remins in idle. Chnnel 2 of Figure 10 shows signl pek triggered by the hlf full flg of the FIFOs. Tht results in Blckfin processor interrupt which strts the next DMA trnsmission. From the end of trnsmission one to trnsmission two tkes 1.04ms.This is left for SDRAM or ny other ccess vi the externl port. Figure 10: ADSP-BF535 performnce test result Design Improvements Tody s FIFOs re much more enhnced thn the one tken for this project. The min resons for tken the IDT72V06 ws the vilbility s well s the pckge size. The IDT72V06 is vilble in PLCC pckge insted of the IDT72T36105 discussed below. However, the next IDT genertion of FIFOs like the IDT72T36105 provides bus widths up to 36 bits in single chip. It supports fetures like synchronous nd synchronous timing, retrnsmit, progrmmble lmost full nd empty flgs, bus mtching These chips provide lot of functionlities tht decrese the number of externl logic required. Asynchronous vs. Synchronous Timing: The device cn be progrmmed to meet the synchronous timing s it is required for Blckfin s well s synchronous timing required for the video device. Retrnsmit: Allows to trnsmit the dt stored mny times. Progrmmble lmost full/empty flgs: A progrmmble threshold of certin level when the pin sserts. As mentioned before tking the hlf full flg wstes lot of memory. A Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 9 of 12
cheper chip with less memory could be chosen if the lmost full fg is progrmmble. Bus Mtching: The input bus of the FIFO cn be limited to 18 bits while the output keeps the width of 36. This wy the device collects 18 bit words nd pcks it to be 36 bit words. No glue logic is required for ltertion. Figure 11 shows schemtic tht includes such device. This schemtic is just recommendtion but hs never been tested on hrdwre. DATA D[31:0] FIFO IDT 72T36105 D[31:0] Q[15:0] P[15:0] P[15:0] /AMS1 /RD /WEN DV GPIO 1 /PAF GPIO 2 /REN WCLK 74LV08D LLC2 /PRS 74LV74D ADSP- BF535 / D CK0< CLR =1 ADV 7183 GPIO 3 GPIO 4 ADM 708 SAR /RESET /MR 74LV08D VREF FIELD /OE GPIO 5 GPIO 6 SCCB Interfce to configure the device SCL SDA Figure 11: Enhnced ADSP-BF535 video connection block digrm Conclusion This note should hve given n ide on how to connect devices like the ADV7183 video decoder to the ADSP-BF535. It hs been discussed the processors behvior of the externl port (EBIU) especilly in combintion with DMA trnsfers. A stndrd video source (ADV7183), the digitl signl obtined from nd the wy it cn be implemented in the video signl chin hs been covered. Furthermore the glue logic required nd the connections to such devices. Derivtes s such s the ADSP-BF533 will be equipped with interfces (PPI) tht fit glueless to this sort of video devices. Additionlly, the PPI interfce will include fetures like ITU-656/601 support. The dt strem will be investigted by the PPI nd optionlly skip blnking, skip even or odd smples to select bw/color smples or skip field 1 or 2. Also, externl sync signls re supported (HSYNC/VSYNC). Future processors will hve even more support s such s on-fly seprtion of luminnce nd chrominnce vlues, windowing of n re of interest, re-smpling 4:4:4>4:2:2, RGB/YUV conversion, down smpling or up smpling. Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 10 of 12
For lower speed devices it is referred to the note EE-181. EE-181 is dedicte to show how single chip CIF cmers cn be connected to the ADSP-BF535. Such cmers supply n output clock of bout 8MHz. ADSP-BF531/532/533 Support The ADSP-BF531/532/533 is lredy equipped with PPI Interfce. The use of ny glue logic is not necessry. Due to the fct tht the PPI is hlf duplex bi-directionl port it is not cpble for multiple video devices. But if for ny reson two PPI interfces re required the 16-bit externl port of the ADSP-BF531/532/533 cn lso be tken s it is done in this note to mke second PPI. Figure 12 shows this. With the help of just two FIFOs nd nerly the sme logic the ADV7183 cn lso be connected to the ADSP- BF531/532/533 externl port. The ADSP-BF531/532/533 does not show the sme behvior s the ADSP- BF535 on the externl port due to design chnges. The gps re not existing nymore. Plese see the Hrdwre Reference Mnul DATA /AMS1 D[15:0] Q[7:0] /R /HF /W /RS P[7:0] P[15:0] 2 X 74LV08D P[15:0] ADSP- BF535 D[15:8] Q[7:0] /R /HF /W /RS 2 X FIFO IDT 72V06 P[15:8] 74LV74D LLC2 DV ADV 7183 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 ADM 708 SAR /RESET /MR SCCB Interfce to configure the device / D CK0< CLR =1 74LV08D VREF FIELD /OE SCL SDA Figure 12: ADSP-BF533 video connection block digrm Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 11 of 12
Premble = FF 00 00 DA Premble = FF 00 00 C7 Blnking Active Video Dt Figure 13: ITU-656 Digitl Video Dt Strem References [1] IDT 72V06 Dtsheet, August 2001 Integrted Device Technology Inc [2] IDT72T36105 Dtsheet, June 2002 Integrted Device Technology Inc [3] ADV7183 Dtsheet, Rev 0, 2002. Anlog Devices Inc [4] ADSP-BF535 Dtsheet, Rev PrC, 2002. Anlog Devices Inc [5] ADSP-BF535 Blckfin Processor Hrdwre Reference Mnul, Second Edition, Mrch 2003 [6] Video Demystified by Keith Jck, Third Edition, 2001 Document History Version September 01, 2003 by T. Lorenzen. Description Initil Relese Interfcing the ADSP-BF535/ADSP-BF533 Blckfin Processor to NTSC/PAL video decoder over the synchronous port (EE-203) Pge 12 of 12