SOC Implementation for Christmas Lighting with Pattern Display Indication RAMANDEEP SINGH 1, AKANKSHA SHARMA 2, ANKUR AGGARWAL 3, ANKIT SATIJA 4 1

1016 SOC Implementation for Christmas Lighting with Pattern Display Indication RAMANDEEP SINGH 1, AKANKSHA SHARMA 2, ANKUR AGGARWAL 3, ANKIT SATIJA 4 1 Assistant Professor, Department of EECE, ITM University, Gurgaon, INDIA 2, 3, 4 UG Student, Department of EECE, ITM University, Gurgaon, INDIA 1 ramandeepsingh@itmindia.edu, 2 akankshaa4m@gmail.com, 3 aggarwalankur1993@gmail.com, 4 ankitsatija8808@gmail.com ABSTRACT The presented paper deals with the implementation of Light Emitting Diode (LED) patterns on a dedicated System on a Chip using selection switches in Verilog language. The LEDs glow in different patterns depending on the switch selected by the user. The seven segment display indicates the corresponding switch number selected by the user. Keywords: System on chip, Christmas lighting, LED pattern, Verilog, Xilinx 1. INTRODUCTION The project is designed for the purpose of decorative lighting during the Christmas festival. The aim has been to implement the lighting technique on a system on chip (hereby referred to as SOC) in Verilog language. A system, in general, can be defined as the combination of devices that produces an output after processing a given input. A system on chip is a dedicated integrated circuit that consists of all the components required for the execution of the system [1]. Verilog is a widely used hardware description language (HDL) in designing electronic systems and digital circuits [2]. Verilog allows designers to write compact and concise codes for large circuits quickly [3]. The physical realization of Verilog modules can be obtained by the synthesis software that transforms the Verilog modules into equivalent elementary logic gate operations (AND, OR, NOT etc.) [4]. Field-programmable gate arrays (FPGA) consist of different logic gates that can be used in different combinations. FPGA boards are configured using HDL languages such as Verilog used in this project. The FPGA board used in this project is Nexys3 Xilinx Spartan6. The Christmas lighting system has been implemented on the LEDs, selection switches and seven segment display provided on the FPGA board. There are 8 LEDs, 8 selection switches (out of which 6 has been used) and 4 seven segment display mounted on the Nexys3 board. The system offers six different lighting patterns to the user. The 6 selection switches produce 6 different patterns on the LEDs, each switch providing one pattern at a time. The seven segment display generates the corresponding pattern number that has been selected by the user. 2. BLOCK DIAGRAM The system is divided into three parts namely, the input, processor and the output. The input block consists of the selection switches through which the user gives the input to the system which pattern he wishes to be displayed. The Nexys3 board has six slide switches attached on the board. The position of the slide switches generates the corresponding high or low level. The system bus size from the input switches to the Spartan6 FPGA is six. The processor consists of the Xilinx Spartan6 FPGA which reads the input from the switches and sends the desired control signals to the output. The output block consists of two units the light emitting diodes and the seven segment display (SSD). The Light Emitting Diodes are anode-connected to the FPGA via 390- ohm resistors. They turn on when a logic high voltage is applied to their respective input/output pin [5]. The LEDs glow in the pattern directed by the signals from the processor. There is a four-digit common anode sevensegment LED display on the Nexys3 board. Each digit is a seven segment display which is composed of seven LEDs embedded in a figure 8 pattern [5]. The 4-digit display gets these seven cathode signals as inputs. The digit display is enabled when it gets a common anode signal as input. The SSD displays the number of the pattern selected by the user. Figure 1 displays block diagram of the system used for the implementation of led pattern using selection switches and seven segment display. 3. PATTERNS IMPLEMENTED IN SYSTEM ON CHIP Six LED patterns have been implemented on the SOC. The Nexys3 board has 8 LEDs attached on the board. The patterns are a combination of triggering these LEDs in on and off state. Table 1 given below shows the details of the patterns implemented.

1017 8 Light Emitting Diodes Input from Switches / 6 Spartan 6 FPGA / 4 / 8 Seven Segment Display Fig.1. Block Diagram of the System. Each pattern is explained in detail below: 3.1 All LEDs glow In the first pattern all the LEDs are given a high voltage and are switched on. 3.2 Right Shift Mode In the second pattern, the LEDs appear to be shifting in right direction. Each LED glows one by one. At start, the first LED goes high for a short time period. When the first LED is turned low, it triggers the second LED to high. This is repeated eight times until the last LED is high. When the last LED goes low, the first LED is again triggered to high. This makes the LEDs appear to be glowing in a right shift pattern. 3.3 Left Shift Mode In the third pattern, the LEDs appear to be shifting in left direction. It is the same as the second pattern, the only difference being the last LED is high at the start. The LEDs are triggered in a similar fashion as in the previous pattern until the first LED is high. When the first LED goes low, the last LED is again triggered to high. This makes the LEDs appear to be glowing in a right shift pattern. 3.4 Blinking Mode In the fourth pattern, the LEDs blink at equal intervals of time. All the LEDs are given a high voltage for a short time period. Then the LEDs are kept low for the same time period. These two steps are repeated in a continuous loop. This makes the LEDs appear to be blinking. 3.5 Alternate Blinking Mode In the fifth pattern, the LEDs blink in alternate turns. The pattern is an extension of the blinking mode in which when all even numbered LEDs are high, the odd numbered LEDs are low, and vice versa. 3.6 Converging Mode In the sixth pattern, the LEDs appear to be converging. At start, the first and last LED is high for a short time period. When it turns low, the second and seventh LED is turned high. Similarly, the third and sixth LED is turned high after previous LEDs turn low. And lastly the fourth and fifth LED is turned high. After it turns low, again the first and last LED is turned high. This makes the LEDs appear to be glowing in a converging pattern. Table 1. Patterns implemented in SOC. Pattern Pattern Name Number 1 All LEDs glow 2 Right Shift Mode 3 Left Shift Mode 4 Blinking Mode 5 Alternate Blinking Mode 6 Converging Mode 4. ACTUAL PICTURE OF PROJECT Figure 2 shows SOC implementation of LED pattern and seven segment display using selection switches on Nexys3 Xilinx Spartan6 FPGA. Figure 2(a) shows the pattern 1 implemented in which all LEDs glow and corresponding number (1) displayed on the SSD when selection switch 1 is selected. Figure 2(b) shows the pattern 5 implemented in which alternate LEDs blink on and off and corresponding number (5) displayed on the SSD when selection switch 5 is selected on the Nexys3 board. 5. ALGORITHM AND FLOWCHART The system starts when the power is turned on. The system takes input from the six selection switches on the Nexys3 board. The position of the switches forms a six digit binary number with the corresponding value of the switches. In this manner, six cases are defined for selection of six different switches. The number formed is then compared to pre-defined values in the code. If a condition becomes true, then that particular piece of code is executed. Accordingly, the LEDs glow in the desired pattern that is mentioned in the condition. If a condition

1018 becomes false, it checks for another match, and skips the previous condition. This is repeated for six conditions. If no selection switch is selected, all conditions become false. In this case, the LEDs are turned off and zero is indicated on the seven segment display. The complete process is repeated in a loop until the power is turned off. Figure 3 displays the flowchart of the SOC implementation for Christmas lighting using pattern display indication. Fig.2(a). Actual Picture of Pattern 1 (all LEDs glow) implementation on Nexys3 Xilinx FPGA. Fig.2(b). Actual Picture of Pattern 5 (alternate blinking mode) implementation on Nexys3 Xilinx FPGA. 6. RTL VIEW GENERATED abcd is the name of the Verilog module that has been used in the SOC implementation. There are a total of 7 input lines and 15 output lines in the system. The input consists of a clock source denoted by clock_100 in the figure and six selection switches that are denoted by s0 to s5. The output consists of 8 lines for the light emitting diode (LED) display having one output line for each LED, and 7 output lines for the seven segment display (SSD). The 8 LEDs are treated as a single array and are denoted by led(7:0). Similarly, the seven segment display is also treated as an array and denoted by ssout(6:0) in the figure. Figure 4 shows the register transfer level (RTL) generated by the SOC implementation for Christmas lighting on Xilinx Spartan6 FPGA. 7. APPLICATION The system on chip implementation for LED patterns has a variety of applications, the very first being Christmas lighting. Christmas lightings offer a variety of patterns on LEDs that make it more attractive. This SOC implementation can be used as a decorative lighting for every occasion. The LED patterns can be used as warning lights that glow up in case of emergency. Furthermore, this pattern can be programmed to display active train and flight statuses. 8. ADVANTAGES & COMPARISON LEDs are power efficient and consume very little power in comparison to other light sources such as bulbs or tube lights. LEDs occupy less space and can be accommodated in very small areas. A dedicated system on chip implementation for LED patterns can be tailor made for different applications with little changes required in the programming. The most advantageous factor for using SOC implementation for LED patterns is the huge reduction in cost as LEDs are cheap resources. A few existing Christmas lighting are available only in single mode that offer no different patterns. This SOC implementation is better as it gives the user different patterns for the Christmas lighting with the option of choosing any pattern he desires.

1019 START TAKE INPUT FROM SWITCHES SWITCH=1 LED PATTERN = 1 SSD = 1 SWITCH=2 LED PATTERN = 2 SSD = 2 SWITCH=3 LED PATTERN = 3 SSD = 3 SWITCH=4 LED PATTERN = 4 SSD = 4 SWITCH=5 LED PATTERN = 5 SSD = 5 SWITCH=6 LED PATTERN = 6 SSD = 6 NO LED PATTERN SSD = 0 STOP Fig.3. Flowchart of SOC Implementation.

1020 Fig.4. Register Transfer Level 9. CONCLUSION & FUTURE SCOPE The system on chip implementation for Christmas lighting using selection switches and seven segment display was successfully implemented on Nexys3 Xilinx Spartan6 FPGA board. Each switch generates a different LED pattern and the seven segment display indicates the corresponding pattern number. However, there are a lot of features that can be added in the future. The SOC has more than eight input / output lines. More LEDs can be connected to these output lines. More number of LEDs will make the Christmas lighting look better. Further, there can be variants in size of the Christmas lighting. Currently, the LEDs glow only in green color. This can be improved in other versions of Christmas lighting. Multicolor LEDs can be used and the user can select the desired color by his choice. This can be easily implemented using some additional LED drivers. 10. RESULT The Christmas lighting implementation was simulated on software before hardware testing. The simulation software used was ISlim. The clock input was given a clock pulse. Each input switch was forced to a high value to get the result. The output displayed the corresponding values for LED array led(7:0) and seven segment display array ssout(6:0). The simulation results obtained after implementing the SOC for Christmas lighting on Xilinx software are shown below: When switch 1 is selected, pattern 1 is implemented on the LEDs. Switch 1 goes high, and all the LEDs are given a high voltage. Number 1 is displayed on the seven segment display. Fig.5(a). Simulation Result when Switch 1 is selected When switch 2 is selected, pattern 2 i.e. Left Shift Mode is implemented on the LEDs. Switch 2 goes high and number 2 is displayed on the seven segment display. Fig.5(b). Simulation Result when Switch 2 is selected

1021 When switch 3 is selected, pattern 3 i.e. Right Shift Mode is implemented on the LEDs. Switch 3 goes high and number 3 is displayed on the seven segment display. Fig.5(c). Simulation Result when Switch 3 is selected When switch 4 is selected, pattern 4 i.e. Blinking Mode is implemented on the LEDs. Switch 4 goes high and number 4 is displayed on the seven segment display. Fig.5(d). Simulation Result when Switch 4 is selected When switch 5 is selected, pattern 5 i.e. Alternate Blinking Mode is implemented on the LEDs. Switch 5 goes high and number 5 is displayed on the seven segment display. Fig.5(e). Simulation Result when Switch 5 is selected When switch 6 is selected, pattern 6 i.e. Converging Mode is implemented on the LEDs. Switch 6 goes high and number 6 is displayed on the seven segment display. Fig.5(f). Simulation Result when Switch 6 is selected When no switch is selected, no pattern is implemented on the LEDs. All switches are low and number 0 is displayed on the seven segment display. Fig.5(g). Simulation Result when Switch is selected

1022 ACKNOWLEDGEMENTS Every project big or small is successful largely due to the effort of a number of wonderful people who have always given their valuable advice or lent a helping hand. We sincerely appreciate the inspiration, support and guidance of all those people who have been instrumental in making this project a success. We take this opportunity to express our profound gratitude and deep regards to ITM University, Gurgaon for the confidence bestowed in us and entrusting our project. It would not be possible to complete this research without great support of ITMU in providing the resources and the laboratory equipment required for the research. We also take this opportunity to express a deep sense of gratitude to our lab assistants for their cordial support, valuable information and guidance in their respective fields, which helped us in completing this task through various stages. REFERENCES [1] Brackenbury L.E.M., Plana L.A., Pepper J. (2010), System on Chip design and implementation, Education. IEEE Transactions, Vol. 53,. 2, pp. 272-281 [2] Dawson C., Pattanam S.k., Roberts D. (1996), The Verilog Procedural interface for the Verilog hardware description language, Verilog HDL Conference.1996, Proceedings. 1996 IEEE International, pp. 17-23 [3] Ebeling C., French B. (2007), Abstract Verilog: A hardware description language for novice students, Microelectronics Systems Education. 2007 (MSE 07) IEEE International Conference, p.p.105-106 [4] Smith, David R. (1996), Hardware Synthesis from encapsulated Verilog Module, Application Specific Systems. Architectures and Processors. 1996 ASAP Proceedings of International Conference, pp. 284-292 [5] Nexys3 Board Reference Manual. Revision: vember 22, 2011 [Online] http://forums.xilinx.com/xlnx/attachments/xlnx/edk/22262/1/nexys3_rm.pdf