Probe Card System for DHP Chip Testing VXD Workshop, Wetzlar, February 4-6, 213 H. Krüger, Bonn University
4x JTAG 4x LVDS Gbit TX 4x JTAG 64x HSTL 18x CMOS PXD modules are sensitive to singlepoint-of-failure of the DHP Up to know very little statistics of the DHP yield (+ flip chip mounting to wirebond adapters with low yield only) Need to qualify ICs before flip-chip mounting Motivation To/from DCD (86 CMOS/HSTL) DHP 4 x LVDS To Switcher (4x LVDS) To/from DHH (9x LVDS) VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 2
What is needed: DHP Chip Probing Prerequisites Needle card for solder bump probing Test bench for DHP environment IO signals from test system (DHH like) DCD input/output emulation Test procedure to provide full coverage Definition of cut parameters for chip classification Design is based on DHP.2 DHPT 1.x will be pin compatible to DHP.2 VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 3
VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn DAC 4 DHP Chip Probe Test System Power Supply Needle Card PCB GPIB or USB DHP test system (XUPV5 FPGA Board) Infiniband JTAG FPGA DCD emulation Sequencer r/b Probe Needles Eth DHP Probe Station
Thousands 3685µm VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 2µm 5-1 -2-3 1 2 3 bumps to connect: 159 out of 296 18µm Thousands 159 bumps need to be connected Material: lead free, LTS Pitch: 2µm (y), 18µm (x) ~11µm diameter Connections: JTAG (4x LVDS) Timing (4x LVDS) Data Link (1x CML) Aux clock (2x LVDS) SWITCHER (4x LVDS) DCD out (8x 8 HSTL) DCD in (8x 2 CMOS) DCD timing (2x CMOS) DCD JTAG DCD_ref (analog) DHP test system FPGA Power (8x VSS, 4x VDD, 2x VDD_CML) PLLxx2Fast FrameSync ResetB (CMOS) Analog IO test signals 3685µm
1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 1 A no bump 2 B 3 C 4 D 5 E 6 F 7 G 8 H 9 J 1 K 11 L 12 M 13 N 14 O 15 P 16 Q 17 R 18 S 19 T 2 U 21 V 22 W 23 X 24 Y 25 Z 26 AA 27 AB 28 AC 29 AD 3 AE 31 AF 32 AG 33 AH 34 AJ 35 AK 36 AL 37 AM 1 3 5 7 9 11 13 15 17 19 21 23 25 29 31 33 35 18 18 2 18 4 18 6 18 8 18 1 18 12 18 14 18 16 18 18 18 2 18 22 18 24 18 26 18 28 18 3 18 32 18 34 18 36 36 1 36 3 36 5 36 7 36 9 36 11 36 13 36 15 36 17 36 19 36 21 36 23 36 25 36 36 29 36 31 36 33 36 35 54 54 2 54 4 54 6 54 8 54 1 54 12 54 14 54 16 54 18 54 2 54 22 54 24 54 26 54 28 54 3 54 32 54 34 54 36 72 1 72 3 72 5 72 7 72 9 72 11 72 13 72 15 72 17 72 19 72 21 72 23 72 25 72 72 29 72 31 72 33 72 35 9 9 2 9 4 9 6 9 8 9 1 9 12 9 14 9 16 9 18 9 2 9 22 9 24 9 26 9 28 9 3 9 32 9 34 9 36 18 1 18 3 18 5 18 7 18 9 18 11 18 13 18 15 18 17 18 19 18 21 18 23 18 25 18 18 29 18 31 18 33 18 35 126 126 2 126 4 126 6 126 8 126 1 126 12 126 14 126 16 126 18 126 2 126 22 126 24 126 26 126 28 126 3 126 32 126 34 126 36 144 1 144 3 144 5 144 7 144 9 144 11 144 13 144 15 144 17 144 19 144 21 144 23 144 25 144 144 29 144 31 144 33 144 35 162 162 2 162 4 162 6 162 8 162 1 162 12 162 14 162 16 162 18 162 2 162 22 162 24 162 26 162 28 162 3 162 32 162 34 162 36 18 1 18 3 18 5 18 7 18 9 18 11 18 13 18 15 18 17 18 19 18 21 18 23 18 25 18 18 29 18 31 18 33 18 35 198 198 2 198 4 198 6 198 8 198 1 198 12 198 14 198 16 198 18 198 2 198 22 198 24 198 26 198 28 198 3 198 32 198 34 198 36 216 1 216 3 216 5 216 7 216 9 216 11 216 13 216 15 216 17 216 19 216 21 216 23 216 25 216 216 29 216 31 216 33 216 35 234 234 2 234 4 234 6 234 8 234 1 234 12 234 14 234 16 234 18 234 2 234 22 234 24 234 26 234 28 234 3 234 32 234 34 234 36 252 1 252 3 252 5 252 7 252 9 252 11 252 13 252 15 252 17 252 19 252 21 252 23 252 25 252 252 29 252 31 252 33 252 35 2 4 6 8 1 12 14 16 18 2 22 24 26 28 3 32 34 36 Bump coordinates in µm Origin in upper left corner No bump at location (,) Bumps with no needle connection shown in gray VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni 6 Bonn
VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 8 DHP.2 Layout Examples from vendor
PCB with active components, will need some debugging Very sensitive with needles attached Debug Probe Card Dedicated debug Probe Card (almost) same netlist as needle card PCB replace needle footprint with DHP.2 wire bond adapter Debug PCB is ready and tested DHP communication FPGA programming (DCD emulation, Switcher sequencer read-back) Debug Probe Card VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 9
Specs 6 layer PCB 3mm thick mechanical stiffness Needle Card PCB Status PCB Design & Production Component mounting Testing Needle mounting needs ~4 weeks (@ HTT) Needle Probe Card (w/o needles) VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 1
Needle card fixture We have diced chips only put single chips on chuck (Ok for now) chess board fixture with array of cavities for production testing tbd External components: Power supply DHP test system (FPGA board via Infiniband cables) extra JTAG for on board FPGA programming/readback, optional: can use JTAG from Infiniband connection Probe Station Setup VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 11
Probe Card System Status Hardware components of the needle card test system Debug probe card for HW verification and debugging Needle probe card: components mounted and tested, shipped for needle mounting end of January (takes ~4 weeks) Mechanical fixture for probe station Software based on DHP test system from Mikhail ( ) needs further extensions (for basic testing ok) Planning (more) systematic sequencer and DHP DAC output read-back automation of test sequences coverage definition of cut parameters Start commissioning of the needle card system by end of Feb First (rudimentary) tested DHP chips supposed to be available in March VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 12
DHP Chip Availability Only small number of DHP.2 chips left (~15) Next chip version (DHPT 1.) available by mid 213 Need certain number of tested chips for E-MCM and PXD6 large matrix assemblies Possible scenarios: a) DHP has high yield, enough Ok tested die for E-MCM + PXD6 (very optimistic) no action needed b) DHP yield not sufficient, need more chips (more likely) i) Buy remaining MPW chips from MOSIS (rather expensive) ii) iii) Wait for DHPT 1. to become available (maybe too late) Recover unsuccessful DHP.2 flip chip assemblies (quite a few) Recovery procedure De-solder and clean DHP chips (Valencia?) Place new bumps (Heidelberg?) VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 13