MIT International Journal of Electronics and Communication Engineering, Vol. 2, No. 2, Aug. 2012, pp. (83-88) 83 BIST- Built in Self Test A Testing Technique Alpana Singh MIT, Moradabad, UP, INDIA Email: Aalps_646@rediffmail.com Manas Singhal MIT, Moradabad, UP, INDIA Vijay Kumar HOD D.V.S.I.E.T., Meerut, UP, INDIA Email: dec2vijay@gmail.com Priyanka Gupta D.V.S.I.E.T., Meerut, UP, INDIA Email: gupta.priyanka105@gmail.com Pallavi Saxena MIT, Moradabad, UP, INDIA Email: pspallavisaxena@gmail.com ABSTRACT VLSI chips have an enormous complexity and their density doubles every two years. The increasing level of integration results in small features size, and high proximity of functional units. This makes the circuits highly susceptible to external faults which call the need for testing. In this paper we have discussed the testing techniques BIST, since overall cost associated with the circuit implemented using BIST is much less in comparison to all other testing techniques. I. INTRODUCTION These are some chip level testability problems of the late 1990s [1]. There is an extremely high and still increasing logic to pin ratio on the chip. This increasingly makes it harder to accurately observe signals on the device, which is essential for testing. VLSI devices are increasingly dense and faster with submicron feature sizes. There are increasingly long test pattern generation and test application times. Prohibitively large amount of test data must be stored in the ATE. There is increasing difficulty in performing at speed (rated clock) testing using external ATE. For clock rates approaching 1GHz, at speed testing with an ATE is very expensive due to pin inductance and high tester pin costs. 1.1 What is BIST? How does it work? The ability of logic to verify a failure free status automatically, without the need for externally applied test stimuli (other than power and the clock), and without the need for the logic to be part of the running system. 1.2 Basic BIST Architecture During normal system operation, the input isolation circuitry (multiplexer) selects the system inputs to be applied to the CUT. The active BIST start signal resets the counter used to address the TPG and the ORA ROM via the active high clear input to the n bit binary counter. The active BIST start signal also resets the active high BIST done and pass/fail indicators via the two synchronous R S latches. The BIST sequence is activated by setting BIST start to a logic 0, so that the counter begins to count, which in turn, addresses and reads the input test pattern from the TPG ROM and the corresponding expected output responses from the ORA ROM. As the input test pattern read from the TPG ROM are applied to the CUT via the input isolation multiplexer, the output responses of the CUT are compared to the expected output responses being read from a ORA ROM. The ORA comparator will produce a logic 1 in the case of any mismatch between the expected and actual output responses, which in turn turns the pass/fail indication high. When a n bit counter has finished counting, all of the test patterns stored in the TPG ROM have been applied to the CUT. Therefore, when the counter rolls over, the active high carry out from the counter will set the R S latch producing a logic 1 on the BIST done to indicate that the BIST sequence has completed. The type of BIST architecture explained above
MIT International Journal of Electronics and Communication Engineering, Vol. 2, No. 2, Aug. 2012, pp. (83-88) 84 is rarely used in practical applications since it requires conventional test vector development and considerable circuit area for the TPG and ORA ROM as well as the counter. Figure 1: Basic BIST Architecture A minor design change to the CUT may require regeneration of the test vectors and expected output responses which in turn would require re-programming the ROMs in the best case and resizing the ROMs and counter in the worst case. Hence, the minor design change to the CUT could call a need for a major change in the BIST implementation. 1.3 BIST Implementation The Figure 2 shows a BIST implementation using Built in Logic Block Observer (BILBO) [2]. BILBO 1 is configured as an LFSR pattern generator for testing CUT 1, while BILBO 2 is configured as the response compactor to compact the responses of the CUT 1. During this process the behaviour of CUT 2 is ignored. BILBO 2 is configured as an LFSR pattern generator to test CUT 2 in the circuit, while BILBO 1 is configured as a response compactor to compact the responses of CUT 2. Figure 2: BILBO in BIST implementation 1.4 Types of Test Sequences (Deterministic versus Pseudo Random Testing) The determination of a test pattern usually involves feedback from a fault model; in a first step a list of all faults considered by the fault model is made. In the second step a test pattern is assumed and all faults detected by it are removed from the fault list. Repeating this step for new test patterns progressively reduces the fault list. Towards the end of the iteration process the contribution of a new pattern decreases, since the fault list becomes small. One new pattern may be needed to remove one single fault from the list, while other new patterns do not make any contribution at all. Although an exhaustive application of this deterministic algorithm [3] promises the detection of all detectable faults, the duration of the search process and the length of the resulting test pattern may be excessive. A special case of the deterministic test is the exhaustive test, for which all possible test patterns are applied. While this test produces the best possible coverage, it is impracticable for a complete VLSI chip. Considering the partitioning method, a sum of exhaustive tests can be applied progressively to all parts of the circuit. This method is called Pseudo Exhaustive Test. Test pattern generation for the exhaustive and Pseudo exhaustive test [4,5,6] is trivial and does not involve fault simulation. In a completely different approach, a fixed number of test patterns is generated without feedback from the fault model. This sequence of test patterns is called Pseudo Random, because it has some important properties of a random sequence, while being totally predictable and repeatable [4]. The coverage of the test sequence is checked by fault simulation. If a sufficient coverage level has been reached, the set is accepted, otherwise, a new one is generated. One drawback of this pseudo random algorithm, is that the required length of the test sequence is often hard to determine a priori. Although a sequence found by this approach does not necessarily have the best fault coverage possible, it has advantages over the deterministic search: II. For a reasonable coverage limit, the determination of a sequence is extremely fast. The random patterns can easily be generated on chip by a hardware random generator. Since cost is an extremely critical issue in every design, the deterministic approach may have to be terminated at a quite early iteration stage. In this case, the results of the random approach with comparable cost may be superior. BIST RESPONSE COMPACTION Compaction A method of drastically reducing the number of bits in the original circuit response during testing in which some information is lost. Some trivial schemes for response Compaction: Parity checking, in this parity is determined across all circuit responses; Ones counting, in this we count the number of 1 s in the output response from the circuit [7]. Transition count, in this the number of times, signal in the circuit response change during BIST, is counted. NOTE: Aliasing occurs when the compacted response of the bad circuit matches the compacted response of a good circuit and is always a drawback associated with compaction, because information is lost.
MIT International Journal of Electronics and Communication Engineering, Vol. 2, No. 2, Aug. 2012, pp. (83-88) 85 III. LFSR FOR RESPONSE COMPACTION Frohwerk [8] introduced the LFSR for response compaction by signature analysis. In this method, the circuit output data stream is treated as a descending order coefficient polynomial. The output response compactor LFSR performs polynomial division of this data stream polynomial by the characteristics polynomial of the LFSR. The final state of the LFSR is the polynomial remainder of this division. The error detection hypothesis is that the output data stream from a faulty CUT changes the output data stream, and hence the remainder of this polynomial division, which is used as the signature in this compaction method. for analog circuitry has not received sufficient attention until recent years. Hence, testing the analog portion of mixed signal systems has been identified as one of the major challenges for the future and BIST has been identified as one of the potential solutions to this testing problem.[10] Figure 5: BIST architecture for mixed-signal system Figure 3: Example of LFSR 3.1 Multiple Input Signature Register Consider the case when the circuit has many outputs then large number of flip flops and Ex OR gates are required so as to implement the LFSR for each output response. However, we can exploit the fact that the hardware pattern generation and response compaction system using LFSR is a linear system, obeying the equation: X(t+1) = TsX(t). Hence, if we superimpose all of the responses of the different outputs in the same LFSR for response compaction, then the final remainder will be the sum of the remainder due to all the circuit output s. This is highly advantageous, since, it reduces the hardware required. This new response compactor is known as MISR (Multiple Input Signature Register).[9] Figure 4: Example of multiple input signature register 4.1.1 Basic architecture and operation The digital BIST circuitry includes TPG and ORA functions as well as the test controller. In addition to these analog loopback is used to facilitate the return path for the test signals from the TPG, through the analog circuitry under test, and back to the ORA. An additional mux is required for the isolation of the digital test patterns from the input data stream to DAC. Since the target circuitry under test is a analog system circuit, including DACs and ADCs, the digital TPG and its associated MUX are inserted immediately prior to the inputs of the DACs. Similarly, the digital ORA is incorporated at the ADC outputs. 4.1.2 Output Response Analyzer The ORA, illustrated in the Figure 6, consists of a double precision accumulator used to sum the magnitudes of the sampled output responses from the analog circuitry under test. If the final sum is within a predetermined range of values to account for acceptable variations in the analog component parameters, voltage, and temperature as well as quantization noise in the DAC and ADC, the circuit is declared fault free. Determination of the range of resultant values that indicates the circuit is fault-free is based on specifications of the analog circuit responses to the various input signals produced by the TPG. As a result, the BIST approach can be viewed as a specification oriented testing approach. One advantage of the digital ORA is that the results can be read directly through system digital interfaces during system-level testing without the need for an additional ADC to retrieve the BIST results. The absolute value subtractor is included in the ORA design for phase shift, noise, and overshoot/ringing fault detection. IV. DIFFERENT APPROACHES OF BIST 4.1 Mixed Signal BIST Approach for Analog Circuits Large number of BIST approaches are available for testing the digital portion of mixed signal systems. However, BIST Figure 6: ORA Block Diagram
MIT International Journal of Electronics and Communication Engineering, Vol. 2, No. 2, Aug. 2012, pp. (83-88) 86 4.2 Circular BIST Circular BIST (including CSTP and SST) is an embedded, off-line, and test-per-clock BIST architecture because it uses existing flip-flops from the CUT to construct the TPG and ORA functions [11]. The basic idea of the Circular BIST, SST, and CSTP approaches is to partition the CUT into flip-flops and combinational logic. The flip-flops are augmented with additional logic to operate in a BIST mode to test the combinational logic as well as the flip flops themselves. The basic application of Circular BIST to a CUT is illustrated in Figure. The circular nature comes from the fact that the output of the last flip flop in the chain is connected to the input of the first flip-flop in the chain to form a circular shift register type of arrangement. 4.3 Logic BIST Architectures The basic idea underlying BIST approaches for the programmable logic resources in FPGAs and CPLDs is to configure groups of PLBs as TPGs and ORAs, and another group of PLBs as Blocks Under Test (BUTs), as illustrated in Fig. below. The BUTs are then repeatedly reconfigured so that they are tested in all of their modes of operation [12]. Each reconfiguration of the FPGA or CPLD to test a different PLB mode of operation is referred to as a test phase. A test session is a collection of test phases that completely test the BUTs in all of their modes of operation. Once the BUTs have been tested, the roles of the PLBs are reversed so that in the next test session the previous BUTs become TPGs or ORAs, and vice versa. If at least half of the PLBs are BUTs during each test session, only two test sessions are needed to test all PLBs in the FPGA or CPLD. This is illustrated in Figure for an 8 M array of PLBs [13]. Figure corresponds to the first four rows of PLBs in test session #1 in Figure 8. Each test phase consists of the following steps: (1) reconfigure the FPGA or CPLD with a BIST configuration, (2) initiate the BIST sequence which includes initialization, test pattern generation, and output response compaction, and Figure 7: Basic implementation of Circular BIST, SST, CSTP Figure 8: Basic Architecture for logic BIST for FPGA s
MIT International Journal of Electronics and Communication Engineering, Vol. 2, No. 2, Aug. 2012, pp. (83-88) 87 (3) read the BIST results from the ORAs. In step 1, the test controller (ATE for wafer/package-level testing; system or maintenance processor for board/system-level testing) interacts with the FPGA/CPLD under test to reconfigure the device by retrieving a BIST configuration from a storage medium and loading it into the configuration memory of the FPGA/CPLD. The test controller also initializes the TPGs, BUTs, and ORAs, and initiates the BIST sequence (via the BIST Start input in step (2), and reads the subsequent Pass/Fail results (step 3). After the test phase is complete, the test controller must reconfigure the FPGA/CPLD for the next test phase, or for its normal system function once the complete BIST session has been executed. Therefore, the normal system function configuration must be stored along with the BIST configurations. There are many other approaches of BIST as well including BIST for regular Structures, Merging BIST, Non intrusive BIST, Scan Based BIST, Pseudo Exhaustive BIST. V. ADVANTAGES OF BIST Vertical Testability:The same testing approach can be used at wafer and device level testing, for all manufacturing testing, and even for system level testing in the field. High Diagnostic Resolution: When BIST is applied to a VLSI device, detection of a fault by the BIST circuitry will not only indicate that a fault exist in the system but will also identify that VLSI device as faulty. When fault occurs, the BIST hardware is designed to indicate, via an error signal or bus, which sub assembly is faulty. This greatly reduces repair cost. At Speed Testing: All testing by the BIST circuitry is performed at the system clock frequency and it facilitates the detection of faults that lead to excessive delay. Eliminates the need for expensive external test machines [14]. The cost of ATE machines is driven the number of test vectors that must be stored, the speed at which the input test patterns must be applied and the output responses monitored, as well as the number of I/O pins that must be serviced. Burn in testing: In this, the VLSI device or PCB is put under stress conditions, including high voltage at high and low temperatures, to expose defects, that will lead to infant mortality [12]. To fully stress the part, the device or PCB must also process data at a high effective data rate for long periods of time. With the self contained TPG and ORA functions provided by BIST, burn in testing can be performed more economically than having test machines applying external test patterns and monitoring the output responses for failures since only power and clock signals must be applied to the device or PCB, once the BIST sequence is initiated. Reduced manufacturing test time and cost. It is difficult to carry a test stimulus involving hundreds of chip inputs through many layers of circuitry to the chip under test, and then convey the test result back through many circuits layers to an observable point. BIST localizes testing, that eliminates these problems. VI. FUTURE SCOPE OF BIST There are some of the following disadvantages regarding this technique and the work is still going on these. Area Overheads: Larger chip area results in fewer chips per wafer and hence, higher cost per chip [15]. Performance Penalty: Larger signal routing paths, as the system function is spread out to make room for BIST circuitry. Increased power dissipation: Due to high data activity, during BIST sequence, can present problems in some system applications, such as, those with power consumption or temperature restrictions. Additional design time and effort. Additional risk to the project: Since, we are now faced with the task of designing and verifying proper operation of the BIST system, in addition. REFERENCES [1] B. Koenemann, J. Mucha, Built in Test for Complex Digital ICs, IEEE Journal of Solid State Circuits, June 1980. [2] J.Roth, W. Bouricius, Programed Algorithms to Compute Tests to Detect and Distinguish between Failures in Logic Circuits, IEEE Transactions on Electronic Computers EC, pp. 547-580, 16-October-1967. [3] E. McCluskey, Built in Self Test Techniques, IEEE Design and Test of Computers, IEEE Computer Soc. Press, Silver Spring, MD, pp. 21 36, April 1985. [4] P.Bardell, W. McAnney, J. Savir, Built in test for VLSI, Pseudo Random Techniques, Wiley, New York,1987. [5] H. Wunderlich, Hochintegrierte Schaltungen: Priifgerechter Entwurfund Test, Berlin,1991. [6] J.Savir, Syndrome-Testable Design of Combinational Circuits, IEEE Trans. on Computers, pp. 442-451, June 1980. [7] R.A. Frohwerk, Signature analysis:a new digital field service method, Hewlett Packard Journal pp. 2-8, may 1977. [8] R. David, Signature Analysis of multi output circuits, In proc. of the international fault tolerant computing symp., June 1984. [9] Semiconductor Industry Association, International Tech. road map for Semiconductors : 1999 Edition, SEMATECH, 1999.
MIT International Journal of Electronics and Communication Engineering, Vol. 2, No. 2, Aug. 2012, pp. (83-88) 88 [10] C. Stroud, An Automated Built-In Self-Test Approach for General Sequential logic Synthesis, Proc. of ACM/IEEE Design Automation Conf., 1988, pp. 3-8. [11] C. Stroud, S. Konala, P. Chen and M. Abramovici, Built-In Self-Test for Programmable Logic Blocks in FPGAs, Proc. IEEE VLSI Test Symp., 1996, pp.387-392. [12] C. Stroud, E. Lee and M. Abramovici, BIST-Based Diagnostics of FPGA Logic Blocks, Proc. IEEE International Test Conf., 1997, pp. 539-547. [13] M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Kluwer Academic Publishers, 2000. [14] C. Buck, The Economic Benefits of Test During Burn-In: Real-World Experiences, Proc. IEEE International Test Conf., 1987, pp. 1086-1093. [15] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, Reading, Massachusetts: Addison-Wesley, 1985.