H-DFT: A HYBRID DFT ARCHITECTURE FOR LOW-COST HIGH QUALITY STRUCTURAL TESTING

H-DFT: A HYBRID DFT ARCHITECTURE FOR LOW-COST HIGH QUALITY STRUCTURAL TESTING David M. Wu*, Mike Lin, Subhasish Mita, Kee Sup Kim, Anil Sabbavaapu, Talal Jabe, Pete Johnson, Dale Mach, Geg Paish Intel Copoation Abstact This pape descibes a Hybid DFT (H-DFT) achitectue fo low-cost, high quality stuctual testing in the high volume manufactuing (HVM) envionment. This stuctue efficiently combines seveal testing and test data compession appoaches to enable application of a huge amount of ATPG and Weighed Random-BIST (WR-BIST) pattens. Results obtained fom the application of the H-DFT technique to industial designs demonstate significant savings in test cost in tems of test data volume and test application time without compomising test quality. Implementation of the H- DFT achitectue on Intel ASIC and micopocesso designs ae descibed. 1. Intoduction Stuctual testing has been used fo decades to educe oveall test cost as well as to aid silicon debug and fault diagnosis [Eichelbege 77, 91]. Vaious foms of stuctual tests such as scan test, logic BIST and memoy BIST [Badell 97, Lin 93, Wu 02] ae used to sceen manufactuing defects to achieve an acceptable DPM level. Intel made a stategic decision seveal yeas ago to gadually shift fom taditional functional testing to stuctual testing [Wu 99]. The key motivation behind this paadigm shift is to minimize the need fo highspeed functional testes and manual test witing effots. Stuctual test, howeve, is facing a big challenge of eve inceasing test data volume and test time due to exponential gowth in the numbe of tansistos pe die, and the need to apply not only stuck-at test pattens but also delay test pattens such as tansition fault pattens. Huge patten size not only inceases test time but also equies additional teste memoy on stuctual testes with inceasing capital cost. Theefoe, it is highly desiable to develop Design fo Testability techniques to significantly educe teste memoy equiements and test time. To facilitate late discussion, a high-level achitectue of a commecial stuctual teste suppoting scan tests is shown in Fig. 1.1. The teste contains a fixed numbe of scan-in channels that ae connected to inputs of scan chains. Each scan-in channel has its own patten memoy to stoe the test pattens applied to the scan input connected to that channel. Similaly, a teste contains a fixed numbe of scan-out channels with patten memoy fo each channel to stoe expected esponse at the scan output connected to that channel. The depth of the patten memoy associated with a scan channel is equal to the maximum numbe of enties that can be stoed in that memoy. In geneal, the depths of patten memoies of scan-in and scan-out channels ae the same. The patten memoies associated with scan-in and scan-out channels ae significantly deepe compaed to those associated with geneal-pupose channels. Nonetheless, fo vey lage chips, such as an Intel micopocesso, the lage patten memoy still may not be enough to apply all equied test pattens. One specific High Volume Manufactuing (HVM) poblem we faced is descibed as follows: Due to the ulta lage numbe of logic gates to be tested, the amount of ATPG pattens exceeds the teste memoy allocation. One of ou test stategy is to apply on-chip Weighted Random BIST (WR-BIST) test pattens to detect easy stuck-at and tansition faults, and continue with ATPG to geneate test pattens tageting difficult stuck-at and tansition faults. Howeve, Ou design may have souces of unknown logic values (X s). As a esult, the cicuit esponse to WR-BIST test pattens cannot be compacted using a Multiple-Input-Signatue-Registe (MISR). To ovecome this poblem, we intentionally bought out the WR-BIST outputs to the egula scan out channels. Once we have done that, anothe issue sufaced: The combined WR-BIST and ATPG pattens and esponses may equie moe teste memoy than the entie teste patten memoy available. The H-DFT achitectue pesented in this pape povides a vey efficient solution to the above poblem without any 0-7803-8106-8/03 $17.00 Copyight 2003 IEEE ITC INTERNATIONAL TEST CONFERENCE 1229

majo change to the coe design and equiing vey little change to existing DFT and test tool flows. Dive Patten memoy -in channels chain 1 chain n Device unde test Geneal-pupose channels Tansceive & Compaato Stuctual Teste -out channels Receive & Compaato Response memoy Figue 1.1: Achitectue of a typical commecial stuctual teste In section 2, the key components of H-DFT achitectue ae descibed and thei applications to some industial design ae illustated. In section 3, the evolution of the H-DFT development phases ae depicted to show the thinking pocess engaged duing the poject development cycles. The potential issues of dependencies of each H-DFT phase ae descibed. In section 4, the application of the H-DFT design in a micopocesso is descibed. Section 5 concludes the esults. 2. Key Components of the H-DFT Achitectue The H-DFT achitectue has gone though seveal diffeent phases of development. Thee ae seveal poposals that have diffeent dependencies on eithe teste achitectue configuation, commecial tools o chip achitectue. But all poposals equie the following key DFT components (1) A WR-BIST engine (2) A Decompesso [Rajski 02, Koenemann 01, Khoche 02], (3) A compesso/compacto [Rajski 02, Koenemann 01, Khoche 02],. In this pape, we will apply eithe Illinois scan [Patel UI] o Xpand as ou Decompesso and use X-Compact as ou Compesso/Compacto. Fo the futue micopocesso H-DFT implementation, we ae also evaluating some commecial Compession and Decompession techniques. 2.1. Weighted-Random BIST Weighted Random BIST (WR-BIST) is a weighted andom patten geneato [Waicukauski 89, Wu 99b] that is implemented on-chip. A majo advantage of WR- BIST is that test pattens ae geneated and the cicuit esponse is analyzed on-chip. Thus, almost no teste memoy is equied to stoe test pattens and vey little teste memoy is equied to stoe the expected esponse. Also, vey few pins ae equied fo WR-BIST although thee may be lage numbe of scan chains inside the chip. WR-BIST techniques geneally use LFSR and weighting logic to geneate weighted pseudo-andom test pattens and Multiple-Input-Signatue-Registes (MISRs) fo esponse analysis. [Eichelbege 91, Waicukauski 89]. The ability of weighted andom BIST pattens to detect defective pats is demonstated in the pape published by Kusko et al [Kusko 01]. Two majo poblems associated with WR-BIST ae: (1) states that cannot be detemined to be 0 o 1 duing simulation (also called X-states), and (2) data contention. Even a single X in the expected esponse of a test patten can coupt the MISR signatue. To avoid this poblem, the H-DFT achitectue uses the X-Compact technique to compact scan chain outputs while toleating X s. Thee ae two types of data contention need to be addessed. Fist, duing WR-BIST, data Contention can occu in two modes: Duing scanning and afte a typical launch and captue system cycle(s). In ou design, we used the following techniques to handle data contentions duing scanning : (1) Contention duing scanning can be handled by the insetion of HOLDSCAN cells at the souce(s) of contention. (2) Contending nodes can be made to be diven fom non-scan cells. To handle data contention duing system cycles, we ecognized that data contention can occu duing and afte system cycles if full decodes of mutually-exclusive signals in the logic ae spead ove moe than one system cycle. To avoid this situation, WR BIST must un with a numbe of system cycles equal to, o geate than, the numbe of cycles acoss which the decoding logic is spead out. Additionally, the biasing logic can be invoked to eliminate the contending test vectos. 2.2 Decompesso 1: Illinois The idea of Illinois is based on the fact that most faults can be detected by test pattens geneated using a scan configuation whee inputs of multiple scan chains ae diven by the same input [Hamzaoglu 99]. Figue 2.2.1 shows an example configuation whee a single scan-in pin dives inputs of 2 scan chains. The hope is that most faults can be detected by test pattens geneated in this configuation. This esults in shote scan chains and educed test vecto memoy depth. Next, fo the few emaining undetected faults, test pattens can be geneated using a egula scan configuation in which the scan chains ae econfigued into longe chains. Fo example, in Fig. 2.2.1 scan chains 1 and 2 can be configued into a longe chain with input diven by IN1, scan chains 3 and 4 can be configued into a longe chain with input diven by IN2, and scan chains 5 and 6 can be configued into a longe 1230

chain with input diven by IN3. In 1 IN 1 IN 2 In 2 In 3 Figue 2.2.1. Illinois. In 4 In 5 IN 3 In 6 To validate the effectiveness of the Illinois, we implemented Illinois in a couple of test chips and compae its test coveage and test data volume with espect to the egula ATPG. The fist test chip has 81 scan-in and 81 scan-out channels, we use Illinois scan with 4 scan-in and 81 scan-out. The esults ae quite supising: both methods got the same test coveage as shown below: Mode Inputs chains Captues Coveage Nomal 81 81 13512 92.40% Illinois 4 81 14373 92.40% Diffeence 861 0.00% The second test chip has 96 scan-in and 96 scan-out chains. The ATPG un gives 91.85% test coveage. We have tied Illinois scan with 4 scan-in and 360 scan-out and obtained 89.36% test coveage. Even though thee is a ~ 2.5% loss in coveage, the teste memoy saving seems able to justify the ROI. We also noticed that the Illinois scan equied 12019 test pattens while the egula ATPG only equied 2740 test pattens to get the same coveage 89.36%. We have implemented the Illinois scan into one of the micopocesso, but the silicon esults will not be eady fo the timing of this yeas ITC. 2.3 Decompesso 2: XPAND The scan achitectue incopoating the XPAND technique, descibed in [Mita 02c], is shown in Fig. 2.3.1. We have a design with n scan chains. The Xpande cicuit is a combinational cicuit, which accepts m bits of input fom the teste and expands it to n bits at evey scan cycle. Application of a scan shift clock is called a scan cycle. Suppose that we need to apply a given n-bit combination of 0s and 1s, denoted by v, to n scan chains duing a cetain scan cycle. This implies that we apply an m-bit combination of 0s and 1s fom the teste, which gets tanslated into n bits by the Xpande cicuit. Given a bound on the maximum numbe of specified (cae) bits in a scan cycle, the XPAND technique is used to systematically design logic cicuits that ae guaanteed to poduce test pattens with the numbe of cae bits in a scan cycle fewe than o equal to the specified maximum. The Xpande cicuit is designed using XOR gates only. Given an n-bit binay combination to be applied to the scan chains at a scan cycle, we can fom linea equations with m input vaiables (coesponding to the Xpande inputs) and ty to solve these equations to find a m-bit binay combination which gets expanded by the Xpande cicuit into the desied n-bit binay combination. Howeve, depending on the specified n-bit binay combination, we may o may not be able to find a solution fo these equations. Suppose that we have a design with n scan chains. Hence, the Xpande cicuit will have n outputs. Suppose that the Xpande cicuit has m inputs. The Xpande design can be epesented as a binay matix with m ows and n columns called the Xpand matix. Each ow coesponds to an Xpande input (input fom the teste) and each column coesponds to a scan chain. The enty in ow i and column j of the binay matix is 1, if and only if the jth scan chain input depends on the ith Xpande input; the matix enty is 0 othewise. chain input coesponding to column j is obtained by XOR-ing all Xpande inputs (matix ows) that have 1s in column j. In 1 Out 1 IN 1 XPAND-e In 2 Out 2 IN m In n Out n Figue 2.3.1. Achitectue with XPAND-e Cicuit. It is inteesting to note that, the Xpand matix coesponding to the Illinois configuation of Fig. 2.3.1 is: 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1231

Anothe Xpande example with 3 inputs and 6 scan chains is shown in Fig. 2.3.2. The coesponding Xpand matix is shown below. 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 Thee is a fundamental distinction between the Illinois of Fig. 2.3.1 and Xpand cicuit of Fig. 2.3.2. If scan chain 1 and scan chain 2 equie diffeent logic values at the same scan cycle, then the Illinois of Fig. 2.3.1 cannot poduce that test patten. Howeve, fo the Xpande cicuit of Fig. 2.3.2, any constaint on 2 scan chains equiing any combinations of logic values can be satisfied. Systematic techniques fo designing Xpande cicuits ae descibed in [Mita 02c]. eos fom one o moe scan chains when any k o fewe othe scan chains poduce X s simultaneously at the same scan-out cycle, hee, k is a design paamete [Mita 02a, Mita 02b]. Depending on the application, seveal stuctues using the X-Compacto may be used. Some of these stuctues and esults obtained fom the application of X-Compact to Intel designs ae also epoted in Appendix. In 1 In 2 Out 1 Out 2 X-C om pacto In n Out n IN 1 IN 2 IN 3 Out 1 Out m Figue 2.4.1 X-Compact Configuation XOR XOR XOR Figue 2.3.2. Xpande Cicuit with 3 inputs and 6 scan chains. 2.4 Compesso/Compacto: X-Compact The X-Compact appoach to educing the test cost, intoduced in [Mita 02a], is shown in Fig. 2.4.1. The X-Compact technique does not compomise the eo detection and diagnosis capability of scan fo all pactical puposes even in the pesence of unknown logic values (often efeed to as X-values). The X- Compact technique is non-intusive and independent of the test pattens used to test the cicuit. Insetion of X- Compact cicuits does not equie any majo change to the Automatic Test Patten Geneation (ATPG) flow. The failing flip-flop in the scan chains can be diectly identified fom the outputs of the X-Compacto cicuit without configuing the chip into a special diagnosis mode. The X-Compacto cicuit block shown in Fig. 2.4.1 is a combinational cicuit consisting of exclusiveo (XOR) gates. The X-Compact design technique allows systematic design of X-Compacto cicuits with minimum numbe of outputs that guaantee detection of 3. Development phases of H-DFT achitectues The goal of the fist development phase of H-DFT achitectue is to find a vey simple yet efficient solution to the test data volume and test time issues without any majo change to the actual design and equiing no majo change to the existing design and test flows. The basic pinciple behind the H-DFT achitectue is to efficiently compact the outputs poduced by the cicuit unde test in esponse to both ATPG and WR-BIST pattens. The H-DFT achitectue allows compession of ATPG test pattens using techniques such as those descibed in the papes published [Koenemann 01, Khoche 02, Rajski 02, Mita 03a]. Fo output esponse compaction, seveal techniques based on signatue analyzes have been published [Badell 97, Banhat 01]. These techniques geneally assume that all bits in the output esponse ae known to be equal to 0 o 1 duing simulation. Howeve, in ou design, it is athe difficult to have a X-fee condition guaanteed fo the entie chip. Recently, a novel idea was poposed to efficiently compact esponse data even with the pesence of unknown values [Mita 02a]. Since this technique has been implemented in some of the Intel ASIC, we decided to adopt this technique as ou main output compession DFT fo H-DFT. This scheme povides extemely lage compaction without compomising test quality and diagnoseability fo all pactical puposes. 3.1 H-DFT-0 Achitectue 1232

Figue 3.1 shows the basic H-DFT-0 achitectue, whee the same scan chains ae used both duing the application of ATPG geneated pattens and when weighted-andom BIST pattens ae applied. Patten geneato ATPG pattens pattens Chain 0 Chain n-1 Chainout [0-n-1] X-compacto Chip bounday Figue 3.1: H-DFT-0 achitectue ATPG compessed outputs m compessed outputs m m Teste s 1 st set of scan-out channels Teste s 2 nd set of scan-out channels Teste s k th set of scan-out channels The cicuit unde test consists of n scan chains. The scan chain inputs ae connected to n input pins duing ATPG mode and connected to n outputs of a WR-BIST engine. The scan chain outputs ae connected to the inputs of an X-compacto, which compacts the n inputs into m outputs. Suppose that the teste has c (= n) scanout channels and c scan-out pins available. If the numbe of available scan-out channels and the numbe of available scan-out pins aen t equal, we choose c to be equal to the minimum of the two. The c scan-out channels (and c scan-out pins) ae divided into k goups each containing m scan-out channels (m scan-out pins), whee k = c/m. The fist goup of m scan-out channels (and scan-out pins) is efeed to as WR-BIST goup 1, the second goup is efeed to as WR-BIST goup 2, and so on the (k-1)th goup is efeed to as WR-BIST goup k-1. Finally, the last goup is efeed to as ATPG goup. The fist goup of scan-out pins ae connected to the fist goup of scan-out channels, the second goup of scan-out pins ae connected to the second goup of scanout channels, and so on. The ith X-Compacto output is connected to the ith scan-out pin of each goup of scanout pins. Thus, the fist X-Compacto output fans out to the fist scan-out pins of goups 1, 2,, k of scan-out pins, the second X-Compacto output fans out to the second scan-out pins of goups 1, 2,, k of scan-out pins, and so on. Teste patten memoy associated with the ATPG goup of scan-out channels stoes the expected fault-fee esponse at the X-Compacto outputs fo the test pattens geneated by ATPG. The H-DFT-0 achitectue suppots a test session when test pattens geneated by ATPG tool ae applied, efeed to as ATPG session. The weighted-andom test pattens applied duing WR-BIST ae divided into k-1 test sessions, efeed to as WR-BIST sessions. Duing the ATPG session, all c scan-in channels as well as the ATPG goup of m scan-out channels and the associated patten memoies ae used. Teste patten memoy associated with the ATPG goup of scan-out channels stoes the expected fault-fee esponse at the X- Compacto outputs fo the test pattens geneated by ATPG. In contast, duing each WR-BIST session, none of the scan-in channels ae used because WR-BIST test pattens ae geneated by on-chip hadwae fo the ith WR-BIST session only one set of m scan-out channels belonging to WR-BIST goup i ae used. This can be specified as pat of the test pogam. Teste patten memoy associated with the a paticula WR- BIST goup of scan-out channels stoes the expected fault-fee esponse at the X-Compacto outputs fo the weighted-andom test pattens applied duing that paticula BIST session. The ATPG session and k-1 WR-BIST sessions ae applied in sequence one afte the othe. Theefoe, H-DFT-0 achitectue can apply both ATPG and WR-BIST test pattens without equiing any additional teste memoy ove what is equied fo application of ATPG test pattens with taditional scan (with no X-Compact and no H-DFT-0 achitectue) as long as the total numbe of test pattens applied ove all k-1 WR-BIST test sessions is less than o equal to k-1 times the numbe of ATPG test pattens. Thus, the X- compacto togethe with the H-DFT-0 achitectue enables application of k-1 sessions of WR-BIST that ae usually applied pio to ATPG pattens to detect a vey high pecentage of stuck-at and/o tansition faults, thus leaving only a vey small pecentage of difficult faults to be tageted by ATPG. Note that, this technique is also applicable in scenaios such as hybid BIST [Das 00] whee ATPG geneated pattens and pseudo-andom pattens ae used togethe. 3.2. H-DFT-1 Achitectue As noted in Sec. 3.1, the application of both ATPG and BIST test pattens using the H-DFT-0 achitectue esults in an incease in test time compaed to conventional scan with only ATPG test pattens. The additional test time, howeve, can be educed if the scan stuctue can be econfigued to suppot a huge numbe of scan chains with popotionally fewe flip-flops pe scan chain duing WR-BIST mode. Thus, thee ae n scan chains duing ATPG test session (whee n is geneally equal to c since thee ae c scan-ins, although thee could be moe scan chains if test patten compession techniques ae used) and s scan chains duing WR-BIST test session, whee s is significantly 1233

geate than c. Since test pattens ae applied fom an on-chip test patten geneato duing WR-BIST sessions, we don t need any exta scan-in channels. Two X-Compacto cicuits ae used, one fo compacting scan chain outputs duing the ATPG session, efeed to as ATPG-X-Compacto in Fig. 3.2, and the othe called BIST-X-Compacto in Fig. 3.2 fo compacting scan chain outputs duing WR-BIST sessions. The ATPG-X- Compacto compacts outputs of n scan chains to m outputs. The BIST-X-Compacto compacts outputs of s scan chains to outputs. It is clea fom Table 2.3.1 that even if s is significantly geate than n, will be slightly geate than m. Note that, the ATPG-X-Compacto and the BIST-X-Compacto cicuits can shae logic between each othe. In this case, the c scan-out channels (and the scan-out pins) ae divided into g = ((c-m)/) +1 goups. The fist goup is the ATPG goup whee the outputs of ATPG-X-Compacto ae connected. The outputs of BIST-X-Compacto cicuit ae fanned out into the emaining g-1 goups that coespond to g-1 BIST sessions. The oveall H-DFT-1 achitectue is shown in Fig. 3.2. The H-DFT-1 achitectue has the following majo benefits: (1) Compaed to the H-DFT-0 achitectue of Fig. 3.1, the test time fo BIST sessions is educed fo the same numbe of test pattens applied in the H-DFT-0 scenaio. This eduction in test time is obtained because the numbe of scan chains duing WR-BIST sessions is significantly highe than the numbe of scan chains in ATPG session. Refeing to the example in Sec. 3.1, suppose that the scan chains ae econfigued so that thee ae only 500 scan chains duing WR-BIST sessions such that the longest scan chain has only 500 flip-flops. Thus, n = c = 50, s = 500. Hence, the numbe of ATPG-X-Compacto outputs (m) is equal to 8, the numbe of BIST-X-Compacto outputs () is equal to 12. Thus, the numbe of WR-BIST sessions (g-1) = 3. Fom the example in Sec. 3.1, time equied to apply 20,000 test pattens duing ATPG session is 0.5 sec. (with scan shift at 200 MHz). Since 100,000 weighted andom pattens wee applied in the pevious example, 30,000 weighted andom pattens ae applied duing the fist two WR-BIST sessions and 40,000 test pattens ae applied duing the thid WR-BIST session. Since the scan chains duing WR-BIST sessions ae 10 times shote than the scan chains duing ATPG mode, the total test time fo WR-BIST sessions is equal to 0.25 seconds. Thus, with the H-DFT-1 achitectue, the oveall test time is 0.75 seconds compaed to 3 seconds with the H-DFT-0 achitectue. (2) The teste memoy equiement is educed fo the same numbe test pattens compaed to H-DFT-0 achitectue. Fo the pevious example, the amount of teste memoy equied duing the ATPG session is the same as that equied with the H-DFT-1 achitectue. Howeve, fo the BIST sessions, only 15M (= 30,000 500) enties ae equied in the patten memoy coesponding to the scan-out channels duing each of the fist and second WR-BIST sessions, and 20M (= 40,000 500) enties ae equied in the patten memoy coesponding to the scan-out channels duing the thid WR-BIST session, compaed to 100M enties equied fo each of the ATPG and WR-BIST sessions equied fo the H-DFT-0 achitectue. (3) Since we have educed the memoy equiement and the test application time as explained in the pevious two scenaios, we could add moe WR-BIST pattens with H-DFT-1 achitectue. Duing each of the fist two WR-BIST sessions we could add additional 170,000 test pattens (since only depth of 15M is used and the length of the longest scan chain duing BIST is 500) and 160,000 test pattens duing the thid BIST session. 3.2.1 Application of H-DFT-1 Achitectue An Industial Design I has two scan stuctues. In ATPG mode, thee ae 100 scan chains with length of the longest chain 4,000. In WR-BIST mode, the numbe of scan chained is expanded to 250 with numbe of flip-flops in the longest scan chain educed to appoximately 1,800. We use two X-Compacto cicuits the fist one with 100 inputs and 9 outputs used fo compaing ATPG outputs, and the second one with 250 inputs and 10 outputs used to compaed WR-BIST outputs. In this case, we divide the scan-out channels into 10 sets. Patten geneato n ATPG pattens pattens s Chain 0 Chain s -1 Chainout [0~n-1] Chainout [0~s-1] ATPG compessed outputs ATPG X-compacto m BIST X-compacto compessed outputs Chip bounday Figue 3.2: H-DFT-1 achitectue. Teste s 1 st set Of scan-out channels Teste s 2 nd set Of scan-out channels Teste s g th set Of scan-out channels Set 1 has 9 scan-out channels and is used fo ATPG mode. The emaining 9 sets have 10 channels each and ae used fo WR-BIST sessions. Note that, this is 1234

possible because in the WR-BIST mode we don t equie any scan-ins. Also, In ATPG mode, we apply 20,000 pattens. In contast, we apply 20,000 pattens fo each of the 9 WR-BIST sessions. The depth of patten memoy used fo ATPG pattens emains 80M. The memoy depth fo each WR-BIST session is educed to times to only 36M because the length of the longest scan chain is only 1,800 in the BIST mode. The emaining memoy depth can be used to apply appoximately 216,000 additional BIST pattens fo 9 WR-BIST sessions. 3.3 H-DFT-2 Achitectue The H-DFT-0 and H-DFT-1 achitectues descibed in the pevious sections depend on a flexible teste memoy configuation among the scan-in and scan-out memoy channels. Howeve, we ealized that not all teste available today has this flexibility and we need to ovecome this poblem by going to the next development phase: H-DFT-2, as depicted in Figue 3.3. Fo the pupose of illustation, we used a 4-to-1 paallel-to-seial convete to convet it to 9 scan-in channels. Notice that it is assumed that the scan shift fequency is 4 times faste than the teste opeating fequency. In Figue 3.3, = 4, the scan shift fequency can be 200MHz and the teste opeating fequency can be 50 MHz. Similaly, the output of X-Compact will have 9 outputs and it will then be conveted to 36 scanout signals though a 1-to-4 Seial-to-Paallel convete to save a total of 75% teste memoies. The scan chain inputs ae connected to the outputs of an Illinois o an Xpande decompession block with n/ inputs and k outputs duing ATPG mode, and to k outputs of a weighted andom patten geneato duing WR-BIST mode. Fo example, with 100 scan-in channels and 100 scan-out channels (i.e., n = 100), 100 scan chains (i.e., k = 100) and = 4, the Illinois o the Xpande decompession block has 25 inputs and 100 outputs. The scan chain outputs ae connected to the inputs of an X-compacto, which compacts the k inputs into n/ outputs. Hence, the X-Compacto block will have 100 inputs and 25 outputs. Each input of the decompession block is connected to the output of a paallel-to-seial convete block with inputs and a single output. Each output of the X-Compacto block is connected to the input of a seial-to-paallel convete with a single input and outputs. Hence, duing ATPG mode, fo evey teste cycle bits ae loaded into each paallel-toseial convete. Since the scan shift fequency is P a alle l-to - seial In 1 In 1 O u t 1 O u t 1 S e ial-to - paallel Illinois o XPAND In 2 Out 2 X - Com pacto P a a llel-to - seial In n / 0 1 0 1 0 1 O u t n/ In n Out n S e ia l-topaallel Figue 3.3. H-DFT-2 achitectue. W eighted Random Geneato W R -BIST M ode times faste than the teste opeating fequency, all these bits will be decompessed to fill the scan chain fo shift cycles befoe the next teste cycle occus. Similaly, duing the scan shift cycles the compessed esponses (X-Compacto outputs) ae collected into the seial-to-paallel convete egiste and at the next teste cycle the contents of the egiste ae loaded onto the teste. Duing WR-BIST mode, none of the scan-in channels ae used because WR-BIST test pattens ae geneated by on-chip hadwae. The esponse to the weighted andom test pattens ae obseved the same way as in ATPG mode. Theefoe, the H-DFT achitectue can apply both ATPG and WR-BIST test pattens without equiing any additional teste memoy ove what is equied fo application of ATPG test pattens with taditional scan (with no H-DFT achitectue) as long as the total numbe of test pattens applied in the WR-BIST mode is less than o equal to - 1 times the numbe of ATPG geneated test pattens and n = k. Fo example, when is 4, we can have 20,000 ATPG-geneated test pattens and 60,000 weighted-andom pattens without equiing any exta teste memoy ove what is equied fo 20,000 ATPG-geneated test pattens on a design with 100 scan chains and taditional scan achitectue. When k > n, then the atio of the numbe of WR-BIST test pattens that can be applied without inceasing the memoy equiement ove taditional scan with n scan chains is equal to: ( 1) length of longest scan chain with H - DFT. length of longest scan chain with taditional scan 1235

Fo example, if n = 100, k = 200 and = 4, 120,000 WR-BIST pattens can be applied in addition to 20,000 ATPG geneated pattens without equiing exta ATE memoy ove what is equied to apply 20,000 test pattens to the same design with 100 taditional scan chains. It is assumed that the length of the longest scan chain is halved. Note that, while this achitectue facilitates application of WR-BIST without equiing any additional patten memoy, it can incease the total test time. Fo the above example, if the longest scan chain has 5,000 flip-flops and scan shift is pefomed at 200MHz, then the amount of time equied to apply ATPG test pattens is 5,000 20,000 5 10-9 = 0.5 seconds, and the amount of time equied to apply 60,000 WR-BIST test pattens is an additional 0.5 3 = 1.5 seconds. Depending on the application, this incease in test time may o may not be acceptable. The exta test time can be significantly educed by inceasing the numbe of scan chains duing WR-BIST mode. Since test pattens ae geneated on-chip, the numbe of scanin channels doesn t incease. The X-Compact technique is used to compact the scan chain outputs so that thee is no equiement fo exta scan-out channels. Refeing to ou pevious example, we can have 100 scan chains duing ATPG mode and 500 scan chains duing WR- BIST mode and use an X-Compacto to compact a 500 bit esponse to a 25-bit esponse. Thus, the additional test time due to WR-BIST pattens is 0.3 seconds instead of 1.5 seconds. 4 Application of the H-DFT-2 achitectue to a micopocesso The H-DFT-2 achitectue has been implemented on a leading edge micopocesso design. The numbe of scan chains is 36 because the tageted stuctual teste contains 36 scan-in channels and 36 scan-out channels. The scan chains can pefom shift opeation at 200 MHz o highe and the stuctual teste can opeate at a fequency of 50 MHz o highe. Hence, efeing to Fig. 3.3, the value of is equal to 4. The decompesso in the H-DFT-2 achitectue has 9 inputs and 36 outputs, and is implemented using the Illinois technique. Each decompesso input is fanned out to 4 scan chains. Since = 4, each paallel-to-seial convete contains 4 flip-flops. The X-Compacto is 1-X-toleant and is designed to have 36 inputs and 9 outputs. Since = 4, each seial-to-paallel convete contains 4 flip-flops. Cuent ATPG tools have the capability of geneating test pattens using Illinois scan. Afte scan chain insetion is done and the numbe of scan chains finalized, we design the X-compacto and inset this cicuit at the outputs of the scan chains. While cuent ATPG tools can t ecognize any exta cicuity at scan chain outputs duing ATPG, we have a flow in place to pefom ATPG faking as if the X-Compacto isn t pesent and then late simulating the X-Compacto to obtain expected X-Compact outputs. We didn t incease the numbe of scan chains duing WR-BIST mode because that would have added exta complexity to the design flow of an aleady complicated micopocesso. The micopocesso is still unde design, and moe data elated will be povided in the futue. 5. Conclusions H-DFT is an effective DFT achitectue that combines advantages of both scan DFT and WR-BIST to enable low-cost but high quality stuctual testing. Applications of H-DFT to industial designs clealy demonstate temendous savings in teste patten memoy equiements and it significantly educes test application time. The H-DFT technique has been implemented in a high-pefomance micopocesso to accommodate the amount of stuck-at and tansition fault test pattens equied to ensue that the taget test coveage goal is eached. The H-DFT achitectue intoduces vey little aea ovehead, has no impact on poduct pefomance and doesn t affect the design flow significantly. Duing the pocess of implementing the H- DFT technique, we ecognized that the numbe of intenal scan chains is somehow limited by the capability of the outing tool. Theefoe, we need to make some tadeoffs between the savings in of test time with a lage numbe of scan chains and outability. We ae cuently investigating techniques to detemine the optimum scan chain configuations to maximize the benefits of ATPG and WR-BIST modes. Futue extensions to the H-DFT achitectue will include integation of techniques fo compessing test pattens applied fom the teste to futhe educe test time and teste memoy equiements. The application of H-DFT achitectue to a multi-coe design is also being investigated. Appendix: A shift egiste stuctue simila to Intel s scanout stuctue can be inseted at the X-Compacto outputs, as shown in Fig. A.1.1. The stuctue basically consists of one o moe shift egistes with the X-Compacto outputs XOR-ed into inputs of some stages of the shift egistes. Simila shift-egiste stuctues have been used fo seveal othe test applications. The advantage of this appoach is that it equies fewe output pins. Howeve, eos fom two o moe diffeent scanout cycles may cancel each othe. This is a vey well known 1236

concept and can be eliminated by a simple extension of the basic X-Compact design technique. The disadvantage of this appoach is that, unlike the basic X- Compacto stuctue, eos poduced by scan chains at a scan cycle may be masked by X s poduced duing a diffeent scan cycle. A simila stuctue is descibed in [Rajski 03]. Out 1 Out 1 Out 2 D Q Out 2 X-Compacto D Q Out n Out m Figue A.1.1. X-Compacto with a shift egiste stuctue simila to Intel scanout stuctue. The X-Compact technique has been in used in seveal Intel poducts. The esults on the distibutions of X s (unknown logic values) in two ASIC designs and analyze the application of X-Compact to these two designs ae shown below. Both designs have 100 scan chains. Fo these designs, we geneated single stuck-at test pattens with high fault coveage and calculated the numbe of scan cycles with no X, the numbe of scan cycles with 1 X, and so on fom the expected esponse. Table 4.3.1. Distibution of Xs in Design1 No. of % of scan-out cycles Xs 0 85.91% 1 12.53% 2 1.422% 3 0.1243% 4 0.0135% >5 0% Distibution of Xs in Design2 with ill-managed X s No. of Xs % of scan-out cycles 0 73.8% 1 22% 2 3.6% 3 0.47% >4 0.055% Fo Design 1, the amount of test esponse data to be obseved on the teste pe scan-out cycle will D Q OUT be on an aveage equal to ( 1.5% 100 + 98.5% 9) = 10. 3 bits on an aveage instead of 100 bits with taditional scan which gives appoximately 9.6 times eduction in test esponse data volume compaed to taditional scan. Similaly, fo Design 2, the amount of test esponse data to be obseved on the teste pe scan-out cycle will be on an aveage equal to ( 4.2% 100 + 95.8% 9) = 12. 8 bits on an aveage instead of 100 bits with taditional scan which gives appoximately 7.8 times eduction in test esponse data volume compaed to taditional scan. Refeences [Eichelbege 77] Eichelbege, E.B., and T.W. Williams, A Logic Design Stuctue fo LSI Testability, Poc. Design Automation Conf., pp. 462-468, 1977. [Eichelbege 91] Eichelbege, E.B., E. Lindbloom, J. Waicukauski and T.W. Williams, Stuctued Logic Testing, Pentice Hall, 1991. [Lin 93] Lin, M. et. al, PSBIST: A Patial- Based Built-In Self-Test Scheme, Poc. Int l Test Conf., pp. 507-516, Oct. 1993. [Wu 02] Wu, D.M. and Lin, M. HVM Design fo Test Stategy, Invited pape of SCI 2002. [Wu 99] Wu, D.M. et al, and Lin, M., High Volume Manufactuing Design fo Test Stategies, Intel Assembly and Test Technology Jounal, Vol. 2, 1999. [Waicukauski 89] Waicukauski, J.A., E. Lindbloom, E.B. Eichelbege and O.P. Folenza, A Method fo Geneating Weighted Random Pattens, IBM Jounal Res. and Dev., Vol. 33, No. 2, pp. 149-161, Mach 1989. [Wu 99b] Wu, D.M., Pavathala, Peveen, Gollakota, Naga, Methods fo Application of Weighted Random Pattens to Patial Designs, US Patent 5968194, Oct 19, 1999 [Kusko 01] Kusko, M., B.J. Robbins, T.J. Kopowski and W.V. Houtt, 99% AC Test Coveage using only LBIST on the 1 GHz IBM S/390, Poc. Intl. Test Conf.,pp. 586-592, 2001. [Hamzaoglu 99] Hamzaoglu, I., and J.H. Patel, Reducing Test Application Time fo Full Embedded Coes, Poc. Intl. Symp. Fault-Toleant 1237

Computing, pp. 260-267, 1999. [Mita 02a] Mita, S., and K.S. Kim, X-Compact: An Efficient Response Compaction Technique fo Test Cost Reduction, Poc. Intl. Test Conf., pp. 311-320, 2002. [Mita 02b] Mita, S., and K.S. Kim, X-Compact: An Efficient Response Compaction Technique, To appea in IEEE Tans. CAD. [Mita 02c] Mita, S., and K.S. Kim, Stimulus Geneation Patent Pending, Intel Copoation, 2002. [Badell 87] Badell, P.H., W.H. McAnney and J. Savi, Built-In Testing fo VLSI: Pseudoandom Techniques, Wiley Intescience, 1987. [Banhat 01] Banhat, C., V. Bunkhost, F. Distle, O. Fanswoth, B. Kelle, and B. Koenemann, OPMISR: The Foundation fo Compessed ATPG Vectos, Poc. Intl. Test Conf., pp. 748-757, 2001. [Das 00] Das, D., and N.A. Touba, Reducing Test Data Volume using Extenal/LBIST Hybid Test Pattens, Poc. Intl. Test Conf., pp. 115-121, 2000. [Khoche 02] Khoche, A., S. Mita, E. Volkeink, and J. Rivoi, Test Vecto Compession using ATE- DFT Synegies, Poc. IEEE VLSI Test Symp., pp. 97-102, 2002. [Koenemann 01] Koenemann, B., C. Banhat, B. Kelle, T. Snethen, O. Fanswoth and D. Wheate, A SmatBIST Vaiant with Guaanteed Encoding, Poc. IEEE Asian Test Symp., pp. 325-330, 2001. [Rajski 02] Rajski, J., et al., Embedded Deteministic Test fo Low Cost Manufactuing Test, Poc. IEEE Intl. Test Conf., 2002. [Rajski 03] Rajski, J., J. Tsyze, C. Wang and S.M. Reddy, Convolutional Compaction of Test Responses, To appea in Poc. Intl. Test Conf., 2003. [Patel UI] 'An Incemental Algoithm fo Test Geneation in Illinois Achitectue Based Designs', Amit R. Andeyy and Janak H. Patel, Cente fo Reliable & High-Pefomance Computing, Univesity of Illinois, Ubana, IL 61801 1238