Analysis of Sequential Circuits

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NOTE: Explanation Refer lass Notes Digital ircuits(15ee23) Analysis of Sequential ircuits by Nagaraj Vannal, Asst.Professor, School of Electronics Engineering,.L.E. Technological University, Hubballi. nagaraj_vannal@bvb.edu

Digital ircuits(15ee23) Lesson Schedule: 1. Registers 2. Registers 3. ounters Analysis of Sequential ircuit 4. Binary Ripple ounters 5. Synchronous Binary counters 6. Ring and ohnson ounters (Planned Hours:1hours) 7. Design of a Synchronous counters 8. Design of a Synchronous Mod-n ounter using clocked 9. Design of a Synchronous Mod-n ounter using clocked D Flip-Flops 1. Design of a Synchronous Mod-n ounter using clocked T and SR Flip- Flops.

Digital ircuits(15ee23) The Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state table More often, think of a register as storing a vector of binary values Frequently used to perform simple data storage and data movement and processing operations

Shift Registers Digital ircuits(15ee23) A Shift Register is a sequential logic device made up of flip-flops that allows parallel or serial loading and serial or parallel outputs as well as shifting bit by bit.

REGISTER- group of flip flops capable of storing data. Digital ircuits(15ee23) SHIFT REGISTER VOABULARY SERIAL DATA TRANSMISSION- transfer of data from one place to another one bit at a time. PARALLEL DATA TRANSMISSION- simultaneous transfer of all bits of a data word from one place to another. SISO- SERIAL IN/SERIAL OUT- type of register that can be loaded with data serially and has only one serial output. SIPO- SERIAL IN/PARALLEL OUT- type of register that can be loaded with data serially and has parallel outputs available. PISO- PARALLEL IN/SERIAL OUT- type of register that can be loaded with parallel data and has only one serial output. PIPO- PARALLEL IN/PARALLEL OUT- type of register that can be loaded with parallel data and has parallel outputs available.

Serial Input D D D D Digital ircuits(15ee23) Serial in Serial out (SISO) 3 2 1 Serial Output SI L L 3 2 1

Serial In Parallel Out(SIPO) Accepts data serially. Outputs of all stages are available simultaneously. Digital ircuits(15ee23) Data input D D D D L 1 2 3

Digital ircuits(15ee23) Parallel In Parallel Out (PIPO) Simultaneous input and output of all data bits. Parallel data inputs D D 1 D 2 D 3 D D D D L 1 2 3 Parallel data outputs

Digital ircuits(15ee23) Parallel In Serial Out (PISO) Bits are entered simultaneously, but output is serial. Data input D D 1 D 2 D 3 SHIFT/LOAD D Serial D D D data 1 2 3 out L SHIFT. + SHIFT'.D 1

Digital ircuits(15ee23) Bidirectional Shift Registers Data can be shifted either left or right, using a control line RIGHT/LEFT (or simply RIGHT) to indicate the direction. RIGHT/LEFT Serial data in D D 1 D 2 D 3 L RIGHT. + RIGHT'. 2

4-bit bidirectional shift register with parallel load. Digital ircuits(15ee23) Universal Shift Register Mode Select S1 S Register Operation Hold 1 Shift right 1 Shift left 1 1 Parallel load

Digital ircuits(15ee23) Shift Register ounters Shift register counter: a shift register with the serial output connected back to the serial input. They are classified as counters because they give a specified sequence of states. Two common types: the ohnson counter and the Ring counter.

Digital ircuits(15ee23) Ring ounters One flip-flop (stage) for each state in the sequence. The output of the last stage is connected to the D input of the first stage. An n-bit ring counter cycles through n states. No decoding gates are required, as there is an output that corresponds to every state the counter is in.

Digital ircuits(15ee23) Example: A 6-bit ring counter. Ring ounters PRE 1 2 3 4 5 D D D D D D LR L lock 1 2 3 4 5 1 1 1 2 1 3 1 4 1 5 1 1 1 1 1 1 1

Digital ircuits(15ee23) ohnson ounters The complement of the output of the last stage is connected back to the D input of the first stage. Also called the twisted-ring counter. Require fewer flip-flops than ring counters but more flipflops than binary counters. An n-bit ohnson counter cycles through 2n states. Require more decoding circuitry than ring counter but less than binary counters.

ohnson ounters Example: A 4-bit ohnson counter. Digital ircuits(15ee23) LR L 1 2 D D D D ' 3 ' lock 1 2 3 1 1 2 1 1 3 1 1 1 4 1 1 1 1 5 1 1 1 6 1 1 7 1 11 1 111 1111 1 111 11

ounters are circuits that cycle through a specified number of states. Two types of counters: Introduction: ounters synchronous (parallel) counters asynchronous (ripple) counters Digital ircuits(15ee23) Ripple counters allow some flip-flop outputs to be used as a source of clock for other flip-flops. Synchronous counters apply the same clock to all flip-flops.

Digital ircuits(15ee23) Asynchronous (Ripple) ounters Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse. Also known as ripple counters, as the input clock pulse ripples through the counter cumulative delay is a drawback. n flip-flops a MOD (modulus) 2 n counter. (Note: A MOD-x counter cycles through x states.) Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider.

Asynchronous (Ripple) ounters Example: 4-bit ripple binary counter (negative-edge triggered). HIGH Digital ircuits(15ee23) 1 2 3 L FF FF1 FF2 FF3 L 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 1 2 3

Asyn. ounters with MOD no. < 2 n States may be skipped resulting in a truncated sequence. Technique: force counter to recycle before going through all of the states in the binary sequence. Example: Given the following circuit, determine the counting sequence (and hence the modulus no.) All, inputs are 1 (HIGH). B A L LR B L LR Digital ircuits(15ee23) L LR

Example (cont d): All, inputs are 1 (HIGH). B A L LR B L LR Digital ircuits(15ee23) Asyn. ounters with MOD no. < 2 n L LR lock NAND Output A B 1 1 2 3 4 5 6 7 8 9 1 11 12 MOD-6 counter produced by clearing (a MOD-8 binary counter) when count of six (11) occurs.

Digital ircuits(15ee23) Asyn. ounters with MOD no. < 2 n Example (cont d): ounting sequence of circuit (in BA order). lock A B NAND Output 1 1 2 3 4 5 6 7 8 9 1 11 12 1 1 1 1 1 1 1 1 Temporary state 111 11 1 1 ounter is a MOD-6 counter. 11 1 11

Digital ircuits(15ee23) Asyn. ounters with MOD no. < 2 n Decade counters (or BD counters) are counters with 1 states (modulus-1) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.). Design an asynchronous decade counter. (A.)' HIGH D B A L LR LR LR LR

Digital ircuits(15ee23) Asyn. ounters with MOD no. < 2 n Asynchronous decade/bd counter (cont d). HIGH D B A (A.)' L LR LR LR LR lock 1 2 1 3 4 5 6 7 8 9 1 1 1 1 1 11 D 1 1 1 1 1 1 1 1 B 1 1 A NAND output

Digital ircuits(15ee23) Asynchronous Down ounters So far we are dealing with up counters. Down counters, on the other hand, count downward from a maximum value to zero, and repeat. Example: A 3-bit binary (MOD-2 3 ) down counter. 1 L ' ' 1 ' 2 3-bit binary up counter 1 L ' ' 1 ' 2 3-bit binary down counter

Example: A 3-bit binary (MOD-8) down counter. 1 Digital ircuits(15ee23) Asynchronous Down ounters 1 111 L ' ' 1 ' 2 1 11 1 11 11 L 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 1 1 2 1 1 1 1

Digital ircuits(15ee23) Asynchronous (Ripple) ounters Propagation delays in an asynchronous (ripple-clocked) binary counter. If the accumulated delay is greater than the clock pulse, some counter states may be misrepresented! L 1 2 3 4 1 2 t PLH (L to ) t PHL (L to ) t PLH ( to 1 ) t PHL (L to ) t PHL ( to 1 ) t PLH ( 1 to 2 )

Digital ircuits(15ee23) Design of a Synchronous Mod-n ounter using clocked Flip-Flops REFER THE LASS NOTES

Digital ircuits(15ee23) Design of a Synchronous Mod-n ounter using clocked T Flip-Flops REFER THE LASS NOTES

Digital ircuits(15ee23) Design of a Synchronous Mod-n ounter using clocked D Flip-Flops REFER THE LASS NOTES

Digital ircuits(15ee23) Design of a Synchronous Mod-n ounter using clocked SR Flip-Flops REFER THE LASS NOTES

Digital ircuits(15ee23) Design of a Synchronous ounter using clocked SR Flip-Flops Sequence = 1 3 4 2 REFER THE LASS NOTES