Successful Trnsfer of V phemt Technology Json Fender 1, Monic C De Bc 1, Jenn Hw Hung 1, Monte Miller 1, Jose Surez 1 Iris Hsieh 2, Y.C. Wng 2 1 Freescle Semiconductor, RF Division, 20 E. Elliot Rd., Tempe, AZ 85284, USA json.fender@freescle.com, 480-413-3521 2 WIN Semiconductors Corp., 69 Technology 7th Rd., Hwy Technology Prk, Kuei Shn Hsing, To Yun Shien, Tiwn 333, irish@winfoundry.com, 886-3-397-5999 ext 1557 Keywords: PHEMT, Trnsfer, Process, Test Abstrct This extended bstrct describes the process tht ws followed nd the results in trnsferring V phemt technology from Freescle Semiconductor to WIN Semiconductors. The process trnsfer project ws divided into four sections: the trnsfer msk, the epitxil substrte, the frontside process, nd the bckside process. To evlute the success of the trnsferred process, DC nd RF chrcteristics were mesured. In ddition, relibility tests were used for the qulifiction. All success criteri were met. BACKGROUND In the erly prt of yer 2000, Freescle Semiconductor (s Motorol Semiconductor Product Sector) developed GAs phemt technology for wireless infrstructure pplictions [1]. Freescle continues to develop nd support power mplifiers for the wireless infrstructure mrket including GAs liner mplifier ICs nd discrete power trnsistors. The high linerity V phemt technology, cpble of 40V drin brekdown, is criticl prt of Freescle RF Division s mplifier product line. The technology ws developed nd optimized in the Freescle internl fb over severl yers. At the end of yer 2008, Freescle closed its GAs fb commensurte with selling its hndset power mplifier business. Since Freescle exited GAs wfer mnufcturing, WIN Semiconductors hs been the foundry prtner for GAs wfer mnufcturing. A power phemt device technology ws not prt of WIN Semiconductors portfolio, nd trnsfer ws necessry to continue the Freescle product line nd future development. The gol of the trnsfer ws to produce drop-in replcement performnce, mtching both RF nd DC chrcteristics to the originl product. TRANSFER METHODOLOGY A joint tem with Freescle nd WIN Semiconductors engineers ws formed t the beginning of the project. The tem ws mde up of product, device, design, test, nd fb engineers so tht ll spects of the technology nd product trnsfer could be thoroughly explored. By including ll disciplines from the beginning, most questions nd risks were identified nd could be ddressed in the development phse. The overll methodology ws to use copy smrt trnsfer. After detiled review of the Freescle process, the tem ws ble to determine wht processes could use relesed mnufcturing processes in the receiving fb. By using existing processes t the foundry, the trnsfer would require less development time, reduce the cost, nd go into mnufcturing esier. A key component through the entire trnsfer process ws documenttion. The trnsfer project followed detiled technology trnsfer pln nd checklist. This included the following key items: schedule, definition of technology nd product specifictions, process flow informtion nd specifictions, risk nlysis/fmea s, control plns, test dt nlysis requirements, relibility testing requirements, nd product level qulifiction. Both Freescle nd WIN Semiconductors shred the responsibility for documenttion items. In ddition, ll experiments were documented, both short flow nd full flow lots included. These results were regulrly communicted with the tem. The sttus of experiments running in the foundry ws trcked closely so tht follow-on ctivities were redy for completed wfers. With consistent communiction, the trnsfer process rn smoothly. The trnsfer process development ws divided into four min sections: the trnsfer msk, the epitxil substrte, the frontside process, nd the bckside process. TRANSFER MASK The first order of technology trnsfer is to define test vehicle tht both prties cn use to guge the progress of the trnsfer. A pizz msk set ws creted which contined designted test vehicles, such s product die, relibility devices, PCM test structures nd RF-probe-ble devices designed from both compnies. Involved in this, preliminry design rules were estblished bsed on the foundry process. Probe crds nd test codes were lso exchnged nd reference wfers were tested by both prties to clibrte the CS MANTECH Conference, My 16th-19th, 2011, Plm Springs, Cliforni, USA 285
testers. This foundtion set the stge for the engineering lots to strt. MIM cpcitor. The finl protect nitride were dopted for relibility concern. EPITAXIAL SUBSTRATE One of the criticl components of the technology is the epitxil (epi) mteril. The epi structure ws developed nd customized for the ppliction [1]. As prt of the trnsfer, the structure ws mnufctured by two vendors nd evluted. Wfers from the two vendors nd from Freescle epi inventory were included in severl of the engineering lots. DC, smll signl nd lrge signl RF chrcteristics were compred. One of the criticl prmeters, the crrier doping, ws clibrted to obtin I-V chrcteristics mtched to the historicl dt bse, such s Imx, Idss, Vth, onresistnce nd drin brekdown voltge, etc. Initil dt indicted tht the on-resistnce ws off by lmost 2x. After thorough discussion with the epi vendor, revised growth recipe ws implemented nd brought this prmeter to within the control limits. 0.5 um FRONTSIDE PROCESS The device construction used typicl mnufcturing methods in the Freescle fb consistent with the equipment set vilble. In most cses, the process modules were similr to the foundry cpbilities nd foundry processes were used directly. This ws not the cse for ll modules, prticulrly the gte module. The originl gte process utilized n etched gte chnnel rchitecture while the stndrd foundry gte ws formed by evportion nd liftoff. In the course of the evlution, single lyer liftoff ws proved to be indequte, nd double lyer liftoff process ws implemented. The lyout of the lift-off gte ws lso chnged becuse the stndrd metl 1 lyer ws not combined with gte metl s in the originl process. Fig.1 compres the cross sections of gte electrodes from both prties. The difference is obvious nd drstic. The rest of the process flow ws evluted throughout the project s electricl performnce ws mesured. Short flow test wfers were used to evlute individul modules. Once process ws proven cpble, full-flow, device-redy wfers were run. The flow ws frozen fter ll electricl performnce trgets were chieved. The first lyer, ohmic contcts, ws formed by electron bem evportion for source/drin contcts. Device isoltion ws done by ion implnttion followed by the selective first recess etch. The gte ws done by bi-lyer process for reching the smll undercut with selective recess etch solution. The gte metls, Ti/Pt/Au, ws deposited for D- mode phemt. Fig. 1 (top) shows the SEM cross-section of single-gte device. After the gte metlliztion, the phemt ws fully pssivted by SiN, nd followed by TN resistor with sheet resistnce 50 ohms/squre. Two interconnection metl levels nd 200 nm SiN were used for 300 pf/mm2 0.5 um Figure 1: SEM cross sections of single gte device. Top imge is foundry process nd bottom imge is originl process BACKSIDE PROCESS There re two pckging lines utilized for this technology, therefore two different bckside process flows were required to be trnsferred. The ir-cvity products utilize AuSn die ttch using very thin die thickness. The plstic products utilize soft solder die ttch with 3 mil die thickness. Process development ws required t the foundry for both bckmetl schemes. For the AuSn die ttch, die thickness hd to be evluted long with bckmetl Au thickness to minimize wrpge fter demount while mintining sufficient mteril for die ttch. In the finl process, the substrte is thinned down to 50 µm nd throughvi holes re formed by ICP etch. A 6 µm thick Au film is plted s the bckside metlliztion. For the soft solder die ttch, the foundry hd to develop new processes for the metl lyers required, s referenced [2]. Once the process ws developed, mechnicl smple die were ssembled in pckges for evlution. The AuSn die ttch qulity ws 286 CS MANTECH Conference, My 16th-19th, 2011, Plm Springs, Cliforni, USA
mesured with SEM cross sections nd CSAM. A typicl CSAM imge of good die ttch is shown in Fig. 2. EVALUATION AND RESULTS Figure 2: CSAM imge of die fter AuSn die ttch The soft solder die ttch qulity ws mesured with CSAM nd cross sections looking for solder ttck of the Au bckmetl. An opticl cross section imge of good die ttch showing both the source vi nd bckstreet edge is shown in Fig. 3. Polishing debris The first spect of mtching electricl performnce ws to correlte the test methods. PCM structures, test hrdwre, nd test librry lgorithms were copied exctly into WIN s test frmework. Freescle nd WIN engineering wfers were mesured using both test frmeworks for comprison. The optiml solution ws chieved by combining WIN test structures nd test hrdwre with Freescle librry lgorithms. Once the PCM test cpbility ws chieved, engineering lots were tested both on-wfer nd with pckged product to compre results. The next step ws to introduce on-wfer product testing (unit probe). A similr pproch ws utilized combining Freescle test plns with WIN unit probe frmework, nd chieved good correltion to product historicl performnce. The finl process solution provided mtching PCM, unit probe, nd RF performnce. The DC nd RF chrcteristics comprison is shown in Tble 1. Figure 4 compres the onwfer S-prmeters of single unit cell t V nd %Idss bis over frequency rnge of 800MHz-15.5GHz. Pckged W discrete trnsistors were mesured in fixture using fixed mtching conditions t 3.55GHz under the sme W-CDMA modultion conditions. Figure 5 compres the gin nd W-CDMA ACPR versus output power for Vds=V nd Ids=140mA for the pckged W discrete. The comprison shows tht the trnsferred WIN process mintins the expected db gin level nd >30dBm RF power out cpbility t n ACPR spec of -40dBc. The bck-off ACPR chrcteristic for the trnsferred process from -40dBc to -44dBc is within n cceptble 1.5 to 2dB level. An utomtic lod pull system ws utilized to compre RF CW performnce t drop-in lod nd source mtching conditions which mtch the W-CDMA product test fixture. RF CW gin nd drin efficiency t V nd 180mA re compred in Figure 6. The WIN process mintins the >db gin level, is within 0.5dB for P1dB, nd shows higher drin efficiency in comprison to the bseline process from Freescle. Figure 3: Cross sections of the through vi (top) nd bckside street (bottom) fter soft solder die ttch CS MANTECH Conference, My 16th-19th, 2011, Plm Springs, Cliforni, USA 287
Process Control Monitors (PCM) On Wfer Product Test (Unit Probe) Product Finl Test Prmeter FSL WIN Vth (V) (0.1mA/mm ) Bvgso (V) 0.83 0.92 27.81 41.02 24.42 35.03 21.27 25.8 Ron (Ω) 2.39 2.8 Idsoff (µa) 0.81 2.13 Idelity 1.29 1.54 Brrier Height Ids (ma) (St Current) 0.85 0.84 202.9 218.21 Prmeter FSL WIN Vth (V) (µa/mm) 0.86 1.02 25.2 22.07 Ron (Ω) 0.14 0.19 Idsoff (µa) 1.83 2.05 Igss (µa) 0.15 0.19 Idso (µa ) 43.82 23.59 Prmeter FSL WIN Vgs (V) 0.86 0.98 Vds (V) Ids (ma) 307.29 309.58 Gin (db).94.45 Eff (%) 27, 39.18 ACPR (dbc) 44.62 43.59 IRL (db) 11.02 11.41 Idsq (ma) 140.41 139.96 Igs (µa) 77.83 66.97 Tble 1: DC nd RF chrcteristics comprison of bseline process from Freescle nd trnsferred process t WIN Figure 4: Unit cell S-Prmeter comprison 800MHz-15.5GHz of bseline process from Freescle nd trnsferred process t WIN Gin (db) 11 9 8 7 WIN FSL GAIN & ACPR Comprison 6-55 15 20 25 30 35 RF Power Out (dbm) Figure 5: Product linerity comprison of bseline process from Freescle nd trnsferred process t WIN Gin (db) CW GAIN & DRAIN EFFICIENCY 15 0 14 90 13 80 70 11 60 50 9 FSL 40 8 WIN 30 7 20 6 5 0 15 20 25 30 35 40 Pout (dbm) Figure 6: Product CW gin nd drin efficiency comprison of bseline process from Freescle nd trnsferred process t WIN RELIABILITY We conducted chip-level temperture step stress (TSS) nd 3-temperture stress testing on the prts fbricted t WIN. The performnce ws verified to be equivlent to the originl product. Fig. 7 shows the cumultive filure distribution from the TSS tests. MTTF is clculted to be 2.1e6 hrs nd ctivtion energy is 1.49 ev. These numbers -25-30 -35-40 -45-50 ACPR (dbc) Drin Eff (%) 288 CS MANTECH Conference, My 16th-19th, 2011, Plm Springs, Cliforni, USA
re comprble to the vlues obtined previously on the prts mnufctured by Freescle [3]. nd receiving tem members. Consistent nd regulr documenttion nd communiction between working engineering tems is prticulrly effective. Prllel efforts to evlute multiple spects of the trnsfer re beneficil when the time comes to combine the entire process for the finl evlution product. All performnce nd mnufcturing criteri were met nd new product development utilizing the trnsferred process is now under wy. ACKNOWLEDGEMENTS The uthors would like to thnk the Freescle engineering tems from the following orgniztions: RF Division, RASG Technology Group, Technology Solutions Orgniztion, Qulity Tem (Crig Gw, Tom Arnold, Relibility Assessment Lb), Physicl Anlysis Lb. We lso thnk the WIN Semiconductors engineering tem. Figure 7: Log norml cumultive filure distribution t TCHANNEL = 150 C is plotted for devices tht were temperture step stressed t bis of VDS = volts nd IDS = 70 ma/mm. (Courtesy of C. Gw) A preliminry product level extrinsic relibility ws lso crried out to get n erly check on the product relibility with the chips ssembled in production pckge. The tests included: THB, HTOL, TC nd ESD (HBM, MM, & CDM) per Jedec JESD22 stndrds. Prts pss 00 hours of THB nd HTOL, 00 cycles of TC, nd mtch originl product ESD clsses. Even though the process ws still being optimized when tested, the preliminry results demonstrte comprble relibility. Product qulifiction on prts, from qulifiction lots with frozen epi design nd process nd ssembled ccording to the production flow, hs been strted into full extrinsic relibility testing. The qulifiction pln includes: HTOL, HTRB, HTGB, DCIOL, MSL3, TC, THB, ESD (HBM, MM, & CDM), nd mnufcturing mechnicl indices. Tests hve not been completed t the time of this writing. CONCLUSIONS A successful trnsfer ws chieved by Freescle nd WIN Semiconductors. The copy smrt methodology ws utilized, which combined the strengths from the originl fb with the strengths from the foundry. This significntly reduced the development time nd reduced risk in introducing potentil mnufcturing nd relibility issues. Technology trnsfers re complex nd difficult. They cn be mde esier with combined efforts from both the trnsferring REFERENCES [1] W. Petmn, O. Hrtin, B. Knppenberger, M. Miller, nd R. Hooper, Power Amplifiers for 3.5 GHz W-CDMA Applictions, 2000 IEEE GAs IC Symposium, Settle, WA. [2] J. Fender, T. Dly, Development of Bckside Process For Use With Solder Pste Die Attch, 2006 GAs MANTECH Technicl Digest, pp. 209-211, April 2006. [3] C. Gw, T. Arnold & K. Moore, Intrinsic Relibility of volt Field Plte phemt, Microelectronics Relibility 48 (2008) p. 974-984. ACRONYMS phemt: Pseudomorphic High Electron Mobility Trnsistor FMEA: Filure mode effects nlysis PCM: Process control monitor ICP: Inductively coupled plsm SEM: Scnning electron microscope CSAM: C-Mode Scnning Acoustic Microscopy WCDMA: Widebnd code division multiple ccess ACPR: Adjcent chnnel power rtio CW: Continuous wve P1dB: One db compression point MTTF: Men time to filure THB: Temperture humidity bis HTOL: High temperture operting life TC: Temperture cycles ESD: Electrosttic dischrge HBM: Humn body model MM: Mchine model CDM: Chrge distribution model HTRB: High temperture reverse bis HTGB: High temperture gte bis DCIOL: DC intermitting opertion life MSL3: Moisture sensitivity level 3 CS MANTECH Conference, My 16th-19th, 2011, Plm Springs, Cliforni, USA 289