HCF40193B PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK WITH RESET) BINARY TYPE

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Transcription:

PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK WITH RESET) BINARY TYPE INDIVIDUAL CLOCK LINES FOR COUNTING UP OR COUNTING DOWN SYNCHRONOUS HIGH-SPEED CARRY AND BORROW PROPAGATION DELAYS FOR CASCADING ASYNCHRONOUS RESET AND PRESET CAPABILITY MEDIUM-SPEED OPERATION - f CL = 8MHz (typ.) AT 10 V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I I = 100nA (MAX) AT V DD = 18V T A = 25 C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF40193B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40193B Presettable Binary Up/Down Counter coists of 4 synchronously clocked, GATED "D" type flip-flops connected as a counter. The inputs coist of four individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY DIP ORDER CODES SOP PACKAGE TUBE T & R DIP HCF40193BEY SOP HCF40193BM1 HCF40193M013TR and BORROW outputs for multiple-stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET ENABLE control is low. The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down one count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high. The CARRY and BORROW signals are high when the counter counts up or down. The CARRY signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW signal goes low PIN CONNECTION September 2002 1/12

one-half clock cycle after the counter reaches its minimum count in the count-down mode. The cascading of multiple packages is easily accomplished without the need for additional external circuitry by tying the BORROW and CARRY outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the following package. IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 3, 2, 6, 7 Q1 to Q4 Flip-Flop Outputs 4 CLOCK DOWN Clock Down Input 5 CLOCK UP Clock Up Input 11 PRESET ENABLE Preset Enable Input 12 CARRY Count Up (Carry) 13 BORROW Count Down (Borrow) 14 RESET Reset Input 15, 1, 10, 9 J1 to J4 Data Input 8 V SS Negative Supply Voltage 16 V DD Positive Supply Voltage FUNCTIONAL DIAGRAM 2/12

LOGIC DIAGRAM TRUTH TABLE CLOCK UP CLOCK DOWN PRESET ENABLE RESET ACTION (X) : Don t Care H H L COUNT UP H H L NO COUNT H H L COUNT DOWN H H L NO COUNT X X L L PRESET X X X H RESET 3/12

TIMING DIAGRAM INTERNAL LOGIG OF FLIP-FLOP 4/12

ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V DD Supply Voltage -0.5 to +22 V V I DC Input Voltage -0.5 to V DD + 0.5 V I I DC Input Current ± 10 ma P D Power Dissipation per Package 200 mw Power Dissipation per Output Traistor 100 mw T op Operating Temperature -55 to +125 C T stg Storage Temperature -65 to +150 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditio is not implied. All voltage values are referred to V SS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit V DD Supply Voltage 3 to 20 V V I Input Voltage 0 to V DD V T op Operating Temperature -55 to 125 C 5/12

DC SPECIFICATIONS Test Condition Value Symbol Parameter V I (V) V O (V) I O (µa) V DD (V) T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max. Unit I L Quiescent Current 0/5 5 0.04 5 150 150 0/10 10 0.04 10 300 300 0/15 15 0.04 20 600 600 0/20 20 0.08 100 3000 3000 V OH High Level Output 0/5 <1 5 4.95 4.95 4.95 Voltage 0/10 <1 10 9.95 9.95 9.95 0/15 <1 15 14.95 14.95 14.95 V OL V IH V IL I OH I OL Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current 5/0 <1 5 0.05 0.05 0.05 10/0 <1 10 0.05 0.05 0.05 15/0 <1 15 0.05 0.05 0.05 0.5/4.5 <1 5 3.5 3.5 3.5 1/9 <1 10 7 7 7 1.5/13.5 <1 15 11 11 11 4.5/0.5 <1 5 1.5 1.5 1.5 9/1 <1 10 3 3 3 13.5/1.5 <1 15 4 4 4 0/5 2.5 <1 5-1.36-3.2-1.1-1.1 0/5 4.6 <1 5-0.44-1 -0.36-0.36 0/10 9.5 <1 10-1.1-2.6-0.9-0.9 0/15 13.5 <1 15-3.0-6.8-2.4-2.4 0/5 0.4 <1 5 0.44 1 0.36 0.36 0/10 0.5 <1 10 1.1 2.6 0.9 0.9 0/15 1.5 <1 15 3.0 6.8 2.4 2.4 I I Input Leakage 0/18 Any Input 18 Current ±10-5 ±0.1 ±1 ±1 µa C I Input Capacitance Any Input 5 7.5 pf The Noise Margin for both "1" and "0" level is: 1V min. with V DD =5V, 2V min. with V DD =10V, 2.5V min. with V DD =15V µa V V V V ma ma 6/12

DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25 C, C L = 50pF, R L = 200KΩ, t r = t f = 20 ) Symbol Parameter Test Condition Value (*) Unit V DD (V) Min. Typ. Max. t PLH t PHL Propagation Delay Time 5 250 500 Clock Up or Clock Down to 10 120 240 Q Reset to Q 15 90 180 PE to Q 5 200 400 10 100 200 15 70 140 Clock Up to Carry 5 160 320 Clock Down to Borrow 10 80 160 15 60 120 Reset or PR to Borrow or 5 300 600 Carry 10 150 300 15 110 220 t THL t TLH Traition Time 5 100 200 10 50 100 15 40 80 t rem* Removal Time 5 80 40 Reset or PE 10 40 20 15 30 15 t W Clock Input Pulse Width 5 480 240 Reset 10 300 150 15 260 130 PE 5 120 240 10 85 170 15 70 140 Clock 5 90 180 10 45 90 15 30 60 t r t f f CL Clock Input Rise or Fall Time Maximum Clock Input Frequency 5 15 10 15 15 5 5 2 4 10 5 8 15 5.5 11 (*) The time required for Reset or Preset Enable control to be removed before clocking (see timing diagram). µs MHz 7/12

TEST CIRCUIT C L = 50pF or equivalent (includes jig and probe capacitance) R L = 200KΩ R T = Z OUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1mhz; 50% duty cycle) 8/12

WAVEFORM 2 : MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1mhz; 50% duty cycle) TYPICAL APPLICATION: CASCADED COUNTER PACKAGES 9/12

Plastic DIP-16 (0.25) MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 P001C 10/12

SO-16 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.62 0.024 S 8 (max.) PO13H 11/12

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respoibility for the coequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licee is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificatio mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 12/12