DesignCon 2013 Practical Receiver Equalization Tradeoffs Applicable to Next- Generation 28 Gb/s Links with 20 35 db Loss Channels Edward Frlan, Semtech Corp. (EFrlan@semtech.com) Francois Tremblay, Semtech Corp. (FTremblay@semtech.com)
Abstract Although the OIF CEI-28G-MR (presently in Draft status) and CEI-25G-LR Implementation Agreements (IA s) define the required channel characteristics and link transmitter parameters for several applications of differing reaches, implementation of receiver equalization is not mandated by the IA's and is left to the discretion of the IC or system implementer. Typical 10dB VSR chip-to-module channels require only a simple receiver based CTLE function, however longer reach CEI-28G-MR and CEI-25G-LR types of channels require a combination of CTLE and multi-tap DFE equalization. This paper will investigate the 28G-MR and 25G-LR channels in detail and provide a critical analysis of the required tradeoffs between the two most common types of receiver equalization and their impact to overall performance in the presence of typical system crosstalk and noise impairments. The analysis keeps in mind the goal of maximizing receiver efficiency (ie. pj/bit figure-of-merit), which will become a critical discussion point for the next generation of higher data rate interfaces. Authors Biography Ed Frlan is a Senior System Architect within the Gennum Products Group of Semtech Corp. He joined Gennum from a Hardware Architect position within the Metro Ethernet Networks division of Ciena where he was responsible for the system architecture and synchronization aspects of various line cards (including Carrier Ethernet, SONET, OTN and Broadcast Video). Ed is presently chair of the OIF Physical and Link Layer Interoperability working group and holds a Ph.D. degree in Electrical Engineering from Carleton University. Francois Tremblay is Vice President of Design Engineering for Semtech Canada Corporation responsible for the development of 8-25Gbps module retimer and backplane products. Prior to Semtech, Francois held positions from manager to VP at various semiconductor companies such as Nortel, Cadence, Catena Networks, Ciena and LTRIM technology. His expertise in communications ranges from Discrete Multitones modulation on twisted pair to QAM on cable modem to 28Gbps for module and backplane applications. Francois holds a BSc degree in Electrical Engineering from the University of Ottawa.
1.0 Introduction Today s 100G based high capacity transport and router gear has generally standardized on 10 14 Gb/s intra-system electrical interfaces. Increasing throughput in the network core will demand that next-generation systems support higher density optical modules, examples of which include CFP2, CFP4 and QSFP28 varieties. These are to be largely based on 25 28 Gb/s multi-lane interfaces and will interface to present 10G based ICs via a 10:4 gearbox function over relatively short 10-dB loss links. With time the various line card switch and mapper ICs will absorb the external gearbox function and the higher-speed 25 28 Gb/s interfaces will begin to migrate towards the line card backplane. As this occurs longer reach interfaces such as CEI-28G-MR and CEI-25G-LR will start to be implemented in significant volumes. This paper provides an introduction to the two relevant Implementation Agreements (IA s) which will become prevalent for higher loss links within a line card (CEI-28G- MR, or simply MR ) and between line cards (CEI-25G-LR, or LR ) using various backplane architectures. The applications addressed by each of the relevant IA s will be reviewed and a comparison of their key performance parameters will be provided in section 2. Consequently a discussion is provided on how the OIF channel characteristics and transmitter specified parameters map into possible receiver based approaches combining CTLE (Continuous Time Linear Equalizer) and DFE (Decision Feedback Equalizer) blocks. Two important use cases are studied in significant detail in section 3. and 4. One case is that of a typical single channel NRZ (Non-Return to Zero) system and the other is that of a multi-channel NRZ system where the channel refers to a Tx/Rx pair. For each use case both medium reach (MR) and long reach (LR) links are investigated. MR in this paper refers to OIF CEI-28G-MR chip-to-chip channels having up to 20dB of loss through one connector and LR refers to OIF CEI-25G-LR backplane channels having up to 25 db of loss through two connectors within the OIF definition, but LR will be more broadly used to address channels having greater than 30 db of loss in this paper. Also, the ideal trade-off between CTLE and DFE equalization for each of the use cases will be discussed in terms of commonly used parameters for those functions, For CTLE the DC-gain and pole and zero locations are considered and for DFE the number of taps and the adaptation algorithm are considered. It will be shown that on these typical higher loss MR and LR links that CTLE equalization is able to handle more of the equalization workload in certain cases leading to a simplification of the DFE block's complexity and a subsequent reduction in its power consumption with an increase in receiver overall pj/bit efficiency [1][2].
2.0 OIF CEI-28G-MR and CEI-25G-LR Background Information The OIF IA s target two different applications for MR and LR, but each has similar characteristics and requirements. Fig. 1: CEI-28G-MR Reference Model Figure 1 depicts a typical MR application with up to 20-dB of channel loss between the host and mezzanine ICs as defined between the two system test points. The 20 db of channel loss includes up to one high-speed connector, differential PCB traces and vias and AC coupling capacitors [3]. Fig. 2: CEI-25G-LR Reference Model Figure 2 shows a longer reach 25-dB nominal case for NRZ 25.78 Gb/s signals targeting backplane applications. The channel loss in this case includes up to two high-speed connectors, traces and vias summing 25 db of total loss [4]. The case investigated for this paper is actually for an LR channel operating at 28.0 Gb/s.
The key MR and LR interface parameters are compared in Table 1 below. Value System CEI-28G-SR CEI-28G-MR CEI-25G-LR BER Target < 1x10-15 < 1x10-15 < 1x10-15 Remarks Channel Maximum Channel Loss 15 db 20 db 25 db (30dB extended to 28 Gb/s rate) Maximum IL Deviation 0.5 db,rms 0.5 db,rms 0.5 db,rms Maximum ICN 5.7mV,rms TBD 0.9mV,rms Transmitter Data Rate (Gb/s) 19.9-28.05 19.9-28.05 19.9-25.8 Gb/s Modulation Format NRZ NRZ NRZ Differential Voltage Swing 800-1200mVpp 800-1200mVpp 800-1200mVpp Min. Rise/Fall Time (20% - 80%) 8 ps 8 ps 8 ps Total Jitter < 0.28 UIpp < 0.28 UIpp < 0.28 UIpp FIR Equalization Receiver Jitter Tolerance CDR Untracked Jitter Tolerance 3-tap (1 pre-, 1 post, 1 main) > 0.28UIpp Tx jitter + 5UIpp sinusoidal jiter + 0.05 Uipp HF sinusoidal jitter + channel effects 3-tap (1 pre-, 1 post, 1 main) > 0.28UIpp Tx jitter + 5UIpp sinusoidal jiter + 0.05 Uipp HF sinusoidal jitter + channel effects 3-tap (1 pre-, 1 post, 1 main) > 0.28UIpp Tx jitter + 5UIpp sinusoidal jiter + 0.05 Uipp HF sinusoidal jitter + channel effects >0.7UIpp,typ >0.7UIpp,typ >0.7UIpp,typ Equalization vendor specific vendor specific vendor specific Typical Equalization Required by Channel 0-3dB CTLE + 3to5-tap DFE 0-5dB CTLE + 3to5-tap DFE 0-6dB CTLE + 5- tap DFE Receiver Sensitivity < 50mVpp,diff < 50mVpp,diff < 50mVpp,diff Table 1: OIF CEI-28G-MR and CEI-25G-LR Key Parameters chip ball-to-ball for channel at max allowable IL with 1 UI tap spacing untracked jitter tolerance is not specified by OIF Receiver sensitivity is not a specified OIF parameter - quoted values are implied The SR (Short Reach) and LR IA s are approved OIF Clauses whereas the MR IA is presently in draft status and expected to be approved in 2013. The MR IA is seen as an implementation bridging the maximum SR and LR informative channel losses. The upper data rate of 25.8 Gb/s for LR was initially established to address the IEEE 100GBASE 4x 25.78 Gb/s applications. The LR channel investigated for this paper is based upon an extension of the OIF channel s maximum insertion loss curve up to 28.0 Gb/s in order to address future backplane links at that data rate such as the next fibre-channel speed node of 28.05 Gb/s. The BER targets for the various links are all specified as less than 10-15 and this link performance target is used for the cases investigated in this paper. It should be noted
however that in practice next-generation backplane systems will be required to meet BER performance exceeding 10-17. All of the FIR (Finite Impulse Response) based transmitters in this paper are assumed to have 3 taps (first pre, main, and first post-cursors).
3.0 Investigation of a CEI-28G-MR high loss channel The high-loss MR channel used for this investigation was based upon a set of Nelco 4000-13 EP SI PCB s (Printed Circuit Boards). These PCBs were fabricated with QSFP28 high-speed connectors, for investigation of channels exceeding the CEI-28G- VSR maximum informative channel loss of 10 db. A suitable Nelco PCB trace was cascaded with the original system in order to provide the additional loss necessary to generate a typical expected worst-case MR channel loss profile as shown in Figure 3. Fig. 3: Typical MR Maximum Channel Overall Loss Figure 3 shows the overall MR channel loss response from transmitter die to receiver die termination which indicates 23.5 db of loss at the 14.0 GHz Nyquist frequency of interest for this study. Fig. 4: MR High Loss Channel Loss Contributors The overall breakdown of the loss contributors for the complete channel are depicted in Figure 4. The physical reach for this specific Nelco 4000-13 based PCB implementation is nearly 18 and well suited to addressing typical line card applications. Although CEI- 28G-MR mandates the channel loss characteristics from the Tx Test Point to the Rx Test
Point the simulations and results presented in this paper include the additional parasitic effects of the high-speed packages on either end of the link in order to model the complete channel. 3.1 CEI-28G-MR baseline channel performance The overall system pulse response of the channel of Figure 1, with a transmitter having an output swing of 1 Vpp demonstrates that there is effectively one significant pre-cursor and the post-cursor response has a long tail extending out to greater than 14 UI. The bump evident in the post-cursor response is due to reflections at the QSFP28 connector. Fig. 5: Overall MR Channel Pulse Response Several options are available to the system designer to successfully equalize such a high loss MR channel. One option includes a transmitter based 3-tap FIR filter which is presently mandated by the CEI-28G-MR Implementation Agreement. In order to enable a link with improved power efficiency this paper considers the transmit FIR function is disabled. In that case all of the link equalization is carried out within the receiver using an analog based Continuous Time Linear Equalizer (CTLE) function and a multi-tap Decision Feedback Equalizer (DFE) employing an LMS optimization algorithm. Disabling the transmitter FIR also avoids the inevitable reduction in transmitter output swing. Assuming that a CTLE function having peaking of 16 db at Nyquist frequency is implemented in the receiver, the resulting pulse present at the input to the receiver DFE function shown in Figure 6, illustrates that the main cursor level has been boosted and that the pulse width has been narrowed with the first pre-cursor amplitude decreased and
the post-cursor tail significantly shortened. In effect the number of DFE taps required due to the significant amount of CTLE gain peaking is reduced and it can be shown that a 5- tap DFE will be effective in removing most of the remaining post-cursors. Fig. 6: MR Channel plus 16-dB Rx CTLE Pulse Response Observing the effect of the CTLE in the frequency domain shows that the system bandwidth has been significantly improved and that the remaining burden on the DFE block is significantly reduced compared to a solution that would have more moderate CTLE gain peaking values. Fig. 7: Overall MR Channel Pulse Response
In terms of measuring and simulating system responses the transmitter noise properties were tuned to nearly match the worst-case OIF informative parameters. For example transmitter jitter was tuned to nearly 0.28 UIpp of total jitter, approximately half due to random jitter and the remaining due to deterministic and DCD contributions. Fig. 8: Transmitter Output Data Eye at Tx Test Point BER = 1E-15 eye contour Fig. 9: Receive Slicer Data Eye with 16-dB CTLE and 5-tap DFE total equalization for a PRBS31 data pattern
Simulating this case assuming that the 16-dB CTLE block along with a 5-tap DFE will be sufficient yields a BER 1E-15 eye into the receiver slicer circuit having a height of 132mVppd and a width of 0.35 UIpp which is sufficient for a typical 28 Gb/s CMOS receiver. Eye diagram details are shown in Figure 9 including the timing and voltage bathtubs. The eye contour mappings are made up of three cases representing eyes having BER of 1E-3, 1E-7, and 1E-15 from the largest eye to the smallest. The solution space for this specific MR channel was carried out assuming that there was no transmitter based equalization and that a CTLE with up to 20 db of gain peaking and a DFE with up to 11 taps was available at the receiver. The simulations were carried out for the same transmitter signal swing and noise parameters utilized for the above example but were all normalized to a PRBS15 data pattern instead of the PRBS31 case for the results presented in Figure 9. Taking the case of a system based upon a 16-dB CTLE stage it is confirmed that implementing a DFE with more than 5 taps does not provide any significant additional eye opening as was confirmed by studying the system pulse response. Clearly, as long as one is able to adequately control other system effects such as neighboring channel crosstalk noise as well as noise from the receiver itself then this equalization approach can be very useful in improving the overall link power efficiency. 350 Slicer Vertical Eye (mvppd) 300 250 200 150 100 50 0 0 2 4 6 8 10 12 No. of DFE Taps 0-dB CTLE 4-dB CTLE 8-dB CTLE 12-dB CTLE 16-dB CTLE 20-dB CTLE Fig. 10: Receive Slicer Vertical Eye Opening vs Number of DFE Taps for a PRBS 15 Data Pattern
3.2 CEI-28G-MR channel performance in the presence of system crosstalk The MR crosstalk case investigated for this paper was based upon a system consisting of four bi-directional lanes which is capable of being addressed by the QSFP28 Multi- Source Agreement (MSA) connector, among others. Measurements were conducted on mated compliance boards having controlled insertion loss in order to quantify the effects of connector NEXT and FEXT crosstalk contributors. These measurements were used to calculate the overall Multi-Disturber Near-End Crosstalk (MDNEXT) and Multi-Disturber Far-End Crosstalk (MDFEXT) characteristics as well as the Integrated Crosstalk Noise (ICN) parameter [5]. The individual and total power summed NEXT and FEXT responses shown below were obtained for the mated QSFP28 PCBs which exhibited a measured insertion loss of 7.61 db at Nyquist rate. It is evident comparing the NEXT and FEXT contributors onto the victim channel that far-end crosstalk is of significantly greater concern in this particular system than near-end crosstalk. Fig. 11: Compliance Board FEXT Contributors
Fig. 12: Compliance Board NEXT Contributors The total of all crosstalk contributors is shown in Figure 13 below. Over nearly the entire frequency range the overall coupling is dominated by FEXT contributors. Integrating the total power sum crosstalk in order to calculate the ICN parameter for this particular system yields a value of 2.5 mv. BER = 1E-15 eye contour Fig. 13: Total Compliance Board Crosstalk
In order to correctly model the effects of the crosstalk noise and properly account for the magnitude of the coupling in the MR system it was required that the crosstalk coupling to the victim channel be correctly modeled. Two specific cases were investigated for the crosstalk, one based upon the total crosstalk levels shown in Figure 13 and the other was based on that same curve but having 10 db higher amplitude. 250 Slicer Vertical Eye (mvppd) 200 150 100 50 0 0 5 10 15 16-dB CTLE - no crosstalk 16-dB CTLE including nominal crosstalk 16-dB CTLE including crosstalk increased by 10 db No. of DFE Taps Fig. 14: Total Compliance Board Crosstalk It can be seen from Figure 14 that although the CTLE gain block has the property of amplifying noise it can be seen that for this specific system, with measured crosstalk, eye closure is only on the order of several millivolts for the nominal case. However, the +10dB crosstalk curve shows that crosstalk can very quickly be significantly amplified and in that case must be correctly budgeted in order to ensure that the system robustness and BER target is still met with sufficient margin.
4.0 Investigation of a CEI-25G-LR high loss channel The high-loss LR channel used for this investigation was based upon connecting a set of VSR+ channel boards back-to-back. The loss profile in that case is shown below and indicates that overall channel loss from the transmitter to the receiver die is approximately 31.4 db. Fig. 15: Typical LR Maximum Channel Overall Loss The breakdown of the LR channel loss contributors demonstrates that for this specific case of a Nelco based backplane system up to approximately 20 of stripline trace should be able to be accommodated. Fig. 16: LR High Loss Channel Loss Contributors
4.1 CEI-28G-LR baseline channel performance The pulse response of the LR system shows a similar post-cursor tail to that obtained for the MR system. However, it can be noted that the pre-cursor is now significantly larger and must be addressed in order to provide robust equalization for such a system. Fig. 17: Overall LR Channel Pulse Response Figure 18 compares system pulse responses at the receiver s DFE input for two cases, one having 12 db of CTLE peaking and with no transmitter de-emphasis, and the other with an identical CTLE gain setting but with 5 db of pre-cursor de-emphasis. Significant improvement in overall pulse response is shown, but with the inevitable drop in pulse amplitude.
Fig. 18: Comparing LR System Pulse Response with and without transmit deemphasis with a 12-dB CTLE As for the MR case a solution set of possible equalizations was swept out as a function of CTLE gain settings and number of DFE taps. Similarly to the MR channel in an ideal system with no crosstalk noise, leveraging the CTLE block to provide more of the overall equalization burden is a sound tradeoff. Fig. 19: LR System Receive Slicer Vertical Eye Opening vs. Number of DFE Taps for PRBS15 data pattern
Again, it can be noted that for well-behaved channels that there is little benefit to architectures which employ high tap-count DFEs. After 5 DFE taps the benefit of each successive tap is significantly reduced for receivers which employ significant levels of CTLE gain peaking. However, systems that have only moderate levels of CTLE gain less than 10 db are required to employ DFE s with significantly more DFE taps which can significantly affect a links overall pj/bit figure-of-merit. BER = 1E-15 eye contour Fig. 20: Receive Slicer Data Eye with 24-dB CTLE and 5-tap DFE total equalization for a PRBS31 data pattern Figure 20 shows the expected data eye for the LR channel with 24-dB of gain peaking and a 5-tap DFE and appropriate transmit de-emphasis for this LR channel. It is evident that the eye is closed with only a few picoseconds of open horizontal eye and only 44mVpp of vertical eye opening. It should be noted that the resultant eye diagram does not include crosstalk and other system impairments. It is clear that although these higher loss channels are well behaved they do not result in adequate S/N margin at the receiver without the benefit of some other system techniques.
One such technique which is presently being discussed in the various standards bodies addressing channels with > 30 db of loss is to employ various levels of Forward Error Correction (FEC). Using FEC techniques to provide system coding gain which only needs to be on the order of several db for such cases as this LR channel can be implemented within the data protocol itself without having to overclock the data payload. The degradation in system link performance illustrated is a serious concern in lower density and lower loss interconnect applications such as those which are MR based. The highest impact of the degradation in system link performance is especially evident for LR based backplane systems which, typically employing very high density connectors having significant numbers of aggressor channels and smaller data eyes due to higher channel losses. Equalization of LR links having greater than 30 db of overall channel loss is extremely challenging. In practice, other techniques such as FEC will be required in order to provide coding gain to improve the overall S/N ratio.
5.0 Summary This paper has demonstrated key receiver based equalization tradeoffs that can be considered when implementing next-generation robust MR and LR high loss channels. For the case of a high loss MR channel it was shown that CTLE based analog equalization is able to carry a significant portion of the overall equalization burden in practical implementations despite the fact that it does have the property of amplifying system crosstalk noise. Similarly, many typical high-loss LR channels are also able to benefit by trading off the equalization burden between receiver CTLE and DFE blocks in order to ensure suitable robustness while maximizing the overall transceiver per lane pj/bit figure-of-merit. It is important to mention that equalization of LR links having greater than 30 db of overall channel loss is extremely challenging and in practice can only be achieved with the aid of other techniques such as including FEC information in the data protocol in order to provide some coding gain to improve the overall S/N ratio.
6.0 References [1] Frlan, E., Brown, D., Tremblay, F., Building on the OIF CEI-28G-VSR Implementation Agreement to Address Several New Applications, DesignCon, Santa Clara, Feb. 2012. [2] Palaniappan, A., Palermo, S., Power efficiency modeling and optimization of highspeed equalized electrical I/O architectures, IEEE 19 th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010. [3] OIF CEI-28G-MR Specification Consideration and Initial Draft, July 2012. [4] OIF CEI-25G-LR Baseline Clause Proposal, January 2011. [5] OIF Test Methodologies for CEI-28G-SR and CEI-25G-LR, January 2011.