TMS9927 and TMS9937 Single-Chip Video Timers/Controllers

TMS9927 and TMS9937 Single-Chip Vide Timers/Cntrllers Data Manual

IMPORTANT NOTICES Texas Instruments reserves the right t make changes at any time in rder t imprve design and t supply the best prduct pssible. TI cannt assume any respnsibility fr any circuits shwn r represent that they are free frm patent infringement. Cpyright 1982 Texas Instruments Incrprated

TABLE OF CONTENTS Sectin Title Page 1. INTRODUCTION 1.1 Descriptin... 1 1.2 Key Features................................................................... 1 1.3 Typical Applicatin... " 2 2. ARCHITECTURE 2.1 CPU Interface................................................................... 3 2.2 Cursr Cntrl.................................................................. 6 2.3 Hrizntal Cntrl............................................................... 6 2.4 Vertical Cntrl................................................................. 9 2.5 Self Lad... 12 2.6 Terminal Assignments... " 13 3. APPLICATIONS 3.1 TMS9900 Based System.......................................................... 14 3.2 TMS9940 Based System.......................................................... 20 3.3 Start up TMS9927... 21 3.4 Restrictins... 22 4. ELECTRICAL AND MECHANICAL SPECIFICATIONS 4.1 Abslute Maximum Ratings....................................................... 23 4.2 Recmmended Operating Cnditins... 23 4.3 Electrical Characteristics... 23 4.4 Timing Requirements... 23 4.5 Switching Characteristics... 23 5. MECHANICAL DATA 5.1 40 Pin Plastic Package... 26 5.2 40 Pin Ceramic Package.......................................................... 27 iii

LIST OF FIGURES Figure Title Pege 1 TMS9901-Based Applicatin.......................................................... 2 2 TMS9927/TMS9937 Self-Lad Functin................................................. 3 3 TMS9927/TMS9937 Architecture... 4 4 TMS4710 Character Generatr 5 x 7 Embedded Display Blck.............................. 12 5 TMS9900 BasedApplicatin FrTMS9927/TMS9937... 14 6 Pwer-Up Flw Chart... " 19 7 TMS9940 Applicatin With TMS9927/TMS9937 Using Self-Lad Feature...................... 21 8 TMS9927/TMS9937 VTC Timing Diagram................................................ 24 9 General Timing Infrmatin... " 24 10 Cmpsite SYNC Timing... 25 11 Vertical SYNC Timing............................................................... 25 LIST OF TABLES Table Title Page 1 Select Line (SO-S3) Cmmand Assignments............................................. 5 2 Cntrl Register Bit Assignments..................................................... 5 3 Active Characters Per Line Cmbinatins, Register 2..................................... 7 4 Skew Bit Cmbinatins And Resulting Delays........................................... 7 5 Hrizntal And Vertical Cntrl....................................................... 8 6 Cntrl Registers Prgramming Chart.................................................. 10 7 Typical TMS9900 Instructin Sequence... " 17 iv

1. INTRODUCTION 1.1 DESCRIPTION The TMS9927ITMS9937 single chip vide timer/cntrllers (VTC) frm Texas Instruments are pr duced with silicn'gate, N channel, MaS technlgy. These 40 pin devices generate vide display timing signals fr standard and nnstandard CRT mnitrs incrprating bth interlaced and nninterlaced frmats. The TMS9927 prvides nn interlaced peratin with either an even r dd number f scan lines per data rw; and interlaced peratin with an even number f scan lines per data rw. The TMS9937 prvides the same peratinal features as the TMS9927, plus interlaced peratin with an dd number f scan lines per data rw. Character distrtin caused by uneven beam current cmmn t dd field/even field interlacing f alphanumeric displays, may be eliminated by prgramming the TMS9937 fr an dd number f scan lines per data rw. The TMS9927/TMS9937 are designed as memry mapped I/O devices, but can be cmmunicated with ver a CRU interface via the TMS9901. The TMS9927/TMS9937 prvide nine, user prgrammable cntrl registers. Seven f the registers cntrl hrizntal and vertical frmatting, and tw registers cntrl the cursr address. The in herent flexibility f the cntrl registers make pssible a wide variety f cst effective applicatins. 1.2 KEY FEATURES Standard and nnstandard CRT mnitrs Interlaced r nninterlaced frmats Scrlling capability Prgrammable display frmat: Characters per rw Rws per frame Raster scans per rw Raster scans per frame Prgrammable mnitr timing: Blanking Hrizntal sync Vertical sync Cmpsite sync Prgrammable via micrprcessrs r PROMS Cursr utput N Channel, silicn gate MaS device Standard 40 pin plastic r ceramic package Equivalent t CRT 5027/CRT 5037 by SMC.

1.3 TYPICAL APPLICATION The TMS9927ITMS9937 may be interfaced t a CPU thrugh the cmmunicatins register unit (CRU) via a TMS9901 as shwn in Figure 1. Fllwing is a tutrial discussin f this applicatin. Subsequent sectins f this manual detail the many aspects f the TMS9927/TMS9937 usage in trduced here. The TMS9901 accepts serial data bits and serial select bits frm the CRU and creates parallel data select lines fr the TMS9927 /TMS9937. One ther bit, chip select, nt shwn n the diagram, thrugh the TMS 9901 interface causes the VTC t mnitr its data and select lines. The character clumn lines (HO-H7) and rw lines (DRO-DRS) are cmbined t address the refresh RAM. The refresh RAM utputs the seven-bit ASCII character fr display. The TMS4710 character generatr uses the raster scan cunter (RO R3) utputs t select the rw f the dt matrix fr utput. A shift register then shifts the dt infrmatin t the vide circuit at the vide dt frequency. The TMS9927ITMS9937 als feature self lad functins as shwn in Figure 2. This functin is effected by placing the SELF-LOAD cmmand n the VTC select lines and strbing DATA STROBE (00). SELF-LOAD will cause the TMS9927/TMS9937 t transmit addresses n their rw select lines t the cntrl PROM (74S288). The utputs f the cntrl PROM are laded int the VTC cntrl registers. There are tw types f self-lad: prcessr and nn prcessr. The NON PROCESSOR SELF LOAD functin will autmatically start the timing chain after lad is cmpleted. The PROCESSOR SELF-LOAD functin will simply cause a self-lad and then wait fr a START cm mand frm the prcessr. The cmmand t the VTC, which causes self lad, shuld be applied fr the entire duratin f self-lad. CRU TMS 9901 SYSTEM INTERFACE VIDEO DOT 74160 CLOCK DOT COUNTER I DOT CARRY DCC TMS 9900 CPU I" "' DATA BUS 0 ~ TO SYSTEM U AO-A14 n ADDRESS BUS A5A14 DO-D7 v TO SYSTEM I/O I/O DUAL-PORT REFRESH MEMORY 1K X 8 7-BIT ASCII 4 BITS SELECT 8 BITS OATA CHARACTER ADDRESS 1J TMS 4710 CHARACTER GENERATOR SCAN ROW 'C ~ f------'\ --y SO-S3 DO-D7 TMS 9927 TMS 9937 VTC Hl-H7 DR1-DR5 HO/DRO RO-R3 74166 SHIFT REGISTER HORIZ SYNC VERT SYNC COMPOSITE SYN C BLANKING Q r-- ~ VIDEO DOT CLOCK FIGURE 1 - TMS9901 BASED APPLICATION 2

>-------------~--~SO S1 S2 S3 CS 8 BIT DATA BUS TMS 9927/ TMS 9937 LJ OS RO-R3 SELF-LOAD -~::l CS (FROM SYSTEM) 32 X8 PROM 748288 AO-3 1\.---------, A3 A4 +5 V ROW SELECT TO CHARACTER GENERATOR FIGURE 2 - TMS9927ITMS9937 SELF-LOAD FUNCTION 2. ARCHITECTURE The architecture f the TMS9927JTMS9937 vide timer/cntrller (VTC) diagrammed in Figure 3, permits maximum design flexibility. Simply by prgramming the cntrl registers apprpriately, mst raster-scan CRTs may be cntrlled by the TMS9927JTMS9937. The TMS9927/TMS9937 can be subdivided int five sectins: CPU interface, cursr cntrl, hrizntal cntrl, vertical cntrl, and self lad. Each f these subsectins will be discussed in the fllwing paragraphs. 2.1 CPU INTERFACE 2.1.1 General The select lines, SO S3, select the cntrl register fr lading and reading via the data bus, 00-07. The lines als select cntrl functins fr the device. Table 1 lists the 16 assignments fr the fur select lines. The bit assignments fr the nine cntrl registers are listed in Table 2. Nte that bth the cursr rw address and character address can be read frm and written t indicating that the VTC data bus is bidirectinal. 3

ADDRESS ~-----I~ DECODE CHARACTER COUNTER SYNC RO R2 R3 BL 00-07 VIDEO FIGURE 3 - TMS9927/TMS9937 ARCHITECTURE

TABLE 1 - SELECT LINE (50 53) COMMAND ASSIGNMENTS SO 51 52 53 COMMAND REMARKS 0 0 0 0 LOAD CONTROL REGISTER 0 0 0 0 1 LOAD CONTROL REGISTER 1 0 0 1 0 LOAD CONTROL REGISTER 2 0 0 1 1 LOAD CONTROL REGISTER 3 See Table 2 0 1 0 0 LOAD CONTROL REGISTER 4 0 1 0 1 LOAD CONTROL REGISTER 5 0 1 1 0 LOAD CONTROL REGISTER 6 0 1 1 1 PROCESSOR SELF LOAD Instructs TMS9927/TMS9937 t enter self lad mde. 1 a 0 0 READ CURSOR ROW ADDRESS 1 0 0 1 READ CURSOR CHARACTER ADDRESS 1 0 1 0 RESET Resets timing chain t tp left f page. Reset is latched n chip by data strbe (OS), and cunters are held until released by START cmmand. 1 0 1 1 UP SCROLL Increments address f first displayed data rw n page; i.e., prir t receipt f SCROLL cmmand tp line = 0, bttm line = 23; after receipt f SCROLL cmmand tp line = 1, bttm line = O. 1 1 0 0 LOAD CURSOR CHARACTER ADDRESS 1 1 0 1 LOAD CURSOR ROW ADDRESS 1 1 1 0 START TIMING CHAIN After a Reset r Prcessr SELF LOAD cmmand, this cm mand releases the timing chain apprximately ne scan line later. Synchrnus peratin f mre than ne TMS9927ITMS 9937 shuld have the dt cunter held lw during the 55 fr this cmmand. 1 1 1 1 NON PROCESSOR SELF LOAD TMS9927/TMS9937 will begin self lad via PROM when 55 ges lw. (The 1111 cmmand shuld be maintained n SO S3 lng enugh t guarantee self lad, i.e., the scan cunter shuld cy cle at least nce.) Self Lad is autmatically terminated and tim ing chain initiated when the all ONEs cnditin is remved (in dependent f DS). Synchrnus peratin f mre than ne TMS9927/TMS9937 shuld have the Dt Cunter Carry held lw when the cmmand is remved. TABLE 2 - CONTROL REGISTER BIT ASSIGNMENTS REGISTER FUNCTION BITS Register 0 Hrizntal character cunt 0 1 2 3 4 5 6 7 Register 1 Mde interlaced/nn interlaced 0 H sync width 1 2 3 4 H sync delay 5 6 7 Register 2 Scans/data rw 1 2 3 4 characters/data rw 5 6 7 Register 3 Skew bits 0 1 data rws/frame 2 3 4 5 6 7 Register 4 Scan lines/frame 0 1 2 3 4 5 6 7 Register 5 Vertical data start 0 1 2 3 4 5 6 7 Register 6 Last displayed data rw 2 3 4 5 6 7 Register 7 Cursr character address 0 1 2 3 4 5 6 7 Register 8 Cursr rw address 2 3 4 5 6 7 5

2.1.2 Device Initializatin: (a) Under micrprcessr cntrl-the device can be reset under system r prgram cntrl by presenting a 1010 address n SO S3. The device will remain reset at the tp f the even field page un til a START cmmand is executed by presenting a 1110 address n SO S3. (b) Via "Self Lading"-ln a nn prcessr envirnment, the self-lading sequence is effected by presenting and hlding the 1111 address n SO S3, and is initiated by the receipt f the strbe pulse (OS). The 1111 address shuld be maintained lng enugh t ensure that all seven registers have been laded (in mst applicatins under ne millisecnd). The timing sequence will begin ne line scan after the 1111 address is remved. In prcessr-based systems, self lading is initiated by presenting the 0111 address t the device. Self lading is terminated by the START cmmand, which als initiates the timing chain. 2.1.3 Scrlling In additin t the Register 6 strage f the last displayed data rw, a SCROLL cmmand (address 1011) increments the first displayed data rw cunt t facilitate up-scrlling in certain applicatins. 2.2 CURSOR CONTROL Tw f the nine cntrl registers n the TMS9927ITMS9937 are dedicated t cursr cntrl. Register seven (R7) cntains the eight-bit cursr character address (the address within a rw that is the cur rent cursr psitin). Register eight (R8) has the six bit rw address f the cursr. Under sftware cntrl the psitin f the cursr is defined by writing t these registers. Hence, t mve the cursr t the next hrizntal psitin, the user simply increments the value f R7, the cursr character address register, assuming the cursr is nt at the end f the line. Cursr psitin is tracked by the tw registers, a feature that can be useful fr light pen applicatins. When the character cunter (H lines) and data rw cunter (DR lines) utputs match the cursr character and cursr rw address registers, respectively, a pulse is utput n the CRV pin indicating the current cursr psitin. As the cursr psitin changes, the cursr address registers must be updated under sftware cntrl. 2.3 HORIZONTAL CONTROL The TMS9927/TMS9937 hrizntal cntrl sectin is cntained in fur registers, RO R3, which cn trl six functins, including: Ttal hrizntal character cunt Hrizntal sync width Hrizntal sync delay Characters per data rw Skew Data rws per frame Bits in Register 1 3, which pertain t vertical frmatting, are discussed in Sectin 2.4. Hrizntal cntrl (Sectin 2.3) and vertical cntrl (Sectin 2.4) are summarized in Tables 5 and 6. 6

2.3.1 Register 0 Register 0 (RO) cntains the 8 bit hrizntal character cunt. Because the cunt starts with zer, the hrizntal character cunt is the ttal number f characters in a line minus ne. Fr example, if a line cntains 32 displayed characters plus eight characters fr hrizntal retrace, RO will ttal 39. 2.3.2 Register 1 Fur bits (1-4) f Register 1 (R1) are used t stre the hrizntal sync width in character times. Frm ne t 15 character times are allwed. Hrizntal sync delay is indicated with three bits (5-7). Sync delay can be given frm ne t seven character times. In each case, zer is nt allwed. Bit seven is the least-significant bit. 2.3.3 Register 2 Register 2 (R2) cntains the number f characters per data rw. The MSB (bit 0) is nt used. Three bits (5 7) indicate the number f active characters per data rw: frm 20 t 132 active characters may be present in a data rw. The bit cmbinatins indicating which f the eight predefined number f active characters per data rw selected are listed in Table 3. TABLE 3 - ACTIVE CHARACTERS PER LINE BIT COMBINATIONS, REGISTER 2 D5 D6 D7 ACTIVE CHARACTERS/DATA ROW 2.3.4 Register 3 0 0 0 20 0 0 1 32 0 1 0 40 0 1 1 64 1 0 0 72 1 0 1 80 1 1 0 96 1 1 1 132 Register 3 (R3) cntains skew infrmatin. Tw bits (0-1) can be prgrammed t skew r delay sync, blanking, and cursr a predefined number f character times. Table 4 lists the skew bit cmbinatins and the resulting delay. TABLE 4 - SKEW BIT COMBINATIONS AND RESULTING DELAYS DO D1 SYNC AND BLANK DELAY' CURSOR DELAY' 'Character times 0 0 0 0 0 1 2 1 1 0 1 0 1 1 2 2 7

TABLE 5 - HORIZONTAL AND VERTICAL CONTROL FUNCTIONS DEFINITIONS Hrizntal Frmatting: CharacterslData Rw Hrizntal Sync Delay Hrizntal Sync Width Hrizntal Line Cunt Skew Bits A 3-bit cde prviding eight mask-prgrammable character lengths frm 20 t 132. The standard device will be masked fr the fllwing character lengths; 20, 32, 40, 64, 72, 80, 96, and 132. Three bits assigned prviding up t 8 character times fr generatin f "frnt prch". Fur bits assigned prviding up t 15 character times fr generatn f hrizntal sync width. Eight bits assigned prviding up t 256 character times fr ttal hrizntal frmatting A 2-bit cde prviding fr a 0 t 2 character skew (delay) between the hrizntal address cunter and the blank and sync (hrizntal, vertical, cmpsite) signals allwsretiming f vide data prir t generatin f cmpsite vide signal. The Cursr Vide signal is als skewed as a functin f this cde. Vertical Frmatting: Interlaced/Nn-interlaced Scans/Frame This bit prvides fr data presentatin with dd/even field frmatting fr interlaced systems. It mdifies the vertical timing cunters as described belw. A lgic 1 establishes the interlace mde. Eight bits assigned, defined accrding t the fllwing equatins: Let X = value f 8 assigned bits. 1) In interlaced mde - scans/frame = 2X + 513. Therefre fr 525 scans, prgram X '" 6. (00000110). Vertical sync will ccur precisely every 262.5 scans, thereby prducing tw interlaced fields. Range = 513 t 1023 scans/frame, dd cunts nly. 2) In nn-interlaced mde - scans/frame = 2X + 256. Therefre fr 262 scans, prgram X = 3. (00000011). Range = 256 t 766 scans/frame, even cunts nly. In either mde, vertical sync width is fixed at three hrizntal scans ('" 3H). Vertical Data Start Vertical Rws/Frame Last Data Rw ScanslData Rw Eight bits defining the number f raster scans frm the leading edge f vertical sync until the start f display data. At this raster scan, the data rw cunter is set t the data rw address at the tp f the page. Six bits assigned prviding up t 64 data rws per frame. Six bits t allw up r dwn scrlling via a prelad defining the cunt f the last displayed data rw. Fur bits assigned prviding up t 16 scan lines per data rw. 8

2.4 VERTICAL CONTROL The vertical cntrl sectin cnsists f three registers, R4 R6, and parts f R1 R3. The vertical cn trl functins are: Raster scans per frame Vertical data start Last displayed data rw Interlaced mde indicatr Scans per data rw Data rws per frame Vertical cntrl is summarized in Tables 5 and 6. 2.4.1 Registers 1 3 Three vertical cntrl functins are perfrmed in cntrl registers R1 R3. They are interlaced mde indicatr, scans per data rw, and data rws per frame. R1 bit 0 is used t indicate the interlace mde; a ne in this bit indicates interlaced mde and a zer indicates nninterlaced peratin. Fr the TMS9927, bth interlaced and nn interlaced mdes, R2 bits 1 4 are used t stre the number f raster scans per data rw minus 1; e.g. if 12 scans are wanted per data rw, this sectin f R2 wuld cntain 11. In the interlaced mde, this s_ectin f R2, must cntain an even number (minus ne) since the LSB f the scan als serves as the dd r even field indicatr. Fr the TMS9937, interlaced mde nly, R2 bits 1 4 are used t stre the number f raster scans per data rw minus 2; i.e., if 1 5 scans are wanted per data rw, this sectin f R2 must cntain 13. In this mde, unlike the TMS9927, this sectin f R2 can cntain an even r dd number (minus 2). In nn interlaced mde, peratin is the same as the TMS9927. R3 bits 2 7 are used t indicate the ttal number f data rws per frame minus ne. 9

TABLE 6 - CONTROL REGISTERS PROGRAMMING CHART FUNCTIONS Character/Data Rw: DEFINITIONS Hrizntal Line Cunt: Ttal characters/line = N + 1, N =0 t 225 = (D7= LSB) Active Characters/ D5 D6 D7 Data Rw 0 0 0-20 0 0 1 = 32 0 1 0 = 40 0 1 1 = 64 1 0 0 = 72 1 0 1 = 80 1 1 0 = 96 1 1 1 = 132 Hrizntal Sync Delay: Hrizntal Sync Width: = N, frm 1 t 7 character times (D7 = LSB) (N = 0 disallwed) = N, frm 1 t 15 character times (D4 = LSB) (N = 0 disallwed) Sync/Blank Cursr Delay Delay Skew Bits: D1 DO (Character Times) 0 0 0 0 1 0 1 0 0 1 2 1 1 1 2 2 Scans/Frame: Eight bits assigned, defined accrding t the fllwing equatins: Let X = value f 8 assigned bits. (D7 = LSB) 1) In interlaced mde - scans/frame = 2X + 513. Therefre fr 525 scans, prgram X = 6 (00000110). Vertical sync will ccur precisely every 262.5 scans, thereby prducing tw interlaced fields. Range = 513 t 1023 scans/frame, dd cunts nly. 2) In nn interlaced mde - scans/frame = 2X + 256. Therefre fr 262 scans, prgram X = 3 (00000011 ). Range = 256 t 766 scans/frame, even cunts nly. In either mde, vertical sync width is fixed a three hrizntal scans ( = 3H). Vertical Data Start: Data Rws/Frame: N = number f raster lines delay after leading edge f vertical sync f vertical start psitin. (D7 = LSB) Number f data rws = N + 1, N = 0 t 63 (D7 = LSB) Last Data Rw: N = Address f last displayed data rw, N =0 t 63, i.e.; fr 24 data rws, prgram N =23. (D7=LSB) Mde: Scans/Data Rw: Register, 1, DO = 1 establishes Interlace. Interlace Mde TMS9927: Scans per data rw = N + 1 where N = prgrammed number f data rws. N =0 t 15. Scans per data rw must be even cunts nly TMS9937: Scans per data rw = N + 2. N = 0 t 14, dd r even cunts Nn lnterlace Mde TMS9927ITMS9937: Scans per data rw = N + 1, dd r even cunt. N = 0 t 15. 10

2.4.2 Register 4 All eight bits f Register 4 (R4) are used t indicate the ttal number f raster scans per frame. In interlaced mdel the ttal scans per frame is twice the cntents f R4, plus 513. Fr example, if 525 scans are desired, R4 shuld cntain 6_ (2 x 6 + 513 = 525), and vertical sync will ccur exactly every 262.5 scans. In interlaced mde, nly dd cunts are permitted between 513 and 1023. T prgram the ttal number f scans per frame using the nn-interlaced mde, the cntents f R4 are multiplied by 2 and added t 256. Therefre, if 262 scans per frame are required in the nninterlaced mde, R4 shuld be prgrammed as 3- (2 x 3 + 256 = 262). Only even cunts are permitted fr nn-interlaced mdes between 256 and 766. In bth mdes, vertical sync width is equal t three hrizntal scans. 2.4.3 Register 5 Cntrl Register 5 (R5) cntains the vertical-data-start indicatr. This is the 8-bit number f raster scans delay, after the start f vertical sync t valid vide data. The delay permits vertical retrace and signals the TMS9927/TMS9937 the number f raster scans after the start f vertical sync t display data. 2.4.4 Register 6 Register 6 (R6) uses six bits (2-7) t stre the address f the last displayed data rw minus ne. The tw mst significant bits are nt used. If R3 is prgrammed fr 32 data rws, and if it is desired t have line 13 as the bttm line, then R6 shuld be prgrammed with 13-1 = 12. In this example, line 14 wuld be the tp line and line 1 and 32 wuld be cntiguus near the middle f the screen. NOTE Character cunter utputs (H lines) are active during blanking and vertical retrace. 2.4.5 Timing Example Timing cnsideratins must cmprehend the particular mnitr t be cntrlled. Fr the purpses f this discussin, the fllwing timing cnstraints are assumed: 63.5 micrsecnds per hrizntal scan and 60 frames per secnd, nn-interlaced, 262 scans per frame. A ttal f 63.5 micrsecnds per hrizntal scan elapse frm the beginning f ne hrizntal raster scan t the beginning f the next, including hrizntal retrace. If a display f 32 characters per data rw is desired, 40 ttal characters per data rw must be used t calculate timing. At this character width eight character times are needed fr hrizntal sync and retrace. Assuming that each character blck is eight dts wide, a character blck shwn in Figure 4, cnsists f the display matrix plus the spacing between characters. The dt frequency f the assumed system is: 5.04 MHz = 15,750 Hz x (32 + 8) char/line x 8 dts/char (63.5 usec/scan = 15750 Hz) 11

5 8 FIGURE 4 - TMS471 0 CHARACTER GENERATOR 5 X 7 EMBEDDED DISPLAY BLOCK Since apprximate bandwidth equals dt frequency divided by tw, the bandwidth needed by this system is 2.52 MHz. The designer must ensure the particular mnitr can handle this bandwidth. Since a standard TV mnitr has a bandwidth f 4.5 MHz, it culd satisfactrily accept the 2.52 MHz wrst case vide signal cmputed abve. Therefre, a user culd use a hme TV t implement this ap plicatin. The vide screen is cmpletely refreshed 60 times per secnd in the nn interlaced frmat. A ttal f 262 scans per frame are made f which 240 scans display vide data and 22 scans are used fr high vertical sync and retrace. If the design dictates 20 data rws per frame, each data rw is 12 scans high. 2.5 SELF LOAD The TMS9927JTMS9937 features tw self lad peratins: prcessr and nn prcessr. The cm mand n the select lines fr prcessr self lad is 0111 and fr nn prcessr self lad is 1111. The nn prcessr SELF LOAD cmmand must be applied n the select line lng enugh t ensure that self lad is cmpleted. SELF LOAD is initiated when OS is strbed. Issuing a nn prcessr SELF LOAD cmmand causes a self lad and, upn remval f the all ONEs state frm the select lines (independent f OS), the timing chain will begin. A prcessr SELF LOAD cmmand nly causes the TMS9927JTMS9937 t lad its registers. A START cmmand then is needed t start the timing chain. During self lad, VTC-prduced cntrl register cmmands lad the apprpriate registers (see Table 2). Therefre, if cursr rw and character psitin registers require resetting via self lad, the PROM wrds fr addresses 1100 and 1101 shuld be prgrammed as all ZEROs. 12

2.6 TMS9927fTMS9937 TERMINAL ASSIGNMENTS SIGNATURE DO (MSB) 01 D2 D3 D4 D5 D6 D7 (LSB) SO (MSB) S1 S2 S3 (LSB) PIN 18 19 20 21 22 23 24 25 2 1 40 39 14 13 6 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 DESCRIPTION DO thrugh D7 cnstitute the data bus. The data serves as input fr cntrl register cntents t VTC and utput fr cursr ad dress read data. See nte belw. SO thrugh S3 are the select lines, used t select the cntrl register t be laded r ther cntrl functin. See nte belw. POWER SUPPLIES Supply vltage (5 V NOM) Supply vltage (12 V NOM) Grund reference 51 s C5 RU Rl V.. R2 R3 iii CSVN cc VOO Vcc HSYN CRV BL 02 00 152 39 53 38 H7 37 1 H6 36 I H5 35 ) H4 34 J H3 33 H2 32 1 HI 31 HO/DRO 30 ORI 29 IOR2 26 OR3 27 J OR4 26 OR5 25 07 24 06 23 s 22 104 21 103 3 Chip select alerts TMS99271TMS9937 that it is being addressed. HSYN VSYN CSYN 9 15 11 10 Data strbe strbes data frm D()'D7 int the register pinted t by S lines r ut f cursr cntrl registers (LOW active). Hrizntal sync ges active (HIGH) t indicate hrizntal retrace. Vertical sync ges active (HIGH) t indicate vertical retrace. Cmpsite sync prvides a RS 170, cmpsite sync wavefrm, active nly in nn interlaced mde and is f the same width as HSYN. BL 17 Blanking, when active (HIGH), defines nnactive prtin f hrizntal and vertical scans. DR1 OR2 OR3 DR4 DR5(LSB) 30 29 28 27 26 Data rw cunter utputs t the refresh memry indicate which data rw is being displayed. See nte belw. HO/DRO H1 H2. H3 H4 H5 H6 H7 (LSB) 31 32 33 34 35 36 37 38 Output is MSB f character cunter if MSB f character per data rw is a ONE; therwise, utput is MSB f data rw cunter. Character cunter utputs t the refresh memry indicate which character in the data rw is being displayed. See nte belw. RO(MSB) R1 R2 R3 4 5 7 8 Scan cunter utputs t character generatr indicate which scan lines f character, are t be utput. In interlaced mde, R3 defines which field is being displayed, dd r even. See nte belw. DCC 12 Dt cunter carry, carry frm ff device character dt cunter, establishes basic character clck rate. CRY 16 Cursr vide, when active (HIGH), defines cursr lcatin. NOTE: The terminal assignments fr the TMS99271TMS9937 fllw Texas Instruments cnventin f bit 0 being the mst significant bit. 13

3. APPLICATIONS 3.1 TMS9900 BASED SYSTEM 16 rws f 64 characters Nninterlaced frmat 5 x 7 display matrix embedded in an 8 x 12 field 63.5 micrsecnds per hrizntal sweep Vertical refresh 60 times per secnd Mnitr has 262 scans per frame. Figure 5 is a blck diagram f a TMS9900-based applicatin fr the VTC used as a memry-mapped device. The TMS9900 cntrls VTC functins but is nt necessarily dedicated t that purpse. The dual-prt memry can be any system, which allws bth CPU and VTC access t it. The reset circuit shwn in the blck diagram prvides bth the necessary pwer-up reset and a pushbuttn reset ptin. Three subsystems may be defined in the blck diagram: TMS9900, memry, and vide. TO CRT MONITOR Q 01 LOAD LOGIC -5V 5V 12V GND TMS 9900 DATA BUS 00-015 ADDRESS LOGIC 7 BIT ASCii ADDRESS BUS AO-A 14 DOT COUNTER 74LS160A +5 5.03 MHz --i l.uf ~ RESET FIGURE 5 - TMS9900 BASED APPLICATION FOR TMS99271TMS9937 14

The TMS9900 prtin f the 9900-based perfrms any functin requiring an interface t a CRT mnitr. The cmpnents f the 9900 subsystem include a TMS9900, a TMS9904, system memry, and reset circuitry. The TMS9900 subsystem, shwn in the blck diagram, is the minimum system necessary t interface the TMS99271TMS9937. The memry subsystem cnsists f fur elements: an address decder and three memry elements system memry, dual-prt refresh RAM, and TMS9927ITMS9937, each f which is selected by the address decder. The system memry is that prtin f memry that the TMS9900 uses t stre its instructins and data. The refresh RAM stres the ASCII characters the system uses t drive the display. The TMS9927ITMS9937 is used as a memry-mapped 1/0 device. The 7-bit ASCII cde utput frm the refresh RAM is cmbined with the least significant three bits f the scan cunter utputs t generate a 10-blt address t the TMS4710 character generatr. The TMS9927ITMS9937 ccupies 16 eight-bit wrds in the system memry space. Since the VTC has an 8-bit bus and the TMS9900 has a 16-bit bus, the eight mst-significant bits f the TMS9900 data bus are cnnected t the TMS9927ITMS9937. The vide utput subsystem cmprises a dt clck, a dt cunter (74LS160A), a shift register (74LS166), and a TMS4710 character generatr. The dt clck, which scillates at the vide dt frequency, clcks the shift register, sending ut vide t the Z input f the CRT. The dt clck als increments the dt cunter, which cunts dts until the number f hrizntal dts in a character have been utput. Then the cunter ntifies the VTC, via the dt cunter carry (DCC) line, that a character has been utput. Upn receipt f a pulse n the DCC line, the TMS99271TMS9937 updates the character cunter utputs (H lines), scan cunter utputs (R lines), and data rw cunter utputs (DR lines). Since there are 13 lines f character select frm the TMS9927ITMS9937, sme address derivatin lgic may be needed t cmbine the 13 lines with the crrect number f address lines fr the particular refresh memry. The utput f the refresh RAM is a 7-bit ASCII character. The ASCII cde and the scan cunter utputs (R lines) are cmbined t generate an address fr the TMS4710 character generatr. The TMS4710 generates an 8 x 8 character blck with an embedded 5 x 7 display dt matrix. The eight bits frm the TMS4710 are sent t the shift register t be shifted ut at the vide dt frequency by the dt clck. 3.1.1 Design Particulars The typical applicatin described belw is a display with 16 rws f 64 characters each, and the CRT mnitr is a standard mnitr (nn interlaced mde). This standard mnitr has 262 ttal scans per frame, f which 22 are used fr vertical sync and retrace, leaving 240 scans t display infrmatin. Since there are 16 data rws per frame and each rw cnsists f 12 scans, there will be 48 unused scans. Of these 12 scans per rw, seven are used t display infrmatin, and five scans are used fr vertical spacing. In the hrizntal directin 64 characters per rw are specified at a fixed hrizntal scan time f 63.5 micrsecnds per scan. The time needed t effect hrizntal sync and retrace fr a CRT mnitr can be calculated by multiplying 63.5 micrsecnds by 0.18, (18 percent f hrizntal sweep time is fr retrace) btaining 11.43 micrsecnds. Since 11.43 micrsecnds fr retrace, plus the number f display characters, times the time per character shuld yield 63.5 micrsecnds, slve fr the time per character as fllws: r I h 63.5 usec - 11.43 usec 0.814 usec Ime c ar = 64 char = char 15

Next calculate the number f characters times fr hrizntal sync and retrace. Divide 11.43 micrsecnds by 0.814 micrsecnds/char, and rund t the next highest integer, btaining 15 character times fr back prch, hrizntal sync and hrizntal retrace. Thus, there are 79 ttal characters per data rw. A 63.5 micrsecnds per rw scan time equals a scan frequency f 15,750 hertz. Multiply the scan frequency by the ttal number f characters t find character frequency, and multiply character frequency by dts-per-character t btain dt frequency: dt frequency = 15,750 hertz x (64 + 15) char/rw x 8 dts/char = 9.954 megahertz T calculate the bandwidth the mnitr must handle, divide the dt frequency by tw. In this typical system the mnitr must accept a bandwidth f 4.977 megahertz. In the vertical directin 12 scans per character are needed; this includes seven scans fr display infrmatin and five scans fr spacing. There are 16 data rws, each cnsisting f 12 scans, giving a ttal f 192 scans. The standard mnitr used in this example has 262 ttal scans per frame, f which 240 are used fr displayable data and 22 fr vertical sync and retrace. Only 192 scans f the 240 displayable scans are used, leaving 48 scans. The 48 scans are cmpensated by using cntrl register 5, vertical data start. The vertical data start register is used t vertically center the data rws. The screen display size is 16 rws f 64 characters each, which ttals 1024 displayed characters. The minimum size f the refresh memry is 1024 wrds f seven bits each. Depending n the refresh memry architecture and cmpnent speeds, pipelining f memry may be necessary t achieve system speed. The six least-significant bits f the character cunter utputs (H lines) can be cnnected t the ieast the least-significant bits f the refresh memry address lines. Six bits can uniquely address all 64 characters f the data line. If there were 72 characters per data rw, seven bits wuld be needed t represent this, but 56 f the 128 pssible cmbinatiris wuld nt be used, thus requiring sme address cmpressin lgic. The fur least significant bits f the data rw cunter utputs (DR lines) are then tied t the mst-significant bit inputs f its refresh memry. Fur bits can uniquely address the 16 data rws. This is pssible withut any address mdificatin since 16 is an exact integral pwer f tw. The three least-significant bits f the scan cunter utputs (R1-R3) are cnnected t the least significant address bit inputs f the TMS4710 character generatr. The seven bits f ASCII cde frm the refresh memry are then cnnected t the mst-significant bits f the address inputs f the TMS4710. Since three bits f the scan cunter are used, nly eight scan lines per character can be addressed, which is all the TMS4710 stres. In rder t blank the last fur f the 12 scan rws fr vertical spacing, sme circuitry is needed t ensure that the shift register is nt laded with data frm the TMS4710 s that its utput is blank fr these scans. The dt cunter (74LS160A) is clcked at the vide dt frequency. When it cunts eight (the number f dts per character), it generates the carry that is used as the input t the TMS9927 dt cunter carry (DCC). 3.1.2 Pwer Up Upn pwer-up the TMS9900 must initialize the vide interface. The first lgical step in this prcess is t ensure that the refresh RAM is clear. Next, the cntrl registers shuld be laded. A typical TMS9900 instructin sequence t accmplish this functin is listed belw (Table 7) and flwchart in Figure 6. 16

TABLE 7 - TYPICAL TMS9900 INSTRUCTION SEQUENCE LOOP TABLE RO R1 R2 R3 R4 R5 R6 LI CLR LI LI MOV CI JL AL CLR CLR CLR EQU DATA DATA DATA DATA DATA DATA DATA R7, FD14 SET POINTER TO VTC RESET *R7 RESET VTC R7, FDOO SET POINTER TO START ADDRESS OF VTC IN MEMORY R8, TABLE SET POINTER TO VALUES FOR VTC CONTROL REGISTERS *R8 +, *R7 + SEND EIGHT BIT CONTROL WORD TO TMS9927 R7, FDOE HAVE 7 CONTROL WORDS BEEN SENT? LOOP R7,10 SET ADDRESS TO PERFORM CURSOR LOAD * R7 + CURSOR CHARACTER ADDRESS SET TO ZERO * R7 + CURSOR ROW ADDRESS SET TO ZERO *R7 START TMS9927/TMS9937 TIMING CHAIN $ 4EOO 7AOO 5BOO 4FOO 0300 4600 OFOO 3.1.2.1 Register 0 Hrizntal Character Cunt = 4E16 = 78 + 1 = 79 17

3.1.2.2 Register 1 : 1 > : 1 w :5 II: w I Z Z z : 1 : 0 R1 3.1.2.3 Register 2 0:1:0:1:1 w (J) ::J I Z RO 3.1.2.4 Register 3 '-v-' ------~v~------~ DELAY H SYNC 2 16 DATA ROWS CHAR TIMES AND PER FRAME CURSOR 1 CHAR TIME (TABLE 4) R3 3.1.2.5 Register 4 R4 (2*3) + 256 = 262 scans per frame (nninterlaced) 3.1.2.6 Register 5 R5 4616 = 7010 scans after VSYN and befre valid fr vertical data start 3.1.2.7 Register 6 : 1 R6 16 is last displayed data rw 18

RESET VTC LOAD REGISTER WITH TABLE VALUE N LOADED y ZERO CURSOR CHARACTER ZERO CURSOR ROW FIGURE 6 - POWER UP FLOWCHART 19

The TMS9927/TMS9937-cntrlled display is nw running and utputting a blank screen. The cursr is visible in the upper left-hand crner f the screen (external circuitry uses the cursr vide (CRV) utput f the TMS9927/TMS9937 t generate the cursr). Anything placed in the refresh RAM nw will be displayed autmatically. The TMS9900 may place a character in the refresh memry f this system simply as fllws: MOV CHAR, *R4+ MOVE DATA AT CHAR TO REFRESH RAM Nte that R4 must cntain the pinter int refresh RAM t signify where the character is suppsed t g. The five least-significant bits f R4 cntain the character rw address and the next s~ix bits cntain the rw number. As described in a previus sectin, an address derivatin scheme t the refresh RAM might be required. And, as each character is added t the refresh memry, It will be desirable t update the cursr psitin by issuing the cursr lad mmands. 3.1.3 Scrlling Srlling is easily impiemented in this system. When the scrll cmmand is issued, the tp data rw displayed is mved t the bttm data rw, the remainder f the screen is mved up ne line, thus prducing a wrap-arund scheme. Therefre, t implement a scrll up, a scrll cmmand is issued and the new bttm line data shuld be cleared by sftware r verwritten by new data. Multiple scrlling is accmplished by relading Register 6 r by multiple iteratins f the scrll cmmand. 3.2 TMS9940 BASED SYSTEM 3.2.1 GENERAL A typical TMS9940 applicatin using the TMS9927/TMS9937 t functin as an intelligent terminal is diagrammed in Figure 7. This system cmprises three subsystems: keybard Interface, TMS9927ITMS9937 interface, and a vide generatin sectin. In this applicatin the TMS9940 is dedicated t cntrlling the CRT mnitr. The keybard interface enables the user t cmmunicate character and cntrl infrmatin t the CPU. The interface cnsists f a keybard, ASCII cnverter, and 1/0 lines t the TMS9940. Many special functin keys n the keybard may be defined in the TMS9940 sftware, and the ASCII cnverter als may be implemented in TMS9940 sftware. The CPU cmmunicates with and cntrls the VTC thrugh the TMS9927ITMS9937 Interfae. This interface cnsists f the select lines, the self lad PROM, and the dual-prt refresh RAM. The select lines cntrl the TMS99271TMS9937 by issuing SELF-LOAD and CURSOR ADDRESS UPDATE cmmands. The tw cursr address registers can be read by first issuing a READ CURSOR LINE ADDRESS cmmand and sampling the eight I/O prts, Which are used as the data bus. Next, the READ CURSOR CHARACTER ADDRESS Is issued, and again the data bus is sampled. Befre the data bus is read, the I/O line cnnected t DS must be set LOW. The cursr address register is prgrammed similarly except the DS I/O lines are nt set LOW until valid data is utput n the data bus I/O lines. The 74S288 is a 32-wrd by a-bit PROM, which cntains the cntrl wrds fr the TMS99271TMS9937 cntrl register. When the SELF-LOAD cmmand frm the CPU is received, the VTC scan cunter utputs (R lines) either send addresses t the PROM r send data fr PROM cntrl registers. If the CPU issues a NON PROCESSOR SELF-LOAD mmand, it must be acmpanied by a START m mand; therwise, n START cmmand is needed with a SELF-LOAD. The dual-prt refresh RAM is identical t that desribed in Setin 3.1. 20

~ ~~ Veel 5 MHz rd~ '5V XTAL 1 XTAL2 S 1.'0 SO HORiZONTAL SYNC mrr I/O 51 VERTICAL SYNC VCC2 I/O 52 COMPOSITE SYNC I/O m TMS 9940 HiJj - I/O I 1,'0 KEYBOARD I/F I/O 53 BLANK 8 BIT DATA BUS I 1 IL~ TMS9927 TMS9937 I/O 10 BfT ADDRESS 745188 I 00 07 I DAO-DA4 C l.-- HO H6 DOC AO A3 ~ ADDRESS 10 " I ~j. ~ AO A9 DUAL PORT MEMORY AO-A3 A' AS A7 AS IMS 4710 I ~ A9 CARRY A8 74LS160A CK.1 [ V KEYBOARD SHIFT CK REGISTER a 1 I ~ DOT CLOCK I l FIGURE 7-TMS9940 APPLICATION WITH TMS9927ITMS9937 USING SELF LOAD FEATURE 3.3 START UP, TMS9927 When emplying micrprcessr-cntrlled lading f the TMS9927 registers, the fllwing sequence f instructins is necessary: ADDRESS COMMAND 1 1 1 0 Start Timing Chain 1 0 1 0 Reset 0 0 0 0 Lad Register 0 0 0 Lad Register 6 1 0 Start Timing Chain The sequence f START, RESET, LOAD, START ensures prper initializatin f the registers; hwever, this sequence is nt required if register lading is accmplished by either f the Self-Lad mdes. This sequence is ptinal with the TMS9937. 21

3.4 RESTRICTIONS 1. Only ne pin is available fr strbing data int the device via the data bus. The cursr X and Y crdinates are therefre laded int the chip by presenting ne set f addresses and utput ted by presenting a different set f addresses. Therefre the standard WRITE and READ cntrl signals frm mst micrprcessrs must be "NORed" externally t present a single strbe (OS) signal t the device. 2. In interlaced mde the ttal number f character slts assigned t the hrizntal scan must be even t insure that vertical sync ccurs precisely between hrizntal sync pulses. 22

4. TMS9927/TMS9937 ELECTRICAL AND MECHANICAL SPECIFICATIONS 4.1 ABSOLUTE MAXIMUM RATING OVER OPERATING FREE AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) Supply vltage, VCC (see Nte 1)... -0.3 V t 10 V Supply vltage, VDD... -0.3 V t 18V All inputs and utputs vltage............................................. -0.3 V t 18 V Cntinuus pwer dissipatin... 1.25 W Free air perating temperature range... O C t 70 C Strage temperature range... -65 C t.150 C NOTE: Vltage values are with respect t Vss. 4.2 RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM MAX UNIT Supply vltage. V CC 4.75 5 5.25 V Supply vltage, VOO 11.4 12 12.6 V Grund reference, VSS 0 V High level input vltage, VIH VCC-1.5 VCC V Lw level input vltage, V I L O.S V Operating free-air temperature, T A 0 70 c 4.3 ELECTRICAL CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TVP MAX UNIT AO A3. 00 07 (IOH = SOIlA) 2.4 VOH High level utput vltage V All thers (loh - 40 "A) 2.4 RO R3 (IOL - 3.2 mal 0.4 VOL Lw-level utput vltage V All thers (IOL = 1.6 mal 0.4 II Input current SO S3, CS V I N = 0.4 250 All thers O"VIN"VCC 10 ICC(av) Average supply current frm VCC SO 100 ma IOO(av) Average supply current frm VOO 40 70 ma los Oata bus leakage in input mde 10 "A Oata bus 10 15 Ci I nput capacitance Clck, OS 25 40 pf All thers 10 15 4.4 TIMING REQUIREMENTS - TMS9927: T A = 2S"C; TMS 9937: TA = O C t 70 C PARAMETER MIN TVP MAX UNIT tc(cb) Dt cunter cycle time 250 2000 ns tr(cb) Rise time 10 50 ns tf(p) Fall time 10 50 ns tw(cbl) Width f lw clck 215 ns tw(ph) Width f high clck 35 ns tw(os) Width f OS lw level 150 10,000 ns tsu1 Setup time - address bus, chip select 125 ns tsu2 Setup time - data bus 125 ns th1 Hld time - address bus, chip select 50 ns th2 Hld time - data bus 75 ns 4.S SWITCHING CHARACTERISTICS TMS9927: T A = 2SC; TMS9937: T A = OOC t 70 C PARAMETER CONDITIONS MIN TVP MAX UNIT tpd1 Prpagatin delay, OS t DO D7 valid CL = 50 pf 125 ns tpd2 Prpagatin delay I Dt cunt carry t HO H7, HS, VS, SL, CRY, COMP SYNC CL = 20 pf 125 tpd3 Prpagatin delay. HSYNC t RO R3, DRO DR5 CL - 20 pf 500 ns tpd4 Prpagatin delay. OS t D()"D7 invalid CL = 50 pf 5 60 ns "A ns 23

ADDRESS CHIP SELECT DBO-7...----tsu 1-----..., '-- VALID DATA I I -J "'-"-'''''-l~_, i4-----t su 2 ------t. L LOADING I VALID DATA I OF DATA ------- ---I"''''''''''''''''''-''-'~ "A06:~~~imz7m7TOT~j7JTm{277l-~A,:;:~~ ~ Os -----------t=- 'wlo" t -'1'... tpd4 -..I HSYNC -..,1 ~'"'----------:"-------- RO-3- ~ --...!~--~...--------- DRO-5 ---------------------------f~- R3-RO and DR5-DRO may change prir t the falling edge f HSYNC. HORIZONTAL TIMING FIGURE 8 - TMS9927fTMS9937 VTC TIMING DIAGRAM' c=: START OF LINE N START OF LINE N+1 ~ rtt/zzzzzzzzzzzzi n --...!j-r-z'7'"""":z""""z ACTIVE VIDEO = CHARACTER PER DATA LINE HORIZONTAL SYNC DELAY (FRONT PORCH) HORIZONTAL SYNC WIDTH VERTICAL TIMING START OF FRAME M OR ODD FIELD.. --------HORIZONTAL LINE COUNT = H ------... ~ ~~~-------------SCANLINESPERFRAME--------~~~ START OF FRAME M +1 OR EVEN FIELD ~~_~IZ~Z~Z~Z~Z~Z~Z~Z~Z~Z~Z~Z~Z~Z~Z~Z~Z~I_~r--1~ ~I~Z~Z~Z~7 r 1 VERTICAL DATA START ACTIVE VIDEO = DATA ROWS PER FRAME FIGURE 9 - GENERAL TIMING ~I ~VERTICAL SYNC = 3H Ii' All switching times are assumed t be at 10% r 90% values. 24

VOH HSYNC VOL VOH VSYNC VOL VOH COMPOSITE SYNC VOL FIGURE 10 - COMPOSITE SYNC TIMING --------------FRAMEM --------4."'I -~----------FRAMEM-t1----------... SCANSI ~H""" DATAROW COUNTER R3 I 1 N=9 I SCAN COUNTER IS HELO- RESET DURING V BLANK 0_ DATA ROW --, ~U2~TER DREi 1L...--~2::2----' DATA ROW COUNTER MAINTAINS LAST COUNT DURING V BLANK BLANK..IL...'UUIU1.n.'UIU'UI..ILItJIUUl:.n..n..ItJIU :L.LA;;;NiKK- 23 \ 23... ~,, --' r VERTICAL DATA START SCAN -(REGISTER 5) VERTICAL SYNC VERTICAL SYNC EXAMPLE BASED ON: Nn-lnWfI... ed (RegiltIII' 1. Bit 0"'01. 24 data rws. 10 SCIIns/dlta rw FIGURE 11 - VERTICAL SYNC TIMING 25

5. MECHANICAL DATA 5.1 TMS9927ITMS993740-PIN PLASTIC PACKAGE... I- BMAX -I ~ ":,':!::~< :::7CJI [:Al 1 f?\~seatingplan:~j'v\~~~~ I~i twm~~tobi --''-- 0 011 0 003 003310 841--"1 [I.J! j I j 0125 i3 171 -,r 10279 00761 NOM,--I ~ MIN - NOM MAX 0,018 0.003 0.07011)81 PIN SPACING 0,070 (1,78) (0,457 0,0761 MAX 010012,54) ALL LINEAR DIMENSIONS ARE IN INCHES AND PARENTHETICALLY IN MILLIMETERS. INCH DIMENSIONS GOVERN. ~ DIM 8 16 18 20 22 24 28 40 A. 0.01010.261 0.30017.621 0.30017,621 030017,621 0.30017,621 0.400 II 0,1 61 0.600 IIS,241 0.600 IIS,241 0.600 (10,24) B MAX 0.39019,91 0.870122,1 I 0.920 123,41 1.070 (27,2) 1.100128,01 1.290132,81 1.440136,61 2090lS3,11 C NOM 0.2S0 16.41 0.2S0 16.41 0.25016,41 0.26SI6,7I 0.3S0 18.91 O.SSO 114,01 0.550 (14,0) 0.550114,0) 26

5.2 TM59927ITM59937 40 PIN CERAMIC PACKAGE Ceramic packages are prvided with side-brazed leads and a metal, epxy, r glass lid seal. ct. ial 002~1~ 51) l r 0070 (1,78) MAX 0.200 (5,08) MAX ~ SEATINGSeel~ -I- ~ ~~- PLANE T ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~J --I~ 0.011, 0.003 (0,279 ± 0,076) _.11... 0018' 0003 J I I ~ I-- (0,457, 0,076) 0.100 (2,54) NOM 0070 (1,78) MAX I-- 0125(3,17) MIN NOTES: a. This minimum spacing is valid fr printed circuit bard munting with 0.033 (0,84) diameter hles fr the leads. b. All linear dimensins are in inches and parenthetically in millimeters. Inch dimensins gvern. c, The index is placed in this area t identify pin 1 and t prvide ther infrmatin as fllws: 1 Pin 1 cnnected t chip-munting pad...1xx Pin XX cnnected t chip-munting pad. N cnnectin t chip-munting pad. Other symbls may indicate any cmbinatin f up t 4 pins cnnected t the chip-munting pad. D~S 16 18 20 22 24 28 40 A! 0.01010,26) 0.30017,621 0.30017,621 0.300 17,621 0.400110.161 0.600 (15,24) 0.600 115.241 0.600 115.241 B MAX 0.840 (21,4) 0.910123.11 1.020125.91 1.100128,01 1.290132.81 1.415136.01 2.020151,31 C NOM 0.290(7,4) 0.290 (7,4) 0.290 (7,4) 0.390 i9,9) 0.590 (15,0) 0.590 (15,0) 0.590 (15,0) 27

TEXAS INSTRUMENTS INCORPORATED JUNE 1982 MP058 Pst Office Bx 1443 I Hustn, Texas 77001 Semicnductr Grup Printed in U.S.