I. INTRODUCTION. Figure 1: Explicit Data Close to Output
|
|
- Joel Tyler
- 5 years ago
- Views:
Transcription
1 Low Power Shift Register Design Based on a Signal Feed Through Scheme 1 Mr. G Ayappan and 2 Ms.P Vinothini, 1 Assistant Professor (Senior Grade), 2 PG scholar, 1,2 Department of Electronics and Communication, Sri Ramakrishna Institute of Technology,Coimbator, India Abstract: A Flip-flop has become a basic storage element in all kinds of digital design but there is a long discharging path problem in flip-flop. In order to overcome this problem a technique of low power pulse triggered flip-flop (P-FF) based on a signal feed through scheme is used. In this project shift registers are designed based on that flip-flop. This method provides low power, better speed and minimum area compared with other designs. PIPO shift register is designed because the output coming a single clock pulse. The technology used here is CMOS 250nm technology. The simulations are carried out using Tanner EDA software. This software contains S Edit, T Spice, W Edit and L Edit windows. S Edit window is used to design the circuit. T Spice window is used to generate the program for the circuit. The layout is generated automatically using the L Edit. The number of transistor is reduced from 116 to 96 and the power is reduced from 31μw to 25μw which in turn reduces layout area using this method Keywords: Shift register; Pass transistor; FF pulse generator; I. INTRODUCTION Shift Registers are a type of sequential logic circuit, mainly used for storing digital data. They are group of Flip-flops connected in a chain and the output from one Flip-flop becomes the input of the next Flip-flop. Register consist of set of n Flip-flop and each Flip-flop stores one data and they have two basic functions, they are data storage and data movement. A Register is a device that allows each of the Flip-flops to pass the stored information to its adjacent neighbour. The storage capacity of a register is the total number of bits (1 or 0) of digital data it can retain. Each stage (flip flop) in a shift register represents one bit of storage capacity. Therefore the number of stages in a register determines its storage capacity. It features parallelinputs, parallel outputs, right shift, left shift, serial inputs and reset. The appropriate choice of flip-flop (FF) topologies is of fundamental importance in the design of VLSI integrated circuits and low-energy Microprocessor. Indeed, FFs affect the clock frequency, since their delay occupies a significant fraction of the clock cycle, especially in fast microarchitectures with low logic depth. FFs are part of the clock network, which is responsible for 30% 50% of the whole chip energy budget [1]-[4]Reduced swing clock driver and a special flip-flop to reduce leakage current was designed in [5]. In order to reduce the total power of the system clock swing should be reduced because clock system power is directly proportional to clock swing or sometimes directly proportional to square of the clock swing. This Flip-flop consists of true single phase master latch and cross coupled NAND slave latch. The type the pulse generation control logic, an AND function is removed from the critical path to facilitate a faster discharge operation[6]. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulseenhancement technique is devised to speed up the discharge along the critical path only when needed. The conditional discharge flip-flop [7]-[10]is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output In this paper Shift registers are designed with the help of signal feed through scheme that is feeding the input directly to the internal node of the latch design to speed up the data transition and this is done with the help of pass transistor. The main aim of the paper is to reduce the long discharging path problem in conventional explicit type pulse triggered Flip-flop and to design a PIPO shift register using signal feed through scheme for providing better speed and performance with low power and minimum area consumption. This paper is organised as follows. Section II discusses about types of flipflop. Section III explained a Pass transistor design based flipflop. The PIPO shift register is described in section IV.The results of comparison and simulation of the shift registers in Section V. Finally, the conclusion is drawn in Section VI. II. TYPES OF FLIPFLOP The true single phase clocked register (TSPCR) uses a single clock, CLK. For the positive latch, when CLK is high, the latch is in the transparent mode and corresponds to two cascaded inverters; the latch is non-inverting, and propagates the input to the output On the other hand, when CLK=0, both inverters are disabled, and the latch is in the hold mode. Only the pull-up networks are still active, while the pull-down circuits are deactivated. As a result of the dual-stage approach, no signal can ever propagate from the input of the latch to the output in this mode. A register can be constructed by cascading positive and negative latches. Figure 1: Explicit Data Close to Output Explicit data close to output flipflip shown in figure1 consist of NAND-logic-based pulse generator and a semi dynamic True Single Phase Clock (TSPC) structured latch design. In this P-FF design, inverters I3 and I4 are used to latch the data, and inverters I1 and I2 are used to hold the internal node X. The pulse width is determined by the delay of three inverters. This design suffers from a serious drawback, i.e., the internal node X is discharged on every rising edge of the clock in spite Available Online@ 303
2 of the presence of a static input 1.This gives rise to large switching power dissipation To overcome this problem, many remedial measures such as Conditional capture, conditional precharge, conditional discharge, and Conditional pulse enhancement scheme have been proposed. An extra nmos transistor MN3 controlled by the output signal Q_fdbk is employed so that no discharge occurs if the input data remains 1. In addition, the keeper logic for the internal node X is simplified and consists of an inverter plus a pull-up pmostransistor. Figure 2: Conditional Discharge Flipflop To overcome this delay for better speed performance, a powerful pull-down circuitry is needed, which causes extra layout area and power consumption. The modified hybrid latch Flip-flop (MHLFF) shown in Figure 3. The keeper logic at node X is removed. A weak pull-up transistor MP1controlled by the output signal Q maintains the level of node X when Q equals 0. Figure 3: Modified Hybrid Latch Flipflop III. PASS TRANSISTOR FLIPFLOP Recalling the four circuits discussed chapter they all encounter the same worst case timing occurring at 0 to 1 data transitions. Referring to Figure 4 the pass transistor Flip-flop adopts a signal feed-through technique to improve this delay. Similar to the SCDFF design, this Flip-flop also employs a static latch structure and a conditional discharge scheme to avoid superfluous switching at an internal node. However, there are three major differences that lead to a unique TSPC latch structure and make the pass transistor design distinct from the previous one Figure 4: Pass Transistor Flipflop First, a weak pull-up pmos transistor MP1 with gate connected to the ground is used in the first stage of the TSPC latch. This gives rise to a pseudo nmos logic style design, and the charge keeper circuit for the internal node X can be saved. In addition to the circuit simplicity, this approach also reduces the load capacitance of node second, a pass transistor MNx controlled by the pulse clock is included so that input data can drive node Q of the latch directly (the signal feed-through scheme).along with the pull-up transistor MP2 at the second stage inverter of the TSPC latch, this extra passage facilitates auxiliary signal driving from the input source to node Q. The node level can thus be quickly pulled up to shorten the data transition delay. Third, the pull-down network of the second stage inverter is completely removed. Instead, the newly employed pass transistor MNx provides a discharging path. The role played by MNx is thus twofold, i.e., providing extra driving to node Q during 0 to 1 data transitions, and discharging node Q during 1 to 0 data transitions. Compared with the latch structure used in SCDFF design, the circuit savings of the pass transistor logic include a charge keeper (two inverters), a pull-down network (two nmos transistors), and a control inverter. The only extra component introduced is an nmos pass transistor to support signal feed through. This scheme actually improves the 0 to 1 delay and thus reduces the disparity between the rise time and the fall time delays. In comparison with other P-FF designs such as EP-DCO, CDFF, and SCDFF, the pass transistor design shows the most balanced delay behaviour. The principles of FF operations of the pass transistor logic are explained as follows. When a clock pulse arrives, if no data transition occurs, i.e., the input data and node Q are at the same level, on current passes through the pass transistor MNx, which keeps the input stage of the FF from any driving effort. At the same time, the input data and the output feedback Q_fdbk assume complementary signal levels and the pull-down path of node X is off. Therefore, no signal switching occurs in any internal nodes. On the other hand, if a 0 to 1 data transition occurs, node X is discharged to turn on transistor MP2, which then pulls node Q high. Referring to Figure 4.this corresponds to the worst case timing of the FF operations as the discharging path conducts only for a pulse duration. However, with the signal feed through scheme, a boost can be obtained from the input source via the pass transistor MNx and the delay can be greatly shortened. Although this seems to burden the input source with direct charging/discharging responsibility, which is a common pitfall of all pass transistor logic, the scenario is different in this case because MNx conducts only for a very short period. Available Online@ 304
3 Referring to Figure 4.6 when a 1 to 0 data transition occurs, transistor MNx is likewise turned on by the clock pulse and node Q is discharged by the input stage through this route. Unlike the cascade of 0 to 1 data transition, the input source bears the sole discharging responsibility. Since MNx is turned on for only a short time slot, the loading effect to the input source is not significant. In particular, this discharging does not correspond to the critical path delay and calls for no transistor size weaking to enhance the speed. In addition, since a keeper logic is placed at node Q, the discharging duty of the input source is lifted once the state of the keeper logic is inverted. IV. PIPO SHIFT REGISTER The are many types of shift registers used for storing purpose the are SISO,SIPO,PISO,PIPO etc. but parallel in parallel out is used in this paper because the output will comes in a single clock pulse For parallel in - parallel out shift registers, all data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. The figure 4.11 shows a four-bit parallel in - parallel out shift register constructed by D flip-flops. Figure 8: Output of Pass Transistor Flipflop Figure 5: block diagram of shift register The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the data at the D inputs appear at the Corresponding Q outputs simultaneously. Figure 4.11 shows the block diagram of PIPO shift register Figure 9: Layout of pass transistor flipflop Figure 6: Circuit Diagram of Shift Register V. SIMULATION AND COMPARISON RESULTS The simulation and the layout are generated using TANNER EDA software and the simulation results are shown in the figure 7 to 15 and the comparison results for the flipflop and the shift registers are shown in the table 1 and 2 Figure10: Circuit diagram of EPDCOflipflop Figure 7: circuit diagram of pass transistor Available Online@ 305
4 Figure 14: Output of pass transistor Figure 11: Output of EPDCO Figure 12: Layout of EPDCO Figure 15: Layout of pass transistor Table 1: Comparison Results for Flipflop PARAMETER EP DCO C D F F SCDFF PASS TRANSIST OR LOGIC No.of transistor Power(µw) PARAMETER Table 2: Comparison results for shift register EP DCO CDFF MHLFF PASS TRANSISTOR LOGIC No.of transistor Power(µw) Figure 13: Circuit diagram of pass transistor The comparison result shows that the number of transistors for the flipflop is reduced to 24 and the number of transistors for the shift registers are reduced to 96 as the same way the power is reduced to µw for flipflops and then the shift register power is reduced to 25.8µw. CONCLUSION The comparison result shows that the shift register using pass transistor Flip-flop has less number of transistor compared to Available Online@ 306
5 other shift register and consume less power compared to other shift register. It also seen that the number of transistor for pass transistor shift register is 96 but for other shift register like EPDCO, CDFF, SCDFF, MHLFF is greater than 100 and this reduce area and the simulation are carried out using tanner EDA software and the layout were generatedthe same method can be extended to more number of bits and can be used for higher data storage. It can be also used for other shift register like Serial In Serial Out (SISO), Serial In Parallel Out (SIPO) and Parallel In Serial Out (PISO). In the future References [1] B. Kong, S. Kim, and Y. Jun, Conditional-capture flip-flop for statistical power reduction, IEEE J. Solid-State Circuits, vol. 36, no. 8, pp , Aug [2] E. Consoli, M. Alioto, G. Palumbo, and J. Rabaey, Conditional pushpull pulsed latch with 726 fjops energy delay product in 65 nm CMOS, in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2012, pp [3] F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, R. Heald, and G. Yee, A new family of semi-dynamic and dynamic flip-flops with embedded logic for high-performance processors, IEEEJ. Solid-State Circuits, vol. 34, no. 5, pp , May [4] H. Partovi, R. Burd, U. Salim, F.Weber, L. DiGregorio, and D. Draper, Flow-through latch and edge-triggered flip-flop hybrid elements, in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1996,pp [5] H. Kawaguchi and T. Sakurai, A reduced clockswing flip-flop (RCSFF) for 63% power reduction, IEEE J. Solid-State Circuits, vol. 33, no. 5, pp , May [6] H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, Ultra low power clocking scheme using energy recovery and clock gating, IEEETrans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 1, pp , Jan [7] Jin Fa Lin Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 1, January [8] J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, Comparative delay and energy of single edge-triggered and dual edge triggered pulsed flip-flops for high-performance microprocessors, in Proc. ISPLED, 2001, pp [9] K. Chen, A 77% energy saving 22-transistor single phase clocking D-flip-flop with adoptive-coupling configuration in 40 nm CMOS, in Proc. IEEE Int. Solid-State Circuits Conf., Nov. 2011, pp [10] M. Alioto, E. Consoli, and G. Palumbo, General strategies to design nanometer flip-flops in the energy-delay space, IEEE Trans. CircuitsSyst., vol. 57, no. 7, pp , Jul [11] M. Alioto, E. Consoli, and G. Palumbo, Flip-flop energy/performance versus Clock Slope and impact on the clock network design, IEEETrans. Circuits Syst., vol. 57, no. 6, pp , Jun [12] M. Alioto, E. Consoli, and G. Palumbo, Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I- methodology and design strategies, IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 19, no. 5, pp , May [13] M. Alioto, E. Consoli and G. Palumbo, Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part II -results and figures of merit, IEEE Trans. Very Large Scale Integr. (VLSI)Syst., vol. 19, no. 5, pp , May [14] M.-W. Phyu, W.-L.Goh, and K.-S. Yeo, A lowpower static dual edge triggered flip-flop using an output-controlled discharge configuration, in Proc. IEEE Int. Symp. Circuits Syst., May 2005, pp [15] P. Zhao, T. Darwish, and M. Bayoumi, Highperformance and low power conditional discharge flip-flop, IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 12, no. 5, pp , May Available Online@ 307
An Optimized Implementation of Pulse Triggered Flip-flop Based on Single Feed-Through Scheme in FPGA Technology
An Optimized Implementation of Pulse Triggered Flip-flop Based on Single Feed-Through Scheme in FPGA Technology 1 S.MANIKANTA, PG Scholar in VLSI System Design, 2 A.M. GUNA SEKHAR Assoc. Professor, HOD,
More informationDESIGN OF DOUBLE PULSE TRIGGERED FLIP-FLOP BASED ON SIGNAL FEED THROUGH SCHEME
Scientific Journal Impact Factor (SJIF): 1.711 e-issn: 2349-9745 p-issn: 2393-8161 International Journal of Modern Trends in Engineering and Research www.ijmter.com DESIGN OF DOUBLE PULSE TRIGGERED FLIP-FLOP
More informationPERFORMANCE ANALYSIS OF AN EFFICIENT PULSE-TRIGGERED FLIP FLOPS FOR ULTRA LOW POWER APPLICATIONS
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 5.258 IJCSMC,
More informationDesign a Low Power Flip-Flop Based on a Signal Feed-Through Scheme
Design a Low Power Flip-Flop Based on a Signal Feed-Through Scheme Mayur D. Ghatole 1, Dr. M. A. Gaikwad 2 1 M.Tech, Electronics Department, Bapurao Deshmukh College of Engineering, Sewagram, Maharashtra,
More informationDesign of Pulse Triggered Flip Flop Using Conditional Pulse Enhancement Technique
Design of Pulse Triggered Flip Flop Using Conditional Pulse Enhancement Technique NAVEENASINDHU P 1, MANIKANDAN N 2 1 M.E VLSI Design, TRP Engineering College (SRM GROUP), Tiruchirappalli 621 105, India,2,
More informationLOW POWER DOUBLE EDGE PULSE TRIGGERED FLIP FLOP DESIGN
INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS ISSN 2320-7345 LOW POWER DOUBLE EDGE PULSE TRIGGERED FLIP FLOP DESIGN G.Swetha 1, T.Krishna Murthy 2 1 Student, SVEC (Autonomous),
More informationLow Power and Reduce Area Dual Edge Pulse Triggered Flip-Flop Based on Signal Feed-Through Scheme
Low Power and Reduce Area Dual Edge Pulse Triggered Flip-Flop Based on Signal Feed-Through Scheme Ch.Sreedhar 1, K Mariya Priyadarshini 2. Abstract: Flip-flops are the basic storage elements used extensively
More informationLOW POWER HIGH PERFORMANCE PULSED FLIP FLOPS BASED ON SIGNAL FEED SCHEME
LOW POWER HIGH PERFORMANCE PULSED FLIP FLOPS BASED ON SIGNAL FEED SCHEME Juhi Rastogi 1, Vipul Bhatnagar 2 1,2 Department of Electronics and Communication, Inderprastha Enginering College, Ghaziabad (India)
More informationDESIGN AND ANALYSIS OF LOW POWER STS PULSE TRIGGERED FLIP-FLOP USING 250NM CMOS TECHNOLOGY
DESIGN AND ANALYSIS OF LOW POWER STS PULSE TRIGGERED FLIP-FLOP USING 250NM CMOS TECHNOLOGY 1 M.SRINIVAS, 2 K.BABULU 1 Project Associate JNTUK, 2 Professor of ECE Dept. JNTUK Email: srinivas.mattaparti@gmail.com,
More informationAsynchronous Model of Flip-Flop s and Latches for Low Power Clocking
Asynchronous Model of Flip-Flop s and Latches for Low Power Clocking G.Abhinaya Raja & P.Srinivas Department Of Electronics & Comm. Engineering, Nimra College of Engineering & Technology, Ibrahimpatnam,
More informationLow Power Pass Transistor Logic Flip Flop
Low Power Pass Transistor Logic Flip Flop CH.Vijayalakshmi 1, S.Vijayalakshmi 2, M.Vijayalakshmi 3 Assistant professor, Dept. of ECE, St.Martin s Engineering College, Secunderabad, Andhrapradesh, India
More informationImprove Performance of Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop
Sumant Kumar et al. 2016, Volume 4 Issue 1 ISSN (Online): 2348-4098 ISSN (Print): 2395-4752 International Journal of Science, Engineering and Technology An Open Access Journal Improve Performance of Low-Power
More informationComparison of Conventional low Power Flip Flops with Pulse Triggered Generation using Signal Feed through technique
Comparison of Conventional low Power Flip Flops with Pulse Triggered Generation using Signal Feed through technique 1 Inder Singh, 2 Vinay Kumar 1 M.tech Scholar, 2Assistant Professor (ECE) 1 VLSI Design,
More informationA Low-Power CMOS Flip-Flop for High Performance Processors
A Low-Power CMOS Flip-Flop for High Performance Processors Preetisudha Meher, Kamala Kanta Mahapatra Dept. of Electronics and Telecommunication National Institute of Technology Rourkela, India Preetisudha1@gmail.com,
More informationA Novel Pass Transistor Logic Based Pulse Triggered Flip-flop with Conditional Enhancement
A Novel Pass Transistor Logic Based Pulse Triggered Flip-flop with Conditional Enhancement Shakthipriya.R 1, Kirthika.N 2 1 PG Scholar, Department of ECE-PG, Sri Ramakrishna Engineering College, Coimbatore,
More informationA Power Efficient Flip Flop by using 90nm Technology
A Power Efficient Flip Flop by using 90nm Technology Mrs. Y. Lavanya Associate Professor, ECE Department, Ramachandra College of Engineering, Eluru, W.G (Dt.), A.P, India. Email: lavanya.rcee@gmail.com
More informationDesign of Low Power Dual Edge Triggered Flip Flop Based On Signal Feed through Scheme
Design of Low Power Dual Edge Triggered Flip Flop Based On Signal Feed through Scheme S.Sujatha 1, M.Vignesh 2 and T.Kowsalya 3 PG Scholar [VLSI], Muthayammal Engineering College, Rasipuram, Namakkal,
More informationDesign of low power 4-bit shift registers using conditionally pulse enhanced pulse triggered flip-flop
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 5, Ver. II (Sep-Oct. 2014), PP 54-64 e-issn: 2319 4200, p-issn No. : 2319 4197 Design of low power 4-bit shift registers using conditionally
More informationPower Optimization Techniques for Sequential Elements Using Pulse Triggered Flip-Flops with SVL Logic
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) ISSN: 2319 4200, ISBN No. : 2319 4197 Volume 1, Issue 4 (Nov. - Dec. 2012), PP 31-36 Power Optimization Techniques for Sequential Elements Using Pulse
More informationADVANCES in NATURAL and APPLIED SCIENCES
ADVANCES in NATURAL and APPLIED SCIENCES ISSN: 1995-0772 Published BY AENSI Publication EISSN: 1998-1090 http://www.aensiweb.com/anas 2016 April 10(4): pages 105-110 Open Access Journal Design and Performance
More informationDesign of New Dual Edge Triggered Sense Amplifier Flip-Flop with Low Area and Power Efficient
Design of New Dual Edge Triggered Sense Amplifier Flip-Flop with Low Area and Power Efficient Ms. Sheik Shabeena 1, R.Jyothirmai 2, P.Divya 3, P.Kusuma 4, Ch.chiranjeevi 5 1 Assistant Professor, 2,3,4,5
More informationMinimization of Power for the Design of an Optimal Flip Flop
Minimization of Power for the Design of an Optimal Flip Flop Kahkashan Ali #1, Tarana Afrin Chandel #2 #1 M.TECH Student, #2 Associate Professor, 1,2 Department of ECE, Integral University, Lucknow, INDIA
More informationDesign of Shift Register Using Pulse Triggered Flip Flop
Design of Shift Register Using Pulse Triggered Flip Flop Kuchanpally Mounika M.Tech [VLSI], CMR Institute of Technology, Kandlakoya, Medchal, Hyderabad, India. G.Archana Devi Assistant Professor, CMR Institute
More informationDesign of a Low Power and Area Efficient Flip Flop With Embedded Logic Module
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 6, Ver. II (Nov - Dec.2015), PP 40-50 www.iosrjournals.org Design of a Low Power
More informationHigh Frequency 32/33 Prescalers Using 2/3 Prescaler Technique
High Frequency 32/33 Prescalers Using 2/3 Prescaler Technique Don P John (School of Electrical Sciences, Karunya University, Coimbatore ABSTRACT Frequency synthesizer is one of the important element for
More informationCERTAIN PERFORMANCE INVESTIGATIONS OF VARIOUS PULSE TRIGGERED FLIP FLOPS
Volume 119 No. 15 2018, 437-455 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ http://www.acadpubl.eu/hub/ CERTAIN PERFORMANCE INVESTIGATIONS OF VARIOUS PULSE TRIGGERED FLIP FLOPS R.MOHAN
More informationDesign And Analysis Of Implicit Pulsed Double Edge Triggered Clocked Latch For Low Power Applications
Design And Analysis Of Implicit Pulsed Double Edge Triggered Clocked Latch For Low Power Applications ¹GABARIYALA SABADINI C ²Dr. P. MANIRAJ KUMAR ³Dr. P.NAGARAJAN 1. PG scholar, VLSI design, Department
More informationDIFFERENTIAL CONDITIONAL CAPTURING FLIP-FLOP TECHNIQUE USED FOR LOW POWER CONSUMPTION IN CLOCKING SCHEME
DIFFERENTIAL CONDITIONAL CAPTURING FLIP-FLOP TECHNIQUE USED FOR LOW POWER CONSUMPTION IN CLOCKING SCHEME Mr.N.Vetriselvan, Assistant Professor, Dhirajlal Gandhi College of Technology Mr.P.N.Palanisamy,
More informationHIGH PERFORMANCE AND LOW POWER ASYNCHRONOUS DATA SAMPLING WITH POWER GATED DOUBLE EDGE TRIGGERED FLIP-FLOP
HIGH PERFORMANCE AND LOW POWER ASYNCHRONOUS DATA SAMPLING WITH POWER GATED DOUBLE EDGE TRIGGERED FLIP-FLOP 1 R.Ramya, 2 C.Hamsaveni 1,2 PG Scholar, Department of ECE, Hindusthan Institute Of Technology,
More informationDESIGN OF A NEW MODIFIED CLOCK GATED SENSE-AMPLIFIER FLIP-FLOP
DESIGN OF A NEW MODIFIED CLOCK GATED SENSE-AMPLIFIER FLIP-FLOP P.MANIKANTA, DR. R. RAMANA REDDY ABSTRACT In this paper a new modified explicit-pulsed clock gated sense-amplifier flip-flop (MCG-SAFF) is
More informationTHE clock system, composed of the clock interconnection
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 5, MAY 2004 477 High-Performance and Low-Power Conditional Discharge Flip-Flop Peiyi Zhao, Student Member, IEEE, Tarek K.
More informationDesign and Analysis of Semi-Transparent Flip-Flops for high speed and Low Power Applications in Networks
IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-issn: 2278-1676,p-ISSN: 2320-3331 PP 58-64 www.iosrjournals.org Design and Analysis of Semi-Transparent Flip-Flops for high speed and
More informationA NOVEL APPROACH TO ACHIEVE HIGH SPEED LOW-POWER HYBRID FLIP-FLOP
A NOVEL APPROACH TO ACHIEVE HIGH SPEED LOW-POWER HYBRID FLIP-FLOP R.Ramya 1, P.Pavithra 2, T. Marutharaj 3 1, 2 PG Scholar, 3 Assistant Professor Theni Kammavar Sangam College of Technology, Theni, Tamil
More informationEFFICIENT DESIGN OF SHIFT REGISTER FOR AREA AND POWER REDUCTION USING PULSED LATCH
EFFICIENT DESIGN OF SHIFT REGISTER FOR AREA AND POWER REDUCTION USING PULSED LATCH 1 Kalaivani.S, 2 Sathyabama.R 1 PG Scholar, 2 Professor/HOD Department of ECE, Government College of Technology Coimbatore,
More informationAn FPGA Implementation of Shift Register Using Pulsed Latches
An FPGA Implementation of Shift Register Using Pulsed Latches Shiny Panimalar.S, T.Nisha Priscilla, Associate Professor, Department of ECE, MAMCET, Tiruchirappalli, India PG Scholar, Department of ECE,
More informationLOW POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES
LOW POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES Mr. Nat Raj M.Tech., (Ph.D) Associate Professor ECE Department ST.Mary s College Of Engineering and Technology(Formerly ASEC),Patancheru
More informationP.Akila 1. P a g e 60
Designing Clock System Using Power Optimization Techniques in Flipflop P.Akila 1 Assistant Professor-I 2 Department of Electronics and Communication Engineering PSR Rengasamy college of engineering for
More informationAbstract 1. INTRODUCTION. Cheekati Sirisha, IJECS Volume 05 Issue 10 Oct., 2016 Page No Page 18532
www.ijecs.in International Journal Of Engineering And Computer Science ISSN: 2319-7242 Volume 5 Issue 10 Oct. 2016, Page No. 18532-18540 Pulsed Latches Methodology to Attain Reduced Power and Area Based
More informationA NOVEL DESIGN OF COUNTER USING TSPC D FLIP-FLOP FOR HIGH PERFORMANCE AND LOW POWER VLSI DESIGN APPLICATIONS USING 45NM CMOS TECHNOLOGY
A NOVEL DESIGN OF COUNTER USING TSPC D FLIP-FLOP FOR HIGH PERFORMANCE AND LOW POWER VLSI DESIGN APPLICATIONS USING 45NM CMOS TECHNOLOGY Ms. Chaitali V. Matey 1, Ms. Shraddha K. Mendhe 2, Mr. Sandip A.
More informationNovel Design of Static Dual-Edge Triggered (DET) Flip-Flops using Multiple C-Elements
Available online at: http://www.ijmtst.com/ncceeses2017.html Special Issue from 2 nd National Conference on Computing, Electrical, Electronics and Sustainable Energy Systems, 6 th 7 th July 2017, Rajahmundry,
More informationA Modified Static Contention Free Single Phase Clocked Flip-flop Design for Low Power Applications
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.8, NO.5, OCTOBER, 08 ISSN(Print) 598-657 https://doi.org/57/jsts.08.8.5.640 ISSN(Online) -4866 A Modified Static Contention Free Single Phase Clocked
More informationModeling and designing of Sense Amplifier based Flip-Flop using Cadence tool at 45nm
Modeling and designing of Sense Amplifier based Flip-Flop using Cadence tool at 45nm Akhilesh Tiwari1 and Shyam Akashe2 1Research Scholar, ITM University, Gwalior, India antrixman75@gmail.com 2Associate
More informationLow-Power and Area-Efficient Shift Register Using Pulsed Latches
Low-Power and Area-Efficient Shift Register Using Pulsed Latches G.Sunitha M.Tech, TKR CET. P.Venkatlavanya, M.Tech Associate Professor, TKR CET. Abstract: This paper proposes a low-power and area-efficient
More informationReduction of Area and Power of Shift Register Using Pulsed Latches
I J C T A, 9(13) 2016, pp. 6229-6238 International Science Press Reduction of Area and Power of Shift Register Using Pulsed Latches Md Asad Eqbal * & S. Yuvaraj ** ABSTRACT The timing element and clock
More informationdata and is used in digital networks and storage devices. CRC s are easy to implement in binary
Introduction Cyclic redundancy check (CRC) is an error detecting code designed to detect changes in transmitted data and is used in digital networks and storage devices. CRC s are easy to implement in
More informationHigh Performance Dynamic Hybrid Flip-Flop For Pipeline Stages with Methodical Implanted Logic
High Performance Dynamic Hybrid Flip-Flop For Pipeline Stages with Methodical Implanted Logic K.Vajida Tabasum, K.Chandra Shekhar Abstract-In this paper we introduce a new high performance dynamic hybrid
More informationEnergy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications
Energy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy School of Electrical and Computer Engineering, Purdue University, West
More informationArea Efficient Pulsed Clock Generator Using Pulsed Latch Shift Register
International Journal for Modern Trends in Science and Technology Volume: 02, Issue No: 10, October 2016 http://www.ijmtst.com ISSN: 2455-3778 Area Efficient Pulsed Clock Generator Using Pulsed Latch Shift
More informationEFFICIENT POWER REDUCTION OF TOPOLOGICALLY COMPRESSED FLIP-FLOP AND GDI BASED FLIP FLOP
EFFICIENT POWER REDUCTION OF TOPOLOGICALLY COMPRESSED FLIP-FLOP AND GDI BASED FLIP FLOP S.BANUPRIYA 1, R.GOWSALYA 2, M.KALEESWARI 3, B.DHANAM 4 1, 2, 3 UG Scholar, 4 Asst.Professor/ECE 1, 2, 3, 4 P.S.R.RENGASAMY
More informationEmbedded Logic Flip-Flops: A Conceptual Review
Volume-6, Issue-1, January-February-2016 International Journal of Engineering and Management Research Page Number: 577-581 Embedded Logic Flip-Flops: A Conceptual Review Sudhanshu Janwadkar 1, Dr. Mahesh
More informationDesign of Low Power and Area Efficient Pulsed Latch Based Shift Register
Design of Low Power and Area Efficient Pulsed Latch Based Shift Register 1 ANUSHA KORE, 2 Dr. S.A.MUZEER Department of ECE Megha Institute of Engineering & Technology For women s Edulabad, Ghatkesar mandal,
More informationDESIGN OF EFFICIENT SHIFT REGISTERS USING PULSED LATCHES 1 M. AJAY
DESIGN OF EFFICIENT SHIFT REGISTERS USING PULSED LATCHES 1 M. AJAY 2 G.SRIHARI 1 ajaymunagala.ajay@gmail.com 2 srihari.nan@gmail.com 1 PG Scholar,Dept of ECE, Sreenivasa Institute of Technology and Management
More informationFully Static and Compressed Topology Using Power Saving in Digital circuits for Reduced Transistor Flip flop
Fully Static and Compressed Topology Using Power Saving in Digital circuits for Reduced Transistor Flip flop 1 S.Mounika & 2 P.Dhaneef Kumar 1 M.Tech, VLSIES, GVIC college, Madanapalli, mounikarani3333@gmail.com
More informationAn Efficient Power Saving Latch Based Flip- Flop Design for Low Power Applications
An Efficient Power Saving Latch Based Flip- Flop Design for Low Power Applications N.KIRAN 1, K.AMARNATH 2 1 P.G Student, VRS & YRN College of Engineering & Technology, Vodarevu Road, Chirala 2 HOD & Professor,
More informationDesign of a High Frequency Dual Modulus Prescaler using Efficient TSPC Flip Flop using 180nm Technology
Design of a High Frequency Dual Modulus Prescaler using Efficient TSPC Flip Flop using 180nm Technology Divya shree.m 1, H. Venkatesh kumar 2 PG Student, Dept. of ECE, Nagarjuna College of Engineering
More informationDesign of Conditional-Boosting Flip-Flop for Ultra Low Power Applications
Design of Conditional-Boosting Flip-Flop for Ultra Low Power Applications Jalluri Jyothi Swaroop Department of Electronics and Communications Engineering, Sri Vasavi Institute of Engineering & Technology,
More informationPower Analysis of Double Edge Triggered Flip-Flop using Signal Feed-Through Technique
Power Analysis of Double Edge Triggered Flip-Flop using Signal Feed-Through Technique Pragati Gupta 1, Dr. Rajesh Mehra 2 M.E. Scholar 1, Associate Professor 2 Department of Electronic and Communication
More informationAN EFFICIENT LOW POWER DESIGN FOR ASYNCHRONOUS DATA SAMPLING IN DOUBLE EDGE TRIGGERED FLIP-FLOPS
AN EFFICIENT LOW POWER DESIGN FOR ASYNCHRONOUS DATA SAMPLING IN DOUBLE EDGE TRIGGERED FLIP-FLOPS NINU ABRAHAM 1, VINOJ P.G 2 1 P.G Student [VLSI & ES], SCMS School of Engineering & Technology, Cochin,
More informationDual Edge Adaptive Pulse Triggered Flip-Flop for a High Speed and Low Power Applications
International Journal of Scientific and Research Publications, Volume 5, Issue 10, October 2015 1 Dual Edge Adaptive Pulse Triggered Flip-Flop for a High Speed and Low Power Applications S. Harish*, Dr.
More informationLOW POWER LEVEL CONVERTING FLIP-FLOP DESIGN BY USING CONDITIONAL DISCHARGE TECHNIQUE
LOW POWER LEVEL CONVERTING FLIP-FLOP DESIGN BY USING CONDITIONAL DISCHARGE TECHNIQUE Keerthana S Assistant Professor, Department of Electronics and Telecommunication Engineering Karpagam College of Engineering
More informationDesign of Low Power D-Flip Flop Using True Single Phase Clock (TSPC)
Design of Low Power D-Flip Flop Using True Single Phase Clock (TSPC) Swetha Kanchimani M.Tech (VLSI Design), Mrs.Syamala Kanchimani Associate Professor, Miss.Godugu Uma Madhuri Assistant Professor, ABSTRACT:
More informationDesign of an Efficient Low Power Multi Modulus Prescaler
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 6, Issue 3 (March 2013), PP. 15-22 Design of an Efficient Low Power Multi Modulus
More informationIntroduction. Serial In - Serial Out Shift Registers (SISO)
Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
More informationNew Low Glitch and Low Power Flip-Flop with Gating on Master and Slave Latches
New Low Glitch and Low Power Flip-Flop with Gating on Master and Slave Latches Dandu Yaswanth M.Tech, Santhiram Engineering College, Nandyal. Syed Munawwar Assistant Professor, Santhiram Engineering College,
More informationAnalysis of Digitally Controlled Delay Loop-NAND Gate for Glitch Free Design
Analysis of Digitally Controlled Delay Loop-NAND Gate for Glitch Free Design S. Karpagambal, PG Scholar, VLSI Design, Sona College of Technology, Salem, India. e-mail:karpagambals.nsit@gmail.com M.S. Thaen
More informationLow Power Different Sense Amplifier Based Flip-flop Configurations implemented using GDI Technique
International Journal of Scientific and Research Publications, Volume 2, Issue 4, April 2012 1 Low Power Different Sense Amplifier Based Flip-flop Configurations implemented using GDI Technique Priyanka
More informationResearch Article Ultra Low Power, High Performance Negative Edge Triggered ECRL Energy Recovery Sequential Elements with Power Clock Gating
Research Journal of Applied Sciences, Engineering and Technology 7(16): 3312-3319, 2014 DOI:10.19026/rjaset.7.676 ISSN: 2040-7459; e-issn: 2040-7467 2014 Maxwell Scientific Publication Corp. Submitted:
More informationDESIGN AND IMPLEMENTATION OF SYNCHRONOUS 4-BIT UP COUNTER USING 180NM CMOS PROCESS TECHNOLOGY
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS 4-BIT UP COUNTER USING 180NM CMOS PROCESS TECHNOLOGY Yogita Hiremath 1, Akalpita L. Kulkarni 2, J. S. Baligar 3 1 PG Student, Dept. of ECE, Dr.AIT, Bangalore, Karnataka,
More informationDesign Of Pulsed Latch Based Shift Register Using Multiplexer With Reduced Power And Area
Design Of Pulsed Latch Based Shift Register Using Multiplexer With Reduced Power And Area Nandhini.N 1,Murugasami.R 2 1 PG Scholar,Nandha Engineering college,erode,india 2 Associate Professor,Nandha Engineering
More informationA Reduced Clock Power Flip-Flop for Sequential Circuits
International Journal of Engineering and Advanced Technology (IJEAT) A Reduced Clock Power Flip-Flop for Sequential Circuits Bala Bharat, R. Ramana Reddy Abstract In most Very Large Scale Integration digital
More informationGLITCH FREE NAND BASED DCDL IN PHASE LOCKED LOOP APPLICATION
GLITCH FREE NAND BASED DCDL IN PHASE LOCKED LOOP APPLICATION S. Karpagambal 1 and M. S. Thaen Malar 2 1 VLSI Design, Sona College of Technology, Salem, India 2 Department of Electronics and Communication
More informationMemory elements. Topics. Memory element terminology. Variations in memory elements. Clock terminology. Memory element parameters. clock.
Topics! Memory elements.! Basics of sequential machines. Memory elements! Stores a value as controlled by clock.! May have load signal, etc.! In CMOS, memory is created by:! capacitance (dynamic);! feedback
More informationAn efficient Sense amplifier based Flip-Flop design
An efficient Sense amplifier based Flip-Flop design Rajendra Prasad and Narayan Krishan Vyas Abstract An efficient approach for sense amplifier based flip-flop design has been introduced in this paper.
More informationPower Efficient Design of Sequential Circuits using OBSC and RTPG Integration
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 2, Issue. 9, September 2013,
More informationLow Power D Flip Flop Using Static Pass Transistor Logic
Low Power D Flip Flop Using Static Pass Transistor Logic 1 T.SURIYA PRABA, 2 R.MURUGASAMI PG SCHOLAR, NANDHA ENGINEERING COLLEGE, ERODE, INDIA Abstract: Minimizing power consumption is vitally important
More informationComparative Analysis of Pulsed Latch and Flip-Flop based Shift Registers for High-Performance and Low-Power Systems
IJECT Vo l. 7, Is s u e 2, Ap r i l - Ju n e 2016 ISSN : 2230-7109 (Online) ISSN : 2230-9543 (Print) Comparative Analysis of Pulsed Latch and Flip-Flop based Shift Registers for High-Performance and Low-Power
More informationComparative study on low-power high-performance standard-cell flip-flops
Comparative study on low-power high-performance standard-cell flip-flops S. Tahmasbi Oskuii, A. Alvandpour Electronic Devices, Linköping University, Linköping, Sweden ABSTRACT This paper explores the energy-delay
More informationLow Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered Flip Flop Based on Signal Feed-Through Scheme
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 5, Ver. I (Sep. - Oct. 2016), PP 33-41 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Low Power Area Efficient VLSI
More informationDesign of Pulse Triggered Flip-Flop Using Pass Transistor Logic for Low-Power Consumption
Design of Pulse Triggered Flip-Flop Using Pass Transistor Logic for Low-Power Consumption Abstract--In this brief, Pulse-triggered FF (P-FF) is a single-latch structure which is more popular than the conventional
More informationInternational Journal Of Global Innovations -Vol.6, Issue.I Paper Id: SP-V6-I1-P46 ISSN Online:
ANALYSIS OF LOW-POWER AND AREA-EFFICIENT SHIFT REGISTERS USING PULSED LATCH #1 GUNTI SUMANJALI, M.Tech Student, #2 V.SRIDHAR, Assistant Professor, Dept of ECE, MOTHER THERESSA COLLEGE OF ENGINEERING &
More informationISSN Vol.08,Issue.24, December-2016, Pages:
ISSN 2348 2370 Vol.08,Issue.24, December-2016, Pages:4666-4671 www.ijatir.org Design and Analysis of Shift Register using Pulse Triggered Latches N. NEELUFER 1, S. RAMANJI NAIK 2, B. SURESH BABU 3 1 PG
More informationInternational Journal of Engineering Research in Electronics and Communication Engineering (IJERECE) Vol 1, Issue 6, June 2015 I.
Low Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Using Power Gating Techniques [1] Shaik Abdul Khadar, [2] P.Hareesh, [1] PG scholar VLSI Design Dept of E.C.E., Sir C R Reddy College of Engineering
More informationAN EFFICIENT DOUBLE EDGE TRIGGERING FLIP FLOP (MDETFF)
AN EFFICIENT DOUBLE EDGE TRIGGERING FLIP FLOP (MDETFF) S.Santhoshkumar, L.Saranya 2 (UG Scholar, Dept.of.ECE, Christ the king Engineering college, Tamilnadu, India, santhosh29ece@gmail.com) 2 (Asst. Professor,
More informationSequential Logic. References:
Sequential Logic Reerences: Adapted rom: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles o CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationCMOS Low Power, High Speed Dual- Modulus32/33Prescalerin sub-nanometer Technology
IJSTE International Journal of Science Technology & Engineering Vol. 1, Issue 1, July 2014 ISSN(online): 2349-784X CMOS Low Power, High Speed Dual- Modulus32/33Prescalerin sub-nanometer Technology Dabhi
More informationDesign of Low Power Universal Shift Register
Design of Low Power Universal Shift Register 1 Saranya.M, 2 V.Vijayakumar, 3 T.Ravi, 4 V.Kannan 1 M.Tech-VLSI design, Sathyabama University, Jeppiaar Nagar, Rajiv Gandhi Salai, Chennai 119 2 Assistant
More informationDesign And Analysis of Clocked Subsystem Elements Using Leakage Reduction Technique
Design And Analysis of Clocked Subsystem Elements Using Leakage Reduction Technique Sanjay Singh, S.K. Singh, Mahesh Kumar Singh, Raj Kumar Sagar Abstract As the density and operating speed of CMOS VLSI
More informationParametric Optimization of Clocked Redundant Flip-Flop Using Transmission Gate
Parametric Optimization of Clocked Redundant Flip-Flop Using Transmission Gate Sapna Sadhwani Student, Department of ECE Lakshmi Narain College of Technology Bhopal, India srsadhwani@gmail.comm Abstract
More informationEL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043
EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP Due 16.05. İLKER KALYONCU, 10043 1. INTRODUCTION: In this project we are going to design a CMOS positive edge triggered master-slave
More informationDesign and analysis of RCA in Subthreshold Logic Circuits Using AFE
Design and analysis of RCA in Subthreshold Logic Circuits Using AFE 1 MAHALAKSHMI M, 2 P.THIRUVALAR SELVAN PG Student, VLSI Design, Department of ECE, TRPEC, Trichy Abstract: The present scenario of the
More informationSHIFT REGISTER USING CNT FET BASED ON SENSE AMPLIFIER PULSED LATCH FOR LOW POWER APPLICATION
SHIFT REGISTER USING CNT FET BASED ON SENSE AMPLIFIER PULSED LATCH FOR LOW POWER APPLICATION Muthusuriya.M 1, Shantha Devi.P 2, Poongodi.M 3 Gayathiri.G 4 1 PG Scholar, Department of ECE, Theni Kammavar
More informationLFSR Counter Implementation in CMOS VLSI
LFSR Counter Implementation in CMOS VLSI Doshi N. A., Dhobale S. B., and Kakade S. R. Abstract As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size
More informationInternational Journal of Emerging Technologies in Computational and Applied Sciences (IJETCAS)
International Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research) International Journal of Emerging Technologies in Computational
More informationLow Power High Speed Voltage Level Shifter for Sub- Threshold Operations
International Journal of Innovative Research in Electronics and Communications (IJIREC) Volume 1, Issue 5, August 2014, PP 34-41 ISSN 2349-4042 (Print) & ISSN 2349-4050 (Online) www.arcjournals.org Low
More informationClock Branch Shearing Flip Flop Based on Signal Feed Through Technique
Clock Branch Shearing Flip Flop Based on Signal Feed Through Technique Pragati Gupta 1, Dr. Rajesh Mehra 2 M.E. Scholar 1, Associate Professor Department of Electronic and Communication Engineering NITTTR,
More informationNew Single Edge Triggered Flip-Flop Design with Improved Power and Power Delay Product for Low Data Activity Applications
American-Eurasian Journal of Scientific Research 8 (1): 31-37, 013 ISSN 1818-6785 IDOSI Publications, 013 DOI: 10.589/idosi.aejsr.013.8.1.8366 New Single Edge Triggered Flip-Flop Design with Improved Power
More informationCurrent Mode Double Edge Triggered Flip Flop with Enable
Current Mode Double Edge Triggered Flip Flop with Enable Remil Anita.D 1, Jayasanthi.M 2 PG Student, Department of ECE, Karpagam College of Engineering, Coimbatore, India 1 Associate Professor, Department
More informationEfficient Architecture for Flexible Prescaler Using Multimodulo Prescaler
Efficient Architecture for Flexible Using Multimodulo G SWETHA, S YUVARAJ Abstract This paper, An Efficient Architecture for Flexible Using Multimodulo is an architecture which is designed from the proposed
More informationDUAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH LOW POWER CONSUMPTION
DUAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH LOW POWER CONSUMPTION Chien-Cheng Yu 1, 2 and Ching-Chith Tsai 1 1 Department of Electrical Engineering, National Chung-Hsing University, Taichung, Taiwan 2 Department
More informationTHE CLOCK system, which consists of the clock distribution
338 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 3, MARCH 2007 Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop Peiyi Zhao, Member, IEEE, Jason McNeely,
More information