Curriculum vitae. u likoolis ka ta ppisteaduste doktori kraadi.

Size: px
Start display at page:

Download "Curriculum vitae. u likoolis ka ta ppisteaduste doktori kraadi."

Transcription

1 Curriculum vitae Ahto Buldas su ndis 17. jaanuaril 1967 Tallinnas ja on Eesti kodanik. Abielus Riina Buldasega, kolme tu tre (Birgit 1998, Piret 2000, Bianka 2011) ja u he poja (Bent 2001) isa. Haridustee: Lo petas Tallinna 43. Keskkooli aastal Sai Tallinna Tehnikau likooli magistrikraadi aastal 1993, ning aastal 1999 samas u likoolis ka ta ppisteaduste doktori kraadi. Teenistuska ik: To o tas Tallinna Tehnikau likoolis laborandina aastail , lektorina aastail , dotsendina aastail ja professorina alates aastast Aastail to o tas Eesti TA Ku berneetika Instituudi nooremteadurina, ja teadurina aastail Alates aastast 1998 to o tab Cybernetica AS vanemteadurina. On to o tanud ka Tartu U likoolis dotsendina aastail ja professorina aastail Tunnustused: Eesti Matemaatika Seltsi poolt va lja antav Arnold Humala preemia (1995) Vabariigi Presidendi Kultuurirahastu noore teadlase preemia (2002) Valgeta he IV klassi teenetema rk (2015) Juhendatud Doktoriva itekirjad: Ahto Buldase juhendamisel on Tallinna Tehnikau likoolis (TTU ) ja Tartu U likoolis (TU ) kaitstud kokku viis doktorikraadi: 1. Aleksandr Lenin: Reliable and efficient determination of the likelihood of rational attacks (TTU 2016) 2. Margus Niitsoo: Black-box oracle separation techniques with applications in time-stamping (TU 2011) 3. Rain Ottis: A systematic Approach to offensive volunteer cyber militia (TTU 2011) 4. Aivo Kalu: Efficient semantics of parallel and serial models of attack trees (TTU 2010) 5. Jan Villemson: Size-efficient interval time stamps (TU 2002) Juhendatud magistriva itekirjad: Ahto Buldase juhendamisel on kaitstud 24 magistrikraadi: Chengxiang Wang (TTU 2017), Gvantsa Grigolia (TTU 2017), Oskar Poola (TTU 2015), Dyan Permata Sari (TTU 2014), Aleksandr Lenin (TTU 2012), Rossella Mattioli (2012), Roman Stepanenko (TTU 2012), Alexander Andrusenko (TTU 2010), Ahto Truu (TU 2010), Juri Hudolejev (TTU 2009), Richard Sassoon (TU 2009), Kristina Kallaste (TTU 2008), Lauri Ra tsep (TU 2008), Margus Niitsoo (TU 2008), Natalija Ilves (TTU 2008), Juri Gavs in (TU 2007), Liina Kamm (TU 2007), Rain Ottis (TTU 2007), Sergei S itov (TU 2007), Triinu Ma gi (TTU 2007), Aivo Kalu (TTU 2006), Meelis Selge (TTU 2006), Sven Laur (TU 2003), Uuno Puus (TU 2002) Teaduslikud huvid: Kru ptograafia, riskianalu u si meetodid, matemaatika alused.

2 Publikatsioonide nimekiri Teaduspublikatsioonid 1. Buldas, A.: Digitaalskeemide simuleerimise algebraliste meetodite analüüs. Magistritöö, Tallinna Tehnikaülikool (1993) 2. Ubar, R., Buldas, A., Paomets, P., Raik, J., Tulit, V.: A PC-based CAD System for Training Digital Test. In: Proc. EUROCHIP Workshop on VLSI Design Training, pp (1994) 3. Buldas, A.: Comparability graphs and the structure of finite graphs. Proc. Estonian Acad. Sci. Phys. Math., 45 (2/3): (1996) 4. Buldas, A., Priisalu, J.: A semi-formal method for security estimation. In: Haav, H.-M., Thalheim, B. (Eds.): Baltic DB&IS 1996, v.2, pp (1996) 5. Buldas, A.: Congruence lattice of a graph. Proc. Estonian Acad. Sci. Phys. Math., 46 (3): Buldas, A., Põldre, J.: A VLSI implementation of RSA and IDEA encryption engine. In: Proc. NORCHIP 97, pp Buldas, A., Laud, P., Lipmaa, H., Villemson, J.: Ajatempli protokollid, turvavajadused ja tehnilised nõuded. Lähteuuring DO- LU-X , Cybernetica AS. Tellitud Eesti Informaatikakeskuse poolt seoses Eesti digitaalallkirja seaduse loomisega. 8. Buldas, A.: Graphs and lattice varieties. Proc. Estonian Acad. Sci. Phys. Math., 47 (2): (1998) 9. Buldas, A., Laud, P., Lipmaa, H., Villemson, J.: Time-Stamping with binary linking schemes. In: Krawczyk, H. (Ed.): CRYP- TO 98. LNCS 1462, pp (1998) 10. Buldas, A., Laud, P.: New linking schemes for digital time-stamping. In: ICISC 98, pp.3 14, Seoul, Korea (1998) 11. Buldas, A.: An algebraic approach to the structure of graphs. Doktoritöö, Tallinna Tehnikaülikool (1999) 12. Buldas, A., Oit, M., Sarv, M.: (1999). Data security in state registers: theory and practice. In: Proc. Information Technologies and Telecommunications in the Baltic States, pp (1999) 13. Buldas, A., Lipmaa, H., Schoenmakers, B.: Optimally efficient accountable time-stamping. In: Imai, H., Zheng, Y. (Eds.): PKC LNCS 1751, pp (2000) 14. Buldas, A., Roos, M., Praust, V., Willemson, J.: On long-term validation of E-documents. Baltic IT-Review, 2 (17): (2000) 15. Buldas, A., Laud, P., Lipmaa, H.: Accountable Certificate Management using undeniable attestations. In: The 7th ACM Conference on Computer and Communication Security CCS 00, pp (2000) 16. Ansper, A., Buldas, A., Roos, M., Willemson, J.: Efficient long-term validation of digital signatures. In: Kim, K. (Eds.): PKC LNCS 1992, pp (2001) 17. Ansper, A., Buldas, A., Saarepera, M., Willemson, J.: Improving the availability of time-stamping services. In: Varadharajan, V., Mu, Y. (Eds.): ACISP LNCS 2119, pp (2001) 18. Buldas, A., Laud, P., Lipmaa, H.: Eliminating counterevidence with applications to accountable certificate management. Journal of Computer Security, 10 (3): (2002) 19. Buldas, A., Roos, M., Willemson, J.: Undeniable replies for database queries. In: Haav, H.-M., Kalja,A. (Eds.): Baltic DB&IS 2002, v.2, pp (2002) 20. Buldas, A., Saarepera, M.: Electronic signature system with small number of private keys. In: The 2nd Annual PKI Research Workshop, pp (2003) 21. Ansper, A., Buldas, A., Freudenthal, M., Willemson, J.: Scalable and efficient PKI for inter-organizational communication. In: ACSAC 2003, pp (2003) 22. Buldas, A., Freudenthal, M.: Long term archiving of electronic signatures. Baltic IT-Review, 1 (28): (2003) 23. Buldas, A., Saarepera, M.: On provably secure time-stamping schemes. In: Lee, P.J. (Ed.): ASIACRYPT LNCS 3329, pp (2004) 24. Buldas, A., Laud, P., Saarepera, M., Willemson, J.: Universally composable time-stamping schemes with audit. In: Zhou, J., Lopez, J., Deng, R.H., Bao, F. (Eds.): ISC 2005, LNCS 3650, pp (2005) 25. Buldas, A., Laur, S.: Do broken hash functions affect the security of time-stamping schemes? In: Zhou, J., Yung, M., Bao, F. (Eds.): ACNS 06, LNCS 3989, pp (2006) 26. Buldas, A., Laud, P., Priisalu, J., Saarepera, M., Willemson, J.: Rational choice of security measures via multi-parameter attack trees. In: Lopez, J. (Ed.): CRITIS LNCS 4347, pp (2006) 27. Buldas, A., Laur, S.: Knowledge-binding commitments with applications in time-stamping. In: Okamoto, T., Wang. X. (Eds.): PKC LNCS 4450, pp (2007) 28. Buldas, A., Mägi, T.: Practical security analysis of e-voting systems. In: Miyaji, A., Kikuchi, H., Rannenberg, K. (Eds.): IWSEC LNCS 4752, pp (2007)

3 29. Buldas, A., Jürgenson, A.: Does secure time-stamping imply collision-free hash functions? In: Susilo, W., Liu, J.K., Mu, Y. (Eds.): ProvSec LNCS 4784, pp (2007) 30. Buldas, A., Niitsoo, M.: Can we construct unbounded time-stamping schemes from collision-free hash functions? In: Baek, J.S., Bao, F., Chen, K., Lai, X. (Eds.): ProvSec LNCS 5324, pp (2008) 31. Buldas, A., Jürgenson, A., Niitsoo, M.: Efficiency bounds for adversary constructions in black-box reductions. In: Boyd, C., Gonzalez Nieto, J. (Eds.): ACISP LNCS 5594, pp (2009) 32. Buldas, A., Laur, S., Niitsoo, M.: Oracle separation in the non-uniform model. In: Pieprzyk, J., Zhang, F. (Eds.): ProvSec LNCS 5848, pp (2009) 33. Buldas, A., Niitsoo, M.: Optimally tight security proofs for hash-then-publish time-stamping. In: Steinfeld, R., Hawkes, P. (Eds.): ACISP LNCS 6168, pp (2010) 34. Buldas, A., Stepanenko, R.: Upper bounds for adversaries utility in attack trees. In: Grossklags, J., Walrand, J. (Eds.): Game- Sec LNCS 7638, pp (2012) 35. Buldas, A., Niitsoo, M.: Black-box separations and their adaptability to the non-uniform model. In: Boyd, C., Simpson, L. (Eds.): ACISP LNCS 7959, pp (2013) 36. Buldas, A., Laanoja, R.: Security proofs for hash tree time-stamping using hash functions with small output size. In: Boyd, C., Simpson, L. (Eds.): ACISP 2013, LNCS 7959, pp (2013) 37. Buldas, A., Andres Kroonmaa, Laanoja, R.: Keyless signatures infrastructure: How to build global distributed hash-trees. In: Riis Nielson, H., Gollmann, D. (Eds.): NordSec LNCS 8208, pp (2013) 38. Ansper, A., Buldas, A., Freudenthal, M., Willemson, J.: High-performance qualified digital signatures for X-Road. In: Riis Nielson, H., Gollmann, D. (Eds.): NordSec LNCS 8208, pp (2013) 39. Ansper, A., Buldas, A., Freudenthal, M., Willemson, J.: Protecting a federated database infrastructure against denial-of-service attacks. In: Luiijf, E., Hartel, P. (Eds.): CRITIS LNCS 8328, pp (2013) 40. Buldas, A., Lenin, A.: New efficient utility upper bounds for the fully adaptive model of attack trees. In: Das, S.K., Nita-Rotaru, C., Kantarcioglu, M. (Eds.): GameSec LNCS 8252, pp (2013) 41. Buldas, A., Laanoja, R., Laud, P., Truu, A.: Bounded pre-image awareness and the security of hash-tree keyless signatures. In: Chow, S.S.M., Liu, J.K., Hui, L.C.K., Yiu, S.M. (Eds.): Provsec LNCS 8782, pp (2014) 42. Buldas, A., Lenin, A.: Limiting adversarial budget in quantitative security analysis. In: Poovendran, R., Saad, W. (Eds.): GameSec LNCS 8840, pp (2014) 43. Buldas, A., Truu, A., Laanoja, R., Gerhards, R.: Efficient record-level keyless signatures for audit logs. In: Bernsmed, K., Fisher-Hübner, S. (Eds.): NordSec LNCS 8788, pp (2014) 44. Buldas, A., Heero, K., Laud, P., Talviste, R., Willemson, J.: Cryptographic algorithms lifecycle report Information System Authority. Doc. A June 22 (2016) 45. Buldas, A., Laanoja, R., Truu, A.: Keyless signature infrastructure and PKI: hash-tree signatures in pre- and post-quantum world. International Journal of Services Technology and Management (IJSTM), 23 (1/2) (2017) 46. Buldas, A., Saarepera, M.: Are the current system engineering practices sufficient to meet cyber crime? In: Tryfonas, T. (Ed.): HAS LNCS 10292, pp (2017) 47. Buldas, A., Geihs, M., Buchmann, J.: Long-term secure commitments via extractable-binding commitments. In: Pieprzyk, J., Suriadi, S. (Eds.): ACISP LNCS 10343, pp (2017) 48. Buldas, A., Kalu, A., Laud, P., Oruaas, M.: Server-supported RSA signatures for mobile devices. Foley, S.N., Gollmann, D., Snekkenes, E. (Eds.): ESORICS 2017, Part I. LNCS 10492, pp (2017) 49. Buldas, A., Lenin, A., Willemson, J., Charnamord, A.: Simple infeasibility certificates for attack trees. In: Obana, S., Chida, K. (Eds.): IWSEC LNCS 10418, pp (2017) 50. Buldas, A., Geihs, M., Buchmann, J.: Long-term secure time-stamping using preimage-aware hash functions. In: Okamoto, T., Yu, Y. (Eds.): ProvSec LNCS pp (2017) 51. Buldas, A., Laanoja, R., Truu, A.: A server-assisted hash-based signature scheme. In: Lipmaa, H., Mitrokotsa, A., Matulevičius, R. (Eds.): NordSec LNCS 10674, pp (2017) Patendid 52. US Patent # : Buldas, A., Laanoja, R., Truu, A.: System and method for sequential data signatures. Filed: April 11, Date of Patent: April 4, Assignee: GUARDTIME IP HOLDINGS, LTD. 53. US Patent # : Buldas, A., Truu, A., Andres Kroonmaa: Document verification with ID augmentation. Filed: August 5, Date of Patent: October 18, Assignee: GUARDTIME IP HOLDINGS, LTD. 54. US Patent # : Michael Gault, Laanoja, R., Buldas, A., Martin Ruubel, Peter Rajnak, David F. A. Piesse, Jian Tan, Jeffrey Pearce: System and method for field-verifiable record authentication. Filed: August 14, Date of Patent: February 23, Assignee: GUARDTIME IP HOLDINGS, LTD.

4 55. US Patent # : Michael Gault, Truu, A., Buldas, A., Martin Ruubel, Jeffrey Pearce: Non-deterministic time systems and methods. Filed: December 2, Date of Patent: November 3, Assignee: GUARDTIME IP HOLDINGS, LTD. 56. US Patent # : Buldas, A., Märt Saarepera: Document verification with distributed calendar infrastructure. Filed: April 30, Date of Patent: September 1, Assignee: GUARDTIME IP HOLDINGS, LTD. 57. US Patent # : Buldas, A., Andres Kroonmaa, Märt Saarepera: System and method for generating keyless digital multisignatures. Filed: June 20, Date of Patent: October 28, Assignee: GUARDTIME IP HOLDINGS, LTD. 58. US Patent # : Buldas, A., Märt Saarepera: Document verification with distributed calendar infrastructure. Filed: September 24, Date of Patent: May 6, Assignee: GUARDTIME IP HOLDINGS, LTD. 59. US Patent # : Buldas, A., Saarepera, M.: System and method for generating a digital certificate. Filed: January 29, Date of Patent: January 1, Assignee: GUARDTIME IP HOLDINGS, LTD. 60. US Patent # : Saarepera, M., Buldas, A.: System and method for generating a digital certificate. Filed: January 29, Date of Patent: November 13, Assignee: GUARDTIME IP HOLDINGS, LTD. 61. US Patent # : Buldas, A., Saarepera, M.: System and method for generating a digital certificate. Filed: December 7, Date of Patent: April 13, Assignee: GUARDTIME AS Patendiavaldused 62. US Patent Application # : Andres Kroonmaa, Buldas, A., Jeffrey Pearce: Redundant Fail-Safe Synchronization in a Data Authentication Infrastructure. Filed: February 27, Publication date: September 1, Applicant: GUARDTIME IP HOLDINGS, LTD. 63. US Patent Application # : Buldas, A., Märt Saarepera: Document Verification With Distributed Calendar Infrastructure. Filed: September 1, Publication date: January 28, Applicant: GUARDTIME IP HOLDINGS, LTD. 64. US Patent Application # : Buldas, A., Laanoja, R., Truu, A.: System and Method for Sequential Data Signatures. Filed: April 11, Publication date: October 15, Applicant: GUARDTIME IP HOLDINGS, LTD. 65. US Patent Application # : Michael Gault, Truu, A., Buldas, A., Martin Ruubel, Jeffrey Pearce: Non-Deterministic Time Systems and Methods. Filed: December 2, Publication date: June 4, Applicant: GUARDTIME IP HOL- DINGS, LTD. 66. US Patent Application # : Michael Gault, Laanoja, R., Buldas, A., Martin Ruubel, Peter Rajnak, David F. A. Piesse: System and Method for Field-Verifiable Record Authentication. Filed: August 14, Publication date: February 19, Applicant: GUARDTIME IP HOLDINGS, LTD. 67. US Patent Application # : Buldas, A., Truu, A., Andres Kroonmaa: Document Verification With Id Augmentation. Filed: August 5, Publication date: February 5, Applicant: GUARDTIME IP HOLDINGS, LTD. 68. US Patent Application # : Buldas, A., Märt Saarepera: Document Verification With Distributed Calendar Infrastructure. Filed: April 30, Publication date: September 18, Applicant: GUARDTIME IP HOLDINGS, LTD. 69. US Patent Application # : Buldas, A., Truu, A.: Verification System and Method with Extra Security for Lower- Entropy Input Records. Filed: May 24, Publication date: August 28, Applicant: GUARDTIME IP HOLDINGS, LTD. 70. US Patent Application # : Buldas, A., Saarepera, M.: Document Verification With Distributed Calendar Infrastructure. Filed: September 24, Publication date: October 17, Applicant: GUARDTIME IP HOLDINGS, LTD. 71. US Patent Application # : Buldas, A., Kroonmaa, A., Saarepera, M.: System and method for generating keyless digital multi-signatures. Filed: June 20, Publication date: December 20, Applicant: GUARDTIME IP HOLDINGS, LTD. 72. US Patent Application # : Saarepera, M., Buldas, A.: System and method for generating a digital certificate. Filed: January 29, Publication date: August 5, Applicant: GUARDTIME AS 73. US Patent Application # : Saarepera, M., Buldas, A.: System and method for generating a digital certificate. Filed: December 7, Publication date: June 23, US Patent Application # : Saarepera, M., Buldas, A.: System and method for renewing and extending digitally signed certificates. Filed: January 8, Publication date: September 30, US Patent Application WO A3: Buldas, A., Saarepera, M.: System and method for creating electronic signatures. Priority date: Jan 31, Filing date: Jan 30, Publication date: Dec 29, US Patent Application # : Ansper, A., Buldas, A., Roos, M., Villemson, J.: Method and apparatus for validating a digital signature. Filed: February 9, Publication date: October 18, US Patent Application WO A1: Buldas, A., Laud, P., Lipmaa, H., Villemson, J.: Time-stamping with binary linking schemes. Priority date: Aug 18. Filing date: Aug 18, , Publication date: Mar 2, 2000

5 Populaarteaduslikud kirjutised 78. Buldas, A.: Krüptoloogia. Miks ja kuidas? Arvutimaailm, 3: (1994) 79. Buldas, A., Lakspere, E., Priisalu, J.: Mikroarvuti plastkaardis. Arvutimaailm, 4: (1994) 80. Buldas, A.: Algoritmid ja diagonaalsed tõestused. Arvutustehnika ja andmetöötlus, 1: 5 10 (1995) 81. Buldas, A.: Graafid ja järjestused. Arvutustehnika ja andmetöötlus, 2: 2 8 (1995) 82. Buldas, A.: Sissejuhatus matroidide teooriasse. Arvutustehnika ja andmetöötlus, 3: 2 5 (1995) 83. Buldas, A.: Goodsteini teoreemist. Arvutustehnika ja andmetöötlus, 4: 2 6 (1995) 84. Buldas, A.: Mis on p-aadilised arvud? Arvutustehnika ja andmetöötlus, 9: 2 8 (1995) 85. Buldas, A.: Elektrondokumendid tõendusmaterjalina. Arvutimaailm, 8: Buldas, A., Lipmaa, H.: Ajatemplid digitaaldokumentidel. Arvutimaailm, 2: (1998) 87. Buldas, A.: Allkirjad elektroonilistel dokumentidel: vääramatu tõenduse algoritmidest. Arvutustehnika ja andmetöötlus, 6: (2000) 88. Buldas, A.: Teadusest, ärist ja impeeriumi pärandusest. Arvutustehnika ja andmetöötlus, 4: 5 8 (2001) Õpikirjandus 89. Hanson, V., Buldas, A., Martens, T., Lipmaa, H., Ansper, A., Tulit, V.: Infosüsteemide turve I. Turvarisk. Küberneetika AS 90. Hanson, V., Buldas, A., Martens, T., Lipmaa, H., Ansper, A., Tulit, V.: Infosüsteemide turve II. Turbetehnoloogia. Küberneetika AS (1998) 91. Buldas, A., Laud, P., Willemson, J.: Graafid. Tartu: Tartu Ülikooli Kirjastus (2008) 92. Veldre, A., Hanson, V., Laur, M., Buldas,A., Krasnosjolov, J.: Andmekaitse ja infoturbe seletussõnastik: AKIT (2011)

Fast thumbnail generation for MPEG video by using a multiple-symbol lookup table

Fast thumbnail generation for MPEG video by using a multiple-symbol lookup table 48 3, 376 March 29 Fast thumbnail generation for MPEG video by using a multiple-symbol lookup table Myounghoon Kim Hoonjae Lee Ja-Cheon Yoon Korea University Department of Electronics and Computer Engineering,

More information

An Efficient Reduction of Area in Multistandard Transform Core

An Efficient Reduction of Area in Multistandard Transform Core An Efficient Reduction of Area in Multistandard Transform Core A. Shanmuga Priya 1, Dr. T. K. Shanthi 2 1 PG scholar, Applied Electronics, Department of ECE, 2 Assosiate Professor, Department of ECE Thanthai

More information

COPY RIGHT. To Secure Your Paper As Per UGC Guidelines We Are Providing A Electronic Bar Code

COPY RIGHT. To Secure Your Paper As Per UGC Guidelines We Are Providing A Electronic Bar Code COPY RIGHT 2018IJIEMR.Personal use of this material is permitted. Permission from IJIEMR must be obtained for all other uses, in any current or future media, including reprinting/republishing this material

More information

Automatic Commercial Monitoring for TV Broadcasting Using Audio Fingerprinting

Automatic Commercial Monitoring for TV Broadcasting Using Audio Fingerprinting Automatic Commercial Monitoring for TV Broadcasting Using Audio Fingerprinting Dalwon Jang 1, Seungjae Lee 2, Jun Seok Lee 2, Minho Jin 1, Jin S. Seo 2, Sunil Lee 1 and Chang D. Yoo 1 1 Korea Advanced

More information

Color Image Compression Using Colorization Based On Coding Technique

Color Image Compression Using Colorization Based On Coding Technique Color Image Compression Using Colorization Based On Coding Technique D.P.Kawade 1, Prof. S.N.Rawat 2 1,2 Department of Electronics and Telecommunication, Bhivarabai Sawant Institute of Technology and Research

More information

Analysis of Visual Similarity in News Videos with Robust and Memory-Efficient Image Retrieval

Analysis of Visual Similarity in News Videos with Robust and Memory-Efficient Image Retrieval Analysis of Visual Similarity in News Videos with Robust and Memory-Efficient Image Retrieval David Chen, Peter Vajda, Sam Tsai, Maryam Daneshi, Matt Yu, Huizhong Chen, Andre Araujo, Bernd Girod Image,

More information

TERRESTRIAL broadcasting of digital television (DTV)

TERRESTRIAL broadcasting of digital television (DTV) IEEE TRANSACTIONS ON BROADCASTING, VOL 51, NO 1, MARCH 2005 133 Fast Initialization of Equalizers for VSB-Based DTV Transceivers in Multipath Channel Jong-Moon Kim and Yong-Hwan Lee Abstract This paper

More information

FAST SPATIAL AND TEMPORAL CORRELATION-BASED REFERENCE PICTURE SELECTION

FAST SPATIAL AND TEMPORAL CORRELATION-BASED REFERENCE PICTURE SELECTION FAST SPATIAL AND TEMPORAL CORRELATION-BASED REFERENCE PICTURE SELECTION 1 YONGTAE KIM, 2 JAE-GON KIM, and 3 HAECHUL CHOI 1, 3 Hanbat National University, Department of Multimedia Engineering 2 Korea Aerospace

More information

Pseudorandom bit Generators for Secure Broadcasting Systems

Pseudorandom bit Generators for Secure Broadcasting Systems +00? IE.Nfejb~lV 4 Pseudorandom bit Generators for Secure Broadcasting Systems Chung-Huang Yang m Computer & Communication Research Laboratories Industrial Technology Research Institute Chutung, Hsinchu

More information

Figure 1.LFSR Architecture ( ) Table 1. Shows the operation for x 3 +x+1 polynomial.

Figure 1.LFSR Architecture ( ) Table 1. Shows the operation for x 3 +x+1 polynomial. High-speed Parallel Architecture and Pipelining for LFSR Vinod Mukati PG (M.TECH. VLSI engineering) student, SGVU Jaipur (Rajasthan). Vinodmukati9@gmail.com Abstract Linear feedback shift register plays

More information

Fast MBAFF/PAFF Motion Estimation and Mode Decision Scheme for H.264

Fast MBAFF/PAFF Motion Estimation and Mode Decision Scheme for H.264 Fast MBAFF/PAFF Motion Estimation and Mode Decision Scheme for H.264 Ju-Heon Seo, Sang-Mi Kim, Jong-Ki Han, Nonmember Abstract-- In the H.264, MBAFF (Macroblock adaptive frame/field) and PAFF (Picture

More information

Implementation of CRC and Viterbi algorithm on FPGA

Implementation of CRC and Viterbi algorithm on FPGA Implementation of CRC and Viterbi algorithm on FPGA S. V. Viraktamath 1, Akshata Kotihal 2, Girish V. Attimarad 3 1 Faculty, 2 Student, Dept of ECE, SDMCET, Dharwad, 3 HOD Department of E&CE, Dayanand

More information

Digital holographic security system based on multiple biometrics

Digital holographic security system based on multiple biometrics Digital holographic security system based on multiple biometrics ALOKA SINHA AND NIRMALA SAINI Department of Physics, Indian Institute of Technology Delhi Indian Institute of Technology Delhi, Hauz Khas,

More information

ITU-T Y Functional framework and capabilities of the Internet of things

ITU-T Y Functional framework and capabilities of the Internet of things I n t e r n a t i o n a l T e l e c o m m u n i c a t i o n U n i o n ITU-T Y.2068 TELECOMMUNICATION STANDARDIZATION SECTOR OF ITU (03/2015) SERIES Y: GLOBAL INFORMATION INFRASTRUCTURE, INTERNET PROTOCOL

More information

PERCEPTUAL QUALITY COMPARISON BETWEEN SINGLE-LAYER AND SCALABLE VIDEOS AT THE SAME SPATIAL, TEMPORAL AND AMPLITUDE RESOLUTIONS. Yuanyi Xue, Yao Wang

PERCEPTUAL QUALITY COMPARISON BETWEEN SINGLE-LAYER AND SCALABLE VIDEOS AT THE SAME SPATIAL, TEMPORAL AND AMPLITUDE RESOLUTIONS. Yuanyi Xue, Yao Wang PERCEPTUAL QUALITY COMPARISON BETWEEN SINGLE-LAYER AND SCALABLE VIDEOS AT THE SAME SPATIAL, TEMPORAL AND AMPLITUDE RESOLUTIONS Yuanyi Xue, Yao Wang Department of Electrical and Computer Engineering Polytechnic

More information

Design and Implementation of an LED Mood Lighting System Using Personalized Color Sequence Generation

Design and Implementation of an LED Mood Lighting System Using Personalized Color Sequence Generation KSII TRANSACTIONS ON INTERNET AND INFORMATION SYSTEMS VOL. 6, NO. 12, Dec 2012 3182 Copyright c 2012 KSII Design and Implementation of an LED Mood Lighting System Using Personalized Color Sequence Generation

More information

Chapter 5: Synchronous Sequential Logic

Chapter 5: Synchronous Sequential Logic Chapter 5: Synchronous Sequential Logic NCNU_2016_DD_5_1 Digital systems may contain memory for storing information. Combinational circuits contains no memory elements the outputs depends only on the inputs

More information

ITU-T Y.4552/Y.2078 (02/2016) Application support models of the Internet of things

ITU-T Y.4552/Y.2078 (02/2016) Application support models of the Internet of things I n t e r n a t i o n a l T e l e c o m m u n i c a t i o n U n i o n ITU-T TELECOMMUNICATION STANDARDIZATION SECTOR OF ITU Y.4552/Y.2078 (02/2016) SERIES Y: GLOBAL INFORMATION INFRASTRUCTURE, INTERNET

More information

Separating Semantic and Circular Security for Symmetric Key Bit Encryption from LWE. Rishab Goyal Venkata Koppula Brent Waters

Separating Semantic and Circular Security for Symmetric Key Bit Encryption from LWE. Rishab Goyal Venkata Koppula Brent Waters Separating Semantic and Circular Security for Symmetric Key Bit Encryption from LWE Rishab Goyal Venkata Koppula Brent Waters n-circular Security [CamenischLysyanskya01] PK 1 PK 1...... PK n PK n Enc PKn

More information

Optimized Color Based Compression

Optimized Color Based Compression Optimized Color Based Compression 1 K.P.SONIA FENCY, 2 C.FELSY 1 PG Student, Department Of Computer Science Ponjesly College Of Engineering Nagercoil,Tamilnadu, India 2 Asst. Professor, Department Of Computer

More information

EXPLORING THE USE OF ENF FOR MULTIMEDIA SYNCHRONIZATION

EXPLORING THE USE OF ENF FOR MULTIMEDIA SYNCHRONIZATION EXPLORING THE USE OF ENF FOR MULTIMEDIA SYNCHRONIZATION Hui Su, Adi Hajj-Ahmad, Min Wu, and Douglas W. Oard {hsu, adiha, minwu, oard}@umd.edu University of Maryland, College Park ABSTRACT The electric

More information

UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD. ITRON, INC., Petitioner. CERTIFIED MEASUREMENT, LLC, Patent Owner

UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD. ITRON, INC., Petitioner. CERTIFIED MEASUREMENT, LLC, Patent Owner UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD ITRON, INC., Petitioner v. CERTIFIED MEASUREMENT, LLC, Patent Owner Case: IPR2015- U.S. Patent No. 6,289,453 PETITION

More information

VLSI Based Minimized Composite S-Box and Inverse Mix Column for AES Encryption and Decryption

VLSI Based Minimized Composite S-Box and Inverse Mix Column for AES Encryption and Decryption VLSI Based Minimized Composite S-Bo and Inverse Mi Column for AES Encryption and Decryption 1 J. Balamurugan, 2 Dr. E. Logashanmugam 1 Research scholar, 2 Professor and Head, 1 St. Peter s University,

More information

Adaptive Key Frame Selection for Efficient Video Coding

Adaptive Key Frame Selection for Efficient Video Coding Adaptive Key Frame Selection for Efficient Video Coding Jaebum Jun, Sunyoung Lee, Zanming He, Myungjung Lee, and Euee S. Jang Digital Media Lab., Hanyang University 17 Haengdang-dong, Seongdong-gu, Seoul,

More information

Bridging the Gap Between CBR and VBR for H264 Standard

Bridging the Gap Between CBR and VBR for H264 Standard Bridging the Gap Between CBR and VBR for H264 Standard Othon Kamariotis Abstract This paper provides a flexible way of controlling Variable-Bit-Rate (VBR) of compressed digital video, applicable to the

More information

VLSI Technology used in Auto-Scan Delay Testing Design For Bench Mark Circuits

VLSI Technology used in Auto-Scan Delay Testing Design For Bench Mark Circuits VLSI Technology used in Auto-Scan Delay Testing Design For Bench Mark Circuits N.Brindha, A.Kaleel Rahuman ABSTRACT: Auto scan, a design for testability (DFT) technique for synchronous sequential circuits.

More information

A Pseudorandom Binary Generator Based on Chaotic Linear Feedback Shift Register

A Pseudorandom Binary Generator Based on Chaotic Linear Feedback Shift Register A Pseudorandom Binary Generator Based on Chaotic Linear Feedback Shift Register Saad Muhi Falih Department of Computer Technical Engineering Islamic University College Al Najaf al Ashraf, Iraq saadmuheyfalh@gmail.com

More information

CRYPTOGRAPHY. Sharafat Ibn Mollah Mosharraf TOUCH-N-PASS EXAM CRAM GUIDE SERIES. Special Edition for CSEDU. Students CSE, DU )

CRYPTOGRAPHY. Sharafat Ibn Mollah Mosharraf TOUCH-N-PASS EXAM CRAM GUIDE SERIES. Special Edition for CSEDU. Students CSE, DU ) Special Edition for CSEDU Students TOUCH-N-PASS EXAM CRAM GUIDE SERIES CRYPTOGRAPHY Prepared By Sharafat Ibn Mollah Mosharraf CSE, DU 12 th Batch (2005 2005-2006 2006) Table of Contents CHAPTER 1: INTRODUCTION

More information

Tel: Fax: Website: ACOSJ-P Java Card PBOC 3.0 A Product Presentation

Tel: Fax: Website:  ACOSJ-P Java Card PBOC 3.0 A Product Presentation Tel: +852-2796-7873 Fax: +852-2796-1286 E-mail: info@acs.com.hk Website: www.acs.com.hk ACOSJ-P Java Card PBOC 3.0 A Product Presentation Rundown 1. Product Overview 2. What is PBOC 3.0? 3. What is DC?

More information

New Approach to Multi-Modal Multi-View Video Coding

New Approach to Multi-Modal Multi-View Video Coding Chinese Journal of Electronics Vol.18, No.2, Apr. 2009 New Approach to Multi-Modal Multi-View Video Coding ZHANG Yun 1,4, YU Mei 2,3 and JIANG Gangyi 1,2 (1.Institute of Computing Technology, Chinese Academic

More information

A New Proposed Design of a Stream Cipher Algorithm: Modified Grain - 128

A New Proposed Design of a Stream Cipher Algorithm: Modified Grain - 128 International Journal of Computer and Information Technology (ISSN: 2279 764) Volume 3 Issue 5, September 214 A New Proposed Design of a Stream Cipher Algorithm: Modified Grain - 128 Norul Hidayah Lot

More information

Test Data Compression for System-on-a-Chip Using Golomb Codes 1

Test Data Compression for System-on-a-Chip Using Golomb Codes 1 Test Data Compression for System-on-a-Chip Using Golomb Codes 1 Anshuman Chandra and Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University Durham, NC 27708 {achandra,

More information

Line-Adaptive Color Transforms for Lossless Frame Memory Compression

Line-Adaptive Color Transforms for Lossless Frame Memory Compression Line-Adaptive Color Transforms for Lossless Frame Memory Compression Joungeun Bae 1 and Hoon Yoo 2 * 1 Department of Computer Science, SangMyung University, Jongno-gu, Seoul, South Korea. 2 Full Professor,

More information

REDUCING DYNAMIC POWER BY PULSED LATCH AND MULTIPLE PULSE GENERATOR IN CLOCKTREE

REDUCING DYNAMIC POWER BY PULSED LATCH AND MULTIPLE PULSE GENERATOR IN CLOCKTREE Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 3, Issue. 5, May 2014, pg.210

More information

Enhancing Performance in Multiple Execution Unit Architecture using Tomasulo Algorithm

Enhancing Performance in Multiple Execution Unit Architecture using Tomasulo Algorithm Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 6.017 IJCSMC,

More information

Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath

Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and

More information

LUT OPTIMIZATION USING COMBINED APC-OMS TECHNIQUE

LUT OPTIMIZATION USING COMBINED APC-OMS TECHNIQUE LUT OPTIMIZATION USING COMBINED APC-OMS TECHNIQUE S.Basi Reddy* 1, K.Sreenivasa Rao 2 1 M.Tech Student, VLSI System Design, Annamacharya Institute of Technology & Sciences (Autonomous), Rajampet (A.P),

More information

Design and Implementation of Partial Reconfigurable Fir Filter Using Distributed Arithmetic Architecture

Design and Implementation of Partial Reconfigurable Fir Filter Using Distributed Arithmetic Architecture Design and Implementation of Partial Reconfigurable Fir Filter Using Distributed Arithmetic Architecture Vinaykumar Bagali 1, Deepika S Karishankari 2 1 Asst Prof, Electrical and Electronics Dept, BLDEA

More information

On the design of turbo codes with convolutional interleavers

On the design of turbo codes with convolutional interleavers University of Wollongong Research Online University of Wollongong Thesis Collection 1954-2016 University of Wollongong Thesis Collections 2005 On the design of turbo codes with convolutional interleavers

More information

Logic Design for Single On-Chip Test Clock Generation for N Clock Domain - Impact on SOC Area and Test Quality

Logic Design for Single On-Chip Test Clock Generation for N Clock Domain - Impact on SOC Area and Test Quality and Communication Technology (IJRECT 6) Vol. 3, Issue 3 July - Sept. 6 ISSN : 38-965 (Online) ISSN : 39-33 (Print) Logic Design for Single On-Chip Test Clock Generation for N Clock Domain - Impact on SOC

More information

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203

More information

E-Learning Tools for Teaching Self-Test of Digital Electronics

E-Learning Tools for Teaching Self-Test of Digital Electronics E-Learning Tools for Teaching Self-Test of Digital Electronics A. Jutman 1, E. Gramatova 2, T. Pikula 2, R. Ubar 1 1 Tallinn University of Technology, Raja 15, 12618 Tallinn, Estonia 2 Institute of Informatics,

More information

A High- Speed LFSR Design by the Application of Sample Period Reduction Technique for BCH Encoder

A High- Speed LFSR Design by the Application of Sample Period Reduction Technique for BCH Encoder IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) ISSN: 239 42, ISBN No. : 239 497 Volume, Issue 5 (Jan. - Feb 23), PP 7-24 A High- Speed LFSR Design by the Application of Sample Period Reduction

More information

Combinational / Sequential Logic

Combinational / Sequential Logic Digital Circuit Design and Language Combinational / Sequential Logic Chang, Ik Joon Kyunghee University Combinational Logic + The outputs are determined by the present inputs + Consist of input/output

More information

International Journal of Advance Engineering and Research Development REMOTE VOTING MACHINE

International Journal of Advance Engineering and Research Development REMOTE VOTING MACHINE Scientific Journal of Impact Factor (SJIF): 5.71 International Journal of Advance Engineering and Research Development Volume 5, Issue 05, May -2018 REMOTE VOTING MACHINE C.V.Rane 1, Aarti Devkar 2, Yogeshwari

More information

Chapter 3 Unit Combinational

Chapter 3 Unit Combinational EE 200: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Chapter 3 Unit Combinational 5 Registers Logic and Design Counters Part Implementation Technology

More information

Adding Analog and Mixed Signal Concerns to a Digital VLSI Course

Adding Analog and Mixed Signal Concerns to a Digital VLSI Course Session Number 1532 Adding Analog and Mixed Signal Concerns to a Digital VLSI Course John A. Nestor and David A. Rich Department of Electrical and Computer Engineering Lafayette College Abstract This paper

More information

DESIGN AND SIMULATION OF A CIRCUIT TO PREDICT AND COMPENSATE PERFORMANCE VARIABILITY IN SUBMICRON CIRCUIT

DESIGN AND SIMULATION OF A CIRCUIT TO PREDICT AND COMPENSATE PERFORMANCE VARIABILITY IN SUBMICRON CIRCUIT DESIGN AND SIMULATION OF A CIRCUIT TO PREDICT AND COMPENSATE PERFORMANCE VARIABILITY IN SUBMICRON CIRCUIT Sripriya. B.R, Student of M.tech, Dept of ECE, SJB Institute of Technology, Bangalore Dr. Nataraj.

More information

A parallel HEVC encoder scheme based on Multi-core platform Shu Jun1,2,3,a, Hu Dong1,2,3,b

A parallel HEVC encoder scheme based on Multi-core platform Shu Jun1,2,3,a, Hu Dong1,2,3,b 4th National Conference on Electrical, Electronics and Computer Engineering (NCEECE 2015) A parallel HEVC encoder scheme based on Multi-core platform Shu Jun1,2,3,a, Hu Dong1,2,3,b 1 Education Ministry

More information

How to Predict the Output of a Hardware Random Number Generator

How to Predict the Output of a Hardware Random Number Generator How to Predict the Output of a Hardware Random Number Generator Markus Dichtl Siemens AG, Corporate Technology Markus.Dichtl@siemens.com Abstract. A hardware random number generator was described at CHES

More information

Melody Retrieval On The Web

Melody Retrieval On The Web Melody Retrieval On The Web Thesis proposal for the degree of Master of Science at the Massachusetts Institute of Technology M.I.T Media Laboratory Fall 2000 Thesis supervisor: Barry Vercoe Professor,

More information

VJ 6040 UHF Chip Antenna for Mobile Devices

VJ 6040 UHF Chip Antenna for Mobile Devices End of Life Last Available Purchase Date: 2-Aug-217 VJ 64 UHF Chip Antenna for Mobile Devices VJ 64 The company s products are covered by one or more of the following: WO5262 (A1), US2833 (A1), US283575

More information

Advanced cryptography - Project

Advanced cryptography - Project Advanced cryptography - Project Vanessa Vitse 2013 2014 Master SCCI Vanessa VITSE (Institut Fourier) Advanced cryptography Master SCCI 1 / 12 Assignment Survey of some research topics related to elliptic

More information

UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram

UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational

More information

[Dharani*, 4.(8): August, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785

[Dharani*, 4.(8): August, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785 IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY IMPLEMENTATION OF ADDRESS GENERATOR FOR WiMAX DEINTERLEAVER ON FPGA T. Dharani*, C.Manikanta * M. Tech scholar in VLSI System

More information

Scopus. Advanced research tips and tricks. Massimiliano Bearzot Customer Consultant Elsevier

Scopus. Advanced research tips and tricks. Massimiliano Bearzot Customer Consultant Elsevier 1 Scopus Advanced research tips and tricks Massimiliano Bearzot Customer Consultant Elsevier m.bearzot@elsevier.com October 12 th, Universitá degli Studi di Genova Agenda TITLE OF PRESENTATION 2 What content

More information

The Design of Efficient Viterbi Decoder and Realization by FPGA

The Design of Efficient Viterbi Decoder and Realization by FPGA Modern Applied Science; Vol. 6, No. 11; 212 ISSN 1913-1844 E-ISSN 1913-1852 Published by Canadian Center of Science and Education The Design of Efficient Viterbi Decoder and Realization by FPGA Liu Yanyan

More information

University of Bristol - Explore Bristol Research. Peer reviewed version. Link to published version (if available): /ICASSP.2016.

University of Bristol - Explore Bristol Research. Peer reviewed version. Link to published version (if available): /ICASSP.2016. Hosking, B., Agrafiotis, D., Bull, D., & Easton, N. (2016). An adaptive resolution rate control method for intra coding in HEVC. In 2016 IEEE International Conference on Acoustics, Speech and Signal Processing

More information

Ultra-lightweight 8-bit Multiplicative Inverse Based S-box Using LFSR

Ultra-lightweight 8-bit Multiplicative Inverse Based S-box Using LFSR Ultra-lightweight -bit Multiplicative Inverse Based S-box Using LFSR Sourav Das Alcatel-Lucent India Ltd Email:sourav10101976@gmail.com Abstract. Most of the lightweight block ciphers are nibble-oriented

More information

Design of Polar List Decoder using 2-Bit SC Decoding Algorithm V Priya 1 M Parimaladevi 2

Design of Polar List Decoder using 2-Bit SC Decoding Algorithm V Priya 1 M Parimaladevi 2 IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 03, 2015 ISSN (online): 2321-0613 V Priya 1 M Parimaladevi 2 1 Master of Engineering 2 Assistant Professor 1,2 Department

More information

Selective Intra Prediction Mode Decision for H.264/AVC Encoders

Selective Intra Prediction Mode Decision for H.264/AVC Encoders Selective Intra Prediction Mode Decision for H.264/AVC Encoders Jun Sung Park, and Hyo Jung Song Abstract H.264/AVC offers a considerably higher improvement in coding efficiency compared to other compression

More information

FPGA Based Implementation of Convolutional Encoder- Viterbi Decoder Using Multiple Booting Technique

FPGA Based Implementation of Convolutional Encoder- Viterbi Decoder Using Multiple Booting Technique FPGA Based Implementation of Convolutional Encoder- Viterbi Decoder Using Multiple Booting Technique Dr. Dhafir A. Alneema (1) Yahya Taher Qassim (2) Lecturer Assistant Lecturer Computer Engineering Dept.

More information

THE USE OF forward error correction (FEC) in optical networks

THE USE OF forward error correction (FEC) in optical networks IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 8, AUGUST 2005 461 A High-Speed Low-Complexity Reed Solomon Decoder for Optical Communications Hanho Lee, Member, IEEE Abstract

More information

Ensemble LUT classification for degraded document enhancement

Ensemble LUT classification for degraded document enhancement Ensemble LUT classification for degraded document enhancement Tayo Obafemi-Ajayi, Gady Agam, Ophir Frieder Department of Computer Science, Illinois Institute of Technology, Chicago, IL 60616 ABSTRACT The

More information

FRAME RATE BLOCK SELECTION APPROACH BASED DIGITAL WATER MARKING FOR EFFICIENT VIDEO AUTHENTICATION USING NETWORK CONDITIONS

FRAME RATE BLOCK SELECTION APPROACH BASED DIGITAL WATER MARKING FOR EFFICIENT VIDEO AUTHENTICATION USING NETWORK CONDITIONS FRAME RATE BLOCK SELECTION APPROACH BASED DIGITAL WATER MARKING FOR EFFICIENT VIDEO AUTHENTICATION USING NETWORK CONDITIONS A. Kirthika 1 and A. Senthilkumar 2 1 Department of Electronics and Communication

More information

Module 8 VIDEO CODING STANDARDS. Version 2 ECE IIT, Kharagpur

Module 8 VIDEO CODING STANDARDS. Version 2 ECE IIT, Kharagpur Module 8 VIDEO CODING STANDARDS Lesson 24 MPEG-2 Standards Lesson Objectives At the end of this lesson, the students should be able to: 1. State the basic objectives of MPEG-2 standard. 2. Enlist the profiles

More information

The Design of Teaching Experiment System Based on Virtual Instrument Technology. Dayong Huo

The Design of Teaching Experiment System Based on Virtual Instrument Technology. Dayong Huo 3rd International Conference on Management, Education, Information and Control (MEICI 2015) The Design of Teaching Experiment System Based on Virtual Instrument Technology Dayong Huo Department of Physics,

More information

PROCEEDINGS OF SPIE. Event: SPIE Defense, Security, and Sensing, 2013, Baltimore, Maryland, United States

PROCEEDINGS OF SPIE. Event: SPIE Defense, Security, and Sensing, 2013, Baltimore, Maryland, United States PROCEEDINGS OF SPIE SPIEDigitalLibrary.org/conference-proceedings-of-spie Front Matter: Volume 8757 Proceedings of SPIE Proceedings of SPIE, "Front Matter: Volume 8757," Proc. SPIE 8757, Cyber Sensing

More information

A New Family of High-Performance Parallel Decimal Multipliers*

A New Family of High-Performance Parallel Decimal Multipliers* A New Family of High-Performance Parallel Decimal Multipliers* Alvaro Vázquez, Elisardo Antelo Dept. of Electronic and Computer Science University of Santiago de Compostela Spain alvaro@dec.usc.es elisardo@dec.usc.es

More information

PERFORMANCE ANALYSIS OF AN EFFICIENT PULSE-TRIGGERED FLIP FLOPS FOR ULTRA LOW POWER APPLICATIONS

PERFORMANCE ANALYSIS OF AN EFFICIENT PULSE-TRIGGERED FLIP FLOPS FOR ULTRA LOW POWER APPLICATIONS Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 5.258 IJCSMC,

More information

Available online at ScienceDirect. Procedia Computer Science 46 (2015 ) Aida S Tharakan a *, Binu K Mathew b

Available online at  ScienceDirect. Procedia Computer Science 46 (2015 ) Aida S Tharakan a *, Binu K Mathew b Available online at www.sciencedirect.com ScienceDirect Procedia Computer Science 46 (2015 ) 1409 1416 International Conference on Information and Communication Technologies (ICICT 2014) Design and Implementation

More information

CPU Bach: An Automatic Chorale Harmonization System

CPU Bach: An Automatic Chorale Harmonization System CPU Bach: An Automatic Chorale Harmonization System Matt Hanlon mhanlon@fas Tim Ledlie ledlie@fas January 15, 2002 Abstract We present an automated system for the harmonization of fourpart chorales in

More information

INFORMATION SYSTEMS. Written examination. Wednesday 12 November 2003

INFORMATION SYSTEMS. Written examination. Wednesday 12 November 2003 Victorian Certificate of Education 2003 SUPERVISOR TO ATTACH PROCESSING LABEL HERE INFORMATION SYSTEMS Written examination Wednesday 12 November 2003 Reading time: 11.45 am to 12.00 noon (15 minutes) Writing

More information

Project Proposal: Sub pixel motion estimation for side information generation in Wyner- Ziv decoder.

Project Proposal: Sub pixel motion estimation for side information generation in Wyner- Ziv decoder. EE 5359 MULTIMEDIA PROCESSING Subrahmanya Maira Venkatrav 1000615952 Project Proposal: Sub pixel motion estimation for side information generation in Wyner- Ziv decoder. Wyner-Ziv(WZ) encoder is a low

More information

On-Supporting Energy Balanced K-Barrier Coverage In Wireless Sensor Networks

On-Supporting Energy Balanced K-Barrier Coverage In Wireless Sensor Networks On-Supporting Energy Balanced K-Barrier Coverage In Wireless Sensor Networks Chih-Yung Chang cychang@mail.tku.edu.t w Li-Ling Hung Aletheia University llhung@mail.au.edu.tw Yu-Chieh Chen ycchen@wireless.cs.tk

More information

The main design objective in adder design are area, speed and power. Carry Select Adder (CSLA) is one of the fastest

The main design objective in adder design are area, speed and power. Carry Select Adder (CSLA) is one of the fastest ISSN: 0975-766X CODEN: IJPTFI Available Online through Research Article www.ijptonline.com IMPLEMENTATION OF FAST SQUARE ROOT SELECT WITH LOW POWER CONSUMPTION V.Elanangai*, Dr. K.Vasanth Department of

More information

Modern Cryptography: Theory And Practice By Wenbo Mao

Modern Cryptography: Theory And Practice By Wenbo Mao Modern Cryptography: Theory And Practice By Wenbo Mao Modern Cryptography Theory And Practice Wenbo Mao Pdf Al - Modern Cryptography Theory And Practice Wenbo Mao Pdf. Home Package Modern Cryptography

More information

INTER GENRE SIMILARITY MODELLING FOR AUTOMATIC MUSIC GENRE CLASSIFICATION

INTER GENRE SIMILARITY MODELLING FOR AUTOMATIC MUSIC GENRE CLASSIFICATION INTER GENRE SIMILARITY MODELLING FOR AUTOMATIC MUSIC GENRE CLASSIFICATION ULAŞ BAĞCI AND ENGIN ERZIN arxiv:0907.3220v1 [cs.sd] 18 Jul 2009 ABSTRACT. Music genre classification is an essential tool for

More information

Key-based scrambling for secure image communication

Key-based scrambling for secure image communication University of Wollongong Research Online Faculty of Engineering and Information Sciences - Papers: Part A Faculty of Engineering and Information Sciences 2012 Key-based scrambling for secure image communication

More information

Design of Fault Coverage Test Pattern Generator Using LFSR

Design of Fault Coverage Test Pattern Generator Using LFSR Design of Fault Coverage Test Pattern Generator Using LFSR B.Saritha M.Tech Student, Department of ECE, Dhruva Institue of Engineering & Technology. Abstract: A new fault coverage test pattern generator

More information

Research on Precise Synchronization System for Triple Modular Redundancy (TMR) Computer

Research on Precise Synchronization System for Triple Modular Redundancy (TMR) Computer ISBN 978-93-84468-19-4 Proceedings of 2015 International Conference on Electronics, Computer and Manufacturing Engineering (ICECME'2015) London, March 21-22, 2015, pp. 193-198 Research on Precise Synchronization

More information

LOW POWER AND HIGH PERFORMANCE SHIFT REGISTERS USING PULSED LATCH TECHNIQUE

LOW POWER AND HIGH PERFORMANCE SHIFT REGISTERS USING PULSED LATCH TECHNIQUE OI: 10.21917/ijme.2018.0088 LOW POWER AN HIGH PERFORMANCE SHIFT REGISTERS USING PULSE LATCH TECHNIUE Vandana Niranjan epartment of Electronics and Communication Engineering, Indira Gandhi elhi Technical

More information

OF AN ADVANCED LUT METHODOLOGY BASED FIR FILTER DESIGN PROCESS

OF AN ADVANCED LUT METHODOLOGY BASED FIR FILTER DESIGN PROCESS IMPLEMENTATION OF AN ADVANCED LUT METHODOLOGY BASED FIR FILTER DESIGN PROCESS 1 G. Sowmya Bala 2 A. Rama Krishna 1 PG student, Dept. of ECM. K.L.University, Vaddeswaram, A.P, India, 2 Assistant Professor,

More information

Express Letters. A Novel Four-Step Search Algorithm for Fast Block Motion Estimation

Express Letters. A Novel Four-Step Search Algorithm for Fast Block Motion Estimation IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 6, NO. 3, JUNE 1996 313 Express Letters A Novel Four-Step Search Algorithm for Fast Block Motion Estimation Lai-Man Po and Wing-Chung

More information

Koester Performance Research Koester Performance Research Heidi Koester, Ph.D. Rich Simpson, Ph.D., ATP

Koester Performance Research Koester Performance Research Heidi Koester, Ph.D. Rich Simpson, Ph.D., ATP Scanning Wizard software for optimizing configuration of switch scanning systems Heidi Koester, Ph.D. hhk@kpronline.com, Ann Arbor, MI www.kpronline.com Rich Simpson, Ph.D., ATP rsimps04@nyit.edu New York

More information

Crypto Key Generation From Selected Portion On An Image With CRT

Crypto Key Generation From Selected Portion On An Image With CRT Crypto Key Generation From Selected Portion On An Image With CRT Kalyanapu Srinivas 1, Dr. V. Janaki 2 1 Research Scholar, Department of Computer Science & Engineering, JNTU Hyderabad, Telangana. India

More information

Analysis of Packet Loss for Compressed Video: Does Burst-Length Matter?

Analysis of Packet Loss for Compressed Video: Does Burst-Length Matter? Analysis of Packet Loss for Compressed Video: Does Burst-Length Matter? Yi J. Liang 1, John G. Apostolopoulos, Bernd Girod 1 Mobile and Media Systems Laboratory HP Laboratories Palo Alto HPL-22-331 November

More information

Research Article Design and Implementation of High Speed and Low Power Modified Square Root Carry Select Adder (MSQRTCSLA)

Research Article Design and Implementation of High Speed and Low Power Modified Square Root Carry Select Adder (MSQRTCSLA) Research Journal of Applied Sciences, Engineering and Technology 12(1): 43-51, 2016 DOI:10.19026/rjaset.12.2302 ISSN: 2040-7459; e-issn: 2040-7467 2016 Maxwell Scientific Publication Corp. Submitted: August

More information

Lecture 3: Nondeterministic Computation

Lecture 3: Nondeterministic Computation IAS/PCMI Summer Session 2000 Clay Mathematics Undergraduate Program Basic Course on Computational Complexity Lecture 3: Nondeterministic Computation David Mix Barrington and Alexis Maciel July 19, 2000

More information

USER DOCUMENTATION. How to Set Up Serial Issue Prediction

USER DOCUMENTATION. How to Set Up Serial Issue Prediction USER DOCUMENTATION How to Set Up Serial Issue Prediction Ex Libris Ltd., 2003 Release 16+ Last Update: May 13, 2003 Table of Contents 1 INTRODUCTION... 3 2 RECORDS REQUIRED FOR SERIAL PREDICTION... 3 2.1

More information

Cryptography CS 555. Topic 5: Pseudorandomness and Stream Ciphers. CS555 Spring 2012/Topic 5 1

Cryptography CS 555. Topic 5: Pseudorandomness and Stream Ciphers. CS555 Spring 2012/Topic 5 1 Cryptography CS 555 Topic 5: Pseudorandomness and Stream Ciphers CS555 Spring 2012/Topic 5 1 Outline and Readings Outline Stream ciphers LFSR RC4 Pseudorandomness Readings: Katz and Lindell: 3.3, 3.4.1

More information

Pairing Devices with Good Quality Output Interfaces

Pairing Devices with Good Quality Output Interfaces Pairing Devices with Good Quality Output Interfaces Nitesh Saxena and Jonathan Voris Polytechnic University nsaxena@duke.poly.edu, jvoris@cis.poly.edu Abstract Pairing is referred to as the operation of

More information

Issue 76 - December 2008

Issue 76 - December 2008 Sensor Type to enter text NEWS FROM PIXELMETRIX Issue 76 - December 2008 HIGHLIGHTS DVStation-Mini DVB-T Affordable, Comprehensive DVB-T Monitoring Electronic Couch Potato (ECP) Affordable DTT Monitoring

More information

Digital Logic Design I

Digital Logic Design I Digital Logic Design I Synchronous Sequential Logic Mustafa Kemal Uyguroğlu Sequential Circuits Asynchronous Inputs Combinational Circuit Memory Elements Outputs Synchronous Inputs Combinational Circuit

More information

Improved Coercion-Resistant Electronic Elections through Deniable Re-Voting

Improved Coercion-Resistant Electronic Elections through Deniable Re-Voting Improved Coercion-Resistant Electronic Elections through Deniable Re-Voting Jörn Müller-Quade 1, Dirk Achenbach 1, Carmen Kempka 2, Bernhard Löwe 1 KARLSRUHE INSTITUTE OF TECHNOLOGY, NTT SECURE PLATFORM

More information

Qs7-1 DEVELOPMENT OF AN IMAGE COMPRESSION AND AUTHENTICATION MODULE FOR VIDEO SURVEILLANCE SYSTEMS. DlSTRlBUllON OF THIS DOCUMENT IS UNLlditEb,d

Qs7-1 DEVELOPMENT OF AN IMAGE COMPRESSION AND AUTHENTICATION MODULE FOR VIDEO SURVEILLANCE SYSTEMS. DlSTRlBUllON OF THIS DOCUMENT IS UNLlditEb,d DEVELOPMENT OF AN IMAGE COMPRESSION AND AUTHENTICATION MODULE FOR VIDEO SURVEILLANCE SYSTEMS Qs7-1 William R. Hale Sandia National Laboratories Albuquerque, NM 87185 Charles S. Johnson Sandia National

More information

Subjective Similarity of Music: Data Collection for Individuality Analysis

Subjective Similarity of Music: Data Collection for Individuality Analysis Subjective Similarity of Music: Data Collection for Individuality Analysis Shota Kawabuchi and Chiyomi Miyajima and Norihide Kitaoka and Kazuya Takeda Nagoya University, Nagoya, Japan E-mail: shota.kawabuchi@g.sp.m.is.nagoya-u.ac.jp

More information

Error Resilient Video Coding Using Unequally Protected Key Pictures

Error Resilient Video Coding Using Unequally Protected Key Pictures Error Resilient Video Coding Using Unequally Protected Key Pictures Ye-Kui Wang 1, Miska M. Hannuksela 2, and Moncef Gabbouj 3 1 Nokia Mobile Software, Tampere, Finland 2 Nokia Research Center, Tampere,

More information

ITU-T Y Specific requirements and capabilities of the Internet of things for big data

ITU-T Y Specific requirements and capabilities of the Internet of things for big data I n t e r n a t i o n a l T e l e c o m m u n i c a t i o n U n i o n ITU-T Y.4114 TELECOMMUNICATION STANDARDIZATION SECTOR OF ITU (07/2017) SERIES Y: GLOBAL INFORMATION INFRASTRUCTURE, INTERNET PROTOCOL

More information

SRAM Based Random Number Generator For Non-Repeating Pattern Generation

SRAM Based Random Number Generator For Non-Repeating Pattern Generation Applied Mechanics and Materials Online: 2014-06-18 ISSN: 1662-7482, Vol. 573, pp 181-186 doi:10.4028/www.scientific.net/amm.573.181 2014 Trans Tech Publications, Switzerland SRAM Based Random Number Generator

More information