START OF DIGITAL ACTIVE LINE CO-SITED C B FIGURE 1. TYPICAL VMI 8-BIT DATA FORMAT FOR RECTANGULAR PIXEL 525/60 VIDEO SYSTEMS

Transcription

1 APPLIATION NOTE Video Module Interface (VMI) for Is AN973 ev.. Sep 997 Introduction VMI was developed in cooperation with several multimedia I companies in order to standardize the video interfaces between devices such as MPEG decoders, NTS/PAL decoders, and GUI accelerators. It is primarily based on the output interface and timing of the Philip's SAA7 NTS/PAL decoder. Video Data Format An -bit 4:2:2 br interface is normally used, similar to that used by the T.656 parallel interface. However, the EAV and SAV sequences that T.656 uses are not present. The 4:2:2 br data is multiplexed into an -bit stream: b r b 2 2 r 2, etc. Figures and 2 illustrate the format for 525/6 and 625/5 video systems, respectively, using -bit br data. The stream of active data words always begins with a b sample. In the multiplexed sequence, the co-sited samples (those that correspond to the same point on the picture) are grouped as b,, r. VMI does not define a specific pixel clock rate. However, most rectangular pixel applications sample each line of video at 3.5MHz, generating 72 active samples of 24-bit 4:4:4 br data, as shown in Figures 3 and 4. This is converted to 6-bit 4:2:2 br data, resulting in 72 active samples of per line, and 36 active samples each of b and r per line. The data and the br data are multiplexed, and the 3.5MHz sample clock rate is increased by two to 27MHz. VMI also does not define any horizontal or vertical blanking intervals, using instead a programmable blanking signal (VATIVE). For most rectangular pixel applications, the vertical blanking intervals will be as shown in Figures 5 and 6. Note that active resolutions other than 72 x 46 and 72 x 576 may be supported (effectively cropping the image) by adjusting the timing of VATIVE. Square Pixel Variation A variation using square pixels may also be used. Instead of a 27MHz clock, a 24.54MHz clock is used for 525/6 video systems (64 x 4 active resolution), and a 29.5MHz clock is used for 625/5 video systems (76 x 576 active resolution). VATIVE ONTOL SIGNAL STAT OF ATIVE LINE O-SITED O-SITED 44 STEAM 76 FIGUE. TPIAL VMI -IT DATA FOMAT FO ETANGULA PIXEL 525/6 SSTEMS AN973 ev.. Page of 9 Sep 997

2 Video Module Interface (VMI) for Is VATIVE ONTOL SIGNAL STAT OF ATIVE LINE O-SITED O-SITED 44 STEAM 72 FIGUE 2. TPIAL VMI -IT DATA FOMAT FO ETANGULA PIXEL 625/5 SSTEMS T = /3.5MHz T = /3.5MHz 6T 2T 3T (72-57) 5% SN LEVEL ATIVE LINE 72T (-79) TOTAL LINE 5T (-57) 44T (72-63) 5% SN LEVEL ATIVE LINE 72T (-79) TOTAL LINE 64T (-63) FIGUE 3. TPIAL VMI HOIZONTAL TIMING ELATIONSHIP FO ETANGULA PIXEL 525/6 SSTEMS FIGUE 4. TPIAL VMI HOIZONTAL TIMING ELATIONSHIP FO ETANGULA PIXEL 625/5 SSTEMS Figures 7 and illustrate the data format, Figures 9 and illustrate the typical horizontal timing relationships, and Figures and 2 show the typical vertical blanking intervals. 6-it br Variation Although not a part of the VMI specification, a variation using 6-bit 4:2:2 br data is common, as shown in Figures 3 and 4. In this instance, the PIXLK signal is one-half the normal clock rate: 3.5MHz, 2.27MHz (square pixel 525/6 video systems) or 4.75MHz (square pixel 625/5 video systems). Video Timing Signals In addition to the pixel data, there are four video timing signals, consisting of VEF, HEF, VATIVE, and PIXLK. To support video sources that do not generate a line-locked clock, a Data Valid signal (DVALID) is also commonly used. VEF and HEF can be considered to be VSN and HSN signals, respectively. If HEF is high during the falling edge of VEF, the field is odd. If HEF is low during the falling edge of VEF, the field is even. Thus, even/odd field detection is done using the trailing edge of VEF, rather than the leading edge, as with most video systems. Figures 5 and 6 illustrate the HEF and VEF timing for 525/6 and 65/5 video systems, respectively. VATIVE can be considered a blanking signal, and indicates that valid pixel data is being transmitted across the br bus. If a DVALID signal is also used, valid pixel data is present when both VATIVE and DVALID are asserted. For -bit br interfaces, PIXLK is a 2x pixel clock. For 6-bit br interfaces, PIXLK is a x pixel clock. AN973 ev.. Page 2 of 9 Sep 997

3 LINE 4 LINE (VATIVE = ) ODD ATIVE LINE 2 (VATIVE = ) LINE NUME VATIVE LINE 266 LINE 264 (VATIVE = ) EVEN 2 ATIVE LINE 23 (VATIVE = ) LINE 3 LINE 525 (VATIVE = ) VATIVE = VATIVE = FIGUE 5. TPIAL VMI VETIAL INTEVALS FO ETANGULA PIXEL 525/6 SSTEMS LINE LINE (VATIVE = ) LINE 23 (VATIVE = ) ODD ATIVE LINE NUME VATIVE -22 LINE 33 LINE 3 (VATIVE = ) LINE 336 (VATIVE = ) EVEN 2 ATIVE LINE 624 (VATIVE = ) LINE 625 VATIVE = VATIVE = FIGUE 6. TPIAL VMI VETIAL INTEVALS FO ETANGULA PIXEL 625/5 SSTEMS

4 VATIVE ONTOL SIGNAL STAT OF ATIVE LINE O-SITED O-SITED 2 STEAM 56 FIGUE 7. TPIAL VMI DATA FOMAT FO SQUAE PIXEL 525/6 SSTEMS VATIVE ONTOL SIGNAL STAT OF ATIVE LINE O-SITED O-SITED 536 STEAM FIGUE. TPIAL VMI DATA FOMAT FO SQUAE PIXEL 625/5 SSTEMS T = /2.27MHz T = /4.75MHz 6T 2T 4T (64-779) 5% SN LEVEL ATIVE LINE 64T (-639) TOTAL LINE 7T (-779) 76T (76-943) 5% SN LEVEL ATIVE LINE 76T (-767) TOTAL LINE 944T (-943) FIGUE 9. TPIAL VMI HOIZONTAL TIMING ELATIONSHIP FO SQUAE PIXEL 525/6 SSTEMS FIGUE. TPIAL VMI HOIZONTAL TIMING ELATIONSHIP FO SQUAE PIXEL 625/5 SSTEMS

5 LINE 4 LINE (VATIVE = ) ODD ATIVE LINE 23 (VATIVE = ) LINE NUME VATIVE LINE 266 LINE 263 (VATIVE = ) EVEN 2 ATIVE LINE 26 (VATIVE = ) LINE 3 LINE 525 (VATIVE = ) VATIVE = VATIVE = FIGUE. TPIAL VMI VETIAL INTEVALS FO SQUAE PIXEL 525/6 SSTEMS LINE LINE (VATIVE = ) LINE 23 (VATIVE = ) ODD ATIVE LINE NUME VATIVE -22 LINE 33 LINE 3 (VATIVE = ) LINE 336 (VATIVE = ) EVEN 2 ATIVE LINE 624 (VATIVE = ) LINE 625 VATIVE = VATIVE = FIGUE 2. TPIAL VMI VETIAL INTEVALS FO SQUAE PIXEL 625/5 SSTEMS

6 FIGUE 3. TPIAL VMI 6-IT DATA FOMAT FO ETANGULA PIXEL 525/6 SSTEMS STAT OF ATIVE LINE VATIVE ONTOL SIGNAL 5 72 STEAM STEAM FIGUE 4. TPIAL VMI 6-IT DATA FOMAT FO ETANGULA PIXEL 625/5 SSTEMS STAT OF ATIVE LINE VATIVE ONTOL SIGNAL STEAM STEAM

7 HEF VEF HEF VEF FIGUE 5. HEF AND VEF TIMING FO 525/6 SSTEMS HEF VEF HEF VEF FIGUE 6. HEF AND VEF TIMING FO 625/5 SSTEMS

8 Video Module Interface (VMI) for Is Data Limits br and blanking data should not use the -bit values of H and FF H since those values are used for timing information in T.656 systems. For -bit systems, the -bit values H 3 H and 3F H 3FF H should not be used to avoid contention with -bit T.656 systems. During blanking intervals, values should be set to H (4 H if a -bit system) and br values set to H (2 H if a -bit system). Implementation onsiderations Video I eceivers Assumptions should not be made about the number of clock cycles per line or horizontal blanking interval. Otherwise, the implementation may not work with real-world video signal sources that use digital PLLs and proposed variations such as scaled video. To ensure compatibility between various video sources, any horizontal counters should be reset by the leading edge of HEF, and not by the trailing edge of VATIVE. Any vertical counters to count lines within a field should be reset by the leading edge of VEF. Some video sources indicate sync timing by having data be a value of less than 6. However, most video Is do not do this. In addition, to allow real-world video and test signals to be passed through with minimum disruption, many Is now allow the data to have a value less than 6 during active video. Thus, receiver designs assuming sync timing will be present on the channel will no longer work. To support video sources that do not generate a line-locked clock, the Data Valid signal (DVALID) is commonly supported. When both VATIVE and DVALID are asserted, valid pixel data is present. Video I Sources HEF and VEF have some unique output hold timings - thus, designers must be careful in designing VMI output interfaces. If these specifications are not met, there may be timing problems. Summary This Application Note presented some of the capabilities and issues of the Video Module Interface. Video Is that support VMI, such as the HMP5 NTS/PAL decoder, ease system design by simplifying video interfacing issues. AN973 ev.. Page of 9 Sep 997

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