LGOITHM HW EEC150 ection 2 Introduction to equential Logic Fall 2001 pproach #2: Combinational divide & conquer a[0] a[1] a[1022] a[1023] MX MX MX 512 + 256 + K+ 1 = 1023 blocks Each MX block has: 64 s; outputs 2 64 entries in truth table elay =? 3 10 = 30 units MX EEC150 - Fall 2001 1-4 COMTIONL vs. EUENTIL Combinational y = f (s) n s, m outputs Examples: dder: y[0:3] = a[0:3] + b[0:3] memoryless systems equential y = f (s, time) (most useful: ed logic) Example: (down) counter Time Y[0:3] (e.g. sec) 0 1010 1 9 2 8 1010 0 EEC150 - Fall 2001 1-2 y 4 LGOITHM HW pproach #3: equential max = 0; for (i=0; i<768, i++) if (a[i]>max) max=a[i]; done Hardware equivalence: a[i] 1024 bit memory for (i=0; i<1024; i++) 15 bit counter if (a[i]>max) comparator (combinational) max=a[i] register CT T clk MEM? EG load delay 1024 units bit serial delay: 768 EEC150 - Fall 2001 1-5 LGOITHM HW Example: Finding the largest number in a list. Unsigned int a[1024]; bit int pproach #1: Combinational Number of variables? 768 Number of lines in truth table? 2 768 logic bits a iggest # vector of bit #s time delay? (.O.P.) 768 s bit 0 3 gate delays EEC150 - Fall 2001 1-3 value comparator equal equential Circuits Circuits with Feedback Outputs = f(s, past s, past outputs) asis for building "memory" into logic circuits oor combination lock is an example of a sequential circuit tate is memory tate is an "output" and an "" to combinational logic Combination storage elements are also memory C1 C2 C3 multiplexer mux control new equal comb. logic state openclosed reset EEC150 - Fall 2001 1-6
implest Circuits with Feedback Two inverters form a static memory cell Will hold value as long as it has power applied "data" "load" "1" "0" "remember" "stored value" How to get a new value into the memory cell? electively break feedback path Load new value into cell "stored value" EEC150 - Fall 2001 1-7 0 0 hold 0 1 0 1 0 1 1 1 unstable - Latch ehavior =00 =01 tate iagram tates: possible values Transitions: changes based on s ' 0 1 =01 possible oscillation between states 00 and 11 =01 =11 =00 =10 =01 =11 ' 0 0 ' 1 1 =10 =11 =00 =11 ' 1 0 =10 =00 =10 EEC150 - Fall 2001 1-10 Memory with Cross-coupled Gates Cross-coupled NO gates imilar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) ' Cross-coupled NN gates imilar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) ' ' ' ' EEC150 - Fall 2001 1-8 ' Observed - Latch ehavior Very difficult to observe - latch in the 1-1 state One of or usually changes first mbiguously returns to state 0-1 or 1-0 so-called "race condition" Or non-deterministic transition =00 =01 ' 0 1 =01 =10 =01 =11 =10 ' 1 0 =00 =10 ' =11 0 0 =11 =00 =00 EEC150 - Fall 2001 1-11 Timing ehavior Gated - Latch eset Hold et eset et ' ace Control when and s matter Otherwise, the slightest glitch on or while enable is low could cause change in value stored et ' enable' ' eset ' \ ' ' enable' ' EEC150 - Fall 2001 1-9 EEC150 - Fall 2001 1-12
Used to keep time s Wait long enough for s (' and ') to settle Then allow to have effect on value stored s are regular periodic signals Period (time between ticks) uty-cycle (time is high between ticks - expressed as % of period) Master-lave tructure reak flow by alternating s (like an air-lock) Use positive to latch s into one - latch Use negative to change outputs with another - latch View pair as one basic unit master-slave flip-flop twice as much logic output changes a few gate delays after the falling edge of but does not affect any cascaded flip-flops duty cycle (in this case, 50%) master stage P' ' slave stage ' period P EEC150 - Fall 2001 1-13 EEC150 - Fall 2001 1-16 s (cont d) Controlling an - latch with a Can't let and change while is active (allowing and to pass) Only have half of period for signal changes to propagate ignals must be stable for the other half of period Flip-Flop Make and complements of each other Eliminates 1s catching problem Can't just hold previous value (must have new value ready every period) Value of just before goes low is what is stored in flip-flop Can make - flip-flop by adding logic to make = + ' ' ' master stage P' ' slave stage ' ' ' ' P ' and ' stable changing stable changing stable 10 gates EEC150 - Fall 2001 1-14 EEC150 - Fall 2001 1-17 Cascading Latches Connect output of one latch to of another How to stop changes from racing through chain? Need to control flow of data from one latch to the next dvance from one latch per period Worry about logic between latches (arrows) that is too fast Edge-Triggered Flip-Flops More efficient solution: only 6 gates sensitive to s only near edge of signal (not while high) 0 holds ' when goes low negative edge-triggered flip-flop (-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture ' ' Clk=1 0 holds when goes low characteristic equation (t+1) = EEC150 - Fall 2001 1-15 EEC150 - Fall 2001 1-18
Edge-Triggered Flip-Flops Comparison of Latches & Flip-Flops Positive edge-triggered Inputs sampled on rising edge; outputs change after rising edge Negative edge-triggered flip-flops Inputs sampled on falling edge; outputs change after falling edge positive edge-triggered flip-flop pos pos' neg neg' positive edge-triggered FF negative edge-triggered FF G transparent (level-sensitive) latch edge latch behavior is the same unless changes while the is high EEC150 - Fall 2001 1-19 EEC150 - Fall 2001 1-22 Timing Methodologies Comparison of Latches & Flip-Flops ules for interconnecting components and s Guarantee proper operation of system when strictly followed pproach depends on building blocks used for memory elements Focus on systems with edge-triggered flip-flops Found in programmable logic devices Many custom integrated circuits focus on level-sensitive latches asic rules for correct timing: (1) Correct s, with respect to time, are provided to the flip-flops (2) No flip-flop changes state more than once per ing event Type When s are sampled When output is valid uned always propagation delay from change latch level-sensitive high propagation delay from change latch (TsuTh around falling or edge (whichever is later) edge of ) master-slave high propagation delay from falling edge flip-flop (TsuTh around falling of edge of ) negative hi-to-lo transition propagation delay from falling edge edge-triggered (TsuTh around falling of flip-flop edge of ) EEC150 - Fall 2001 1-20 EEC150 - Fall 2001 1-23 Timing Methodologies (cont d) efinition of terms : periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level setup time: minimum time before the ing event by which the must be stable (Tsu) hold time: minimum time after the ing event until which the must remain stable (Th) Cascading Edge-triggered FFs hift register New value goes into first stage While previous value of first stage goes into second stage Consider setupholdpropagation delays (prop must be > hold) 0 1 OUT T su T h there is a timing "window" around the ing event during which the must remain stable and unchanged in order to be recognized data data stable changing EEC150 - Fall 2001 1-21 0 1 EEC150 - Fall 2001 1-24
Metastability: synchronous s ed synchronous circuits Inputs, state, and outputs sampled or changed in relation to a common reference signal (called the ) E.g., masterslave, edge-triggered synchronous circuits Inputs, state, and outputs sampled or changed independently of a common reference signal (glitcheshazards a major concern) E.g., - latch synchronous s to synchronous circuits Inputs can change at any time, will not meet setuphold times angerous, synchronous s are greatly preferred Cannot be avoided (e.g., reset signal, memory wait, user ) Handling synchronous Inputs What can go wrong? Input changes too close to edge (violating setup time constraint) In 0 1 In is asynchronous and fans out to 0 and 1 one FF catches the signal, one does not inconsistent state may be reached! EEC150 - Fall 2001 1-25 EEC150 - Fall 2001 1-28 Correcting ynchronization Failure Probability of failure can never be reduced to 0, but it can be reduced (1) slow down the system : this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems (2) use fastest possible logic technology in the synchronizer: this makes for a very sharp "peak" upon which to balance (3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail) asynchronous Clk synchronized Flip-Flop Features eset (set state to 0) ynchronous: new = ' old (when next edge arrives) synchronous: doesn't wait for, quick but dangerous Preset or set (set state to 1) (or sometimes P) ynchronous: new = old + (when next edge arrives) synchronous: doesn't wait for, quick but dangerous oth reset and preset new = ' old + (set-dominant) new = ' old + ' (reset-dominant) elective capability ( enableload) L or EN Multiplexer at : new = L' + L old Load maymay not override resetset (usually have priority) Complementary outputs and ' synchronous system EEC150 - Fall 2001 1-26 EEC150 - Fall 2001 1-29 Handling synchronous Inputs Never allow asynchronous s to fan-out to more than one flip-flop ynchronize as soon as possible and then treat as synchronous signal sync Input ed ynchronous ystem 0 1 sync Input ynchronizer EEC150 - Fall 2001 1-27 0 1 "0" egisters Collections of flip-flops with similar controls and logic tored values somehow related (e.g., form binary value) hare, reset, and set lines imilar logic at each stage Examples hift registers Counters 1 2 3 4 EEC150 - Fall 2001 1-30
hift egister Holds samples of tore last 4 values in sequence 4-bit shift register: inary Counter Logic between registers (not just multiplexer) XO decides when bit should be toggled lways for low-order bit, only when first bit is true for second bit, and so on "1" EEC150 - Fall 2001 1-31 EEC150 - Fall 2001 1-34 Holds 4 values left_in left_out clear s0 s1 Universal hift egister erial or parallel s erial or parallel outputs Permits shift left or right hift in new values from left or right output right_out right_in clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 s1 function 0 0 hold state 0 1 shift right 1 0 shift left 1 1 load new 4-bit ynchronous Up-Counter tandard component with many applications Positive edge-triggered FFs w sync load and clear s Parallel load data from, C,, Enable s: must be asserted to enable counting CO: ripple-carry out used for cascading counters high when counter is in its highest state 1111 implemented using an N gate (2) CO goes high (3) High order 4-bits are incremented (1) Low order 4-bits = 1111 EN C CO C LO CL EEC150 - Fall 2001 1- EEC150 - Fall 2001 1-35 Counters equences through a fixed set of patterns In this case, 0, 0, 0010, 0001 If one of the patterns is its initial state (by loading or setreset) Mobius (or Johnson) counter In this case, 0, 1, 1110, 1111, 0111, 0011, 0001, 0000 EEC150 - Fall 2001 1-33