Fundamentals of Computer Systems
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1 Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Summer 2016
2 State-Holding Elements Bistable Elements S Latch Latch Positive-Edge-Triggered Flip-Flop Flip-Flop with Enable Synchronous igital Logic The Synchronous Paradigm Shift egisters Counters Timing in Synchronous Circuits Flip-Flop Timing Timing in Synchronous Circuits Clock Skew
3 State-Holding Elements
4 Bistable Elements Equivalent circuits; right is more traditional. Two stable states:
5 A Bistable in the Wild This debounces the coin switch. Breakout, Atari 1976.
6 S Latch S S S
7 S Latch S S S Set S Set
8 S Latch S S S 0 0 Hold Set S Hold, State 1
9 S Latch S S S 0 0 Hold Set eset 1 1 S eset
10 S Latch S S S 0 0 Hold Set eset 1 1 S Hold, State 0
11 S Latch S S S 0 0 Hold Set eset Bad S Huh?
12 S Latch S S S 0 0 Hold Set eset Bad S Set
13 S Latch S S S 0 0 Hold Set eset Bad S Hold, State 1
14 S Latch S S S 0 0 Hold Set eset Bad S Huh?
15 S Latch S 0 0 X X S S 0 0 Hold Set eset Bad S Undefined
16 S Latches in the Wild Generates horizontal and vertical synchronization waveforms from counter bits. Stunt Cycle, Atari 1976.
17 Latch C C inputs outputs C 0 X
18 A Challenge A simple traffic light controller. Want the lights to cycle green-yellow-red. C C Y C G oes this work?
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31 C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 1 0 C C C M C S C transparent opaque
32 C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 1 0 C C C M C S C transparent opaque
33 C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 0 1 C C C M C S C transparent opaque opaque transparent
34 C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 0 1 C C C M C S C transparent opaque opaque transparent
35 C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 1 0 C C C M C S C transparent opaque transparent opaque transparent opaque
36 C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 0 1 C C C M C S C transparent opaque transparent opaque opaque transparent opaque transparent
37 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
38 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
39 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
40 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
41 The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
42 The Traffic Light Controller with eset ESET Y G ESET Y G
43 The Traffic Light Controller with eset ESET Y G ESET Y G
44 The Traffic Light Controller with eset ESET Y G ESET Y G
45 The Traffic Light Controller with eset ESET Y G ESET Y G
46 The Traffic Light Controller with eset ESET Y G ESET Y G
47 The Traffic Light Controller with eset ESET Y G ESET Y G
48 Flip-Flop with Enable 0 1 E C C E 0 X X X 1 X X E C What s wrong with this solution?
49 Asynchronous Preset/Clear PE CL PE CL
50 The Traffic Light Controller w/ Async. eset ESET PE CL PE CL Y PE CL G
51 The Synchronous igital Logic Paradigm Gates and flip-flops only INPUTS OUTPUTS Each flip-flop driven by the same clock STATE C L Every cyclic path contains at least one flip-flop CLOCK NEXT STATE
52 Cool Sequential Circuits: Shift egisters A A X X X X 1 0 X X X X X X
53 Universal Shift egister L S 1 S0 S 1 S L S 1 S 0 Operation 0 0 Shift right 0 1 Load 1 0 Hold 1 1 Shift left
54 Cool Sequential Circuits: Counters Cycle through sequences of numbers, e.g.,
55 The 74LS163 Synchronous Binary Counter
56 Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change t su
57 Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h
58 Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h Minimum Propagation elay: Time from clock edge to when might start changing t p(min)
59 Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h Minimum Propagation elay: Time from clock edge to when might start changing t p(min) t p(max) Maximum Propagation elay: Time from clock edge to when guaranteed stable
60 Timing in Synchronous Circuits C L t c t c : Clock period. E.g., 10 ns for a 100 MHz clock
61 Timing in Synchronous Circuits C L Sufficient Hold Time? t p(min,ff) t p(min,cl) Hold time constraint: how soon after the clock edge can start changing? Min. FF delay + min. logic delay
62 Timing in Synchronous Circuits C L t p(max,ff) Sufficient Setup Time? t p(max,cl) Setup time constraint: when before the clock edge is guaranteed stable? Max. FF delay + max. logic delay
63 2 Clock Skew: What eally Happens C L 1 2 Sufficient Hold Time? 1 t skew t p(min,ff) t p(min,cl) 2 arrives late: clock skew reduces hold time
64 2 Clock Skew: What eally Happens C L 1 2 Sufficient Setup Time? 1 t skew t p(max,ff) t p(max,cl) 2 arrives early: clock skew reduces setup time
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