Embedded and Ambient System Labratry Syllabus fr FPGA measurements 1. 2. 3. Measurement 1: Intrductin t Verilg, t LOGSYS Spartan 3E bard and the task Measurement 2: Design tasks f Calc_1, Calc_2, Calc_3 and Calc_4 Measurement 3: Design task f Calc_5. Place f measurements: Department f Measurements and Infrmatin Systems FPGA Labratry, Building I, wing E, Lab. IE321. 1
Measurement 1: Intrductin The gal f this measurement is t intrduce the design f a cmplex digital systems, starting frm specificatin, ending with final verificatin and dcumentatin. During the design Verilg HDL (Hardware Descriptin Language) will be used fr the specificatin and an FPGA (Filed Prgrammable Gate Array) device will be used, as the implementatin platfrm. Each functinal blck will be described using high level language cnstructs. Functinal blcks will be cnnected using structural descriptin, building hierarchical design. Task t be implemented: Simple Calculatr The task is t design and implement a simple calculatr, using the Lgsys Spartan 3E FPGA develpment bard. The calculatr will perfrm the fur basic arithmetic peratins, and will use 4 bit wide perands. Results will be displayed n the develpment bard displays (LEDs, and 7 segment display). During the 3 scheduled lab different versins f the simple calculatr will be designed, which assists yu t understand the design f cmplex digital systems, and als helps t try ut the different peripherals f the develpment bard. Dcumentatin f the wrk must be prepared abut the last tw versins f the calculatr. Dcumentatin must inlcude: Shrt task descriptin Optinaly blck diagram Full Verilg surce cde Simulatin screen-shts Shrt descriptin f the implemented mdules. The general specificatin f the calculatr: Input data: 4 bit wide perands, using the develpment bard switches. (2 x 4 pcs.) Inputs are psitive integer numbers Operatins Additin Substractin Multiplicatin Divisin (In the first design XOR will be used fr simplicity) Operatins can be selected using fur buttns. Result display LEDs, in binary frm 7 segment display, decimal and hexadecimal frmat. 2
The LOGSYS Spartan-3E develpment bard. The Lgsys Spartan-3E develpment bard is a simple and cst effective develpment bard, designed fr beginner HDL designers, mainly used in educatin. The fllwing image depicts the internal structure and peripherals f the bard. Detailed specificatin is available (in Hungarian): http://lgsys.mit.bme.hu/dwnlad/logsys_sp3e_fpga_bard.pdf Webpage f the Lgsys system: (Drivers/prgrams) http://lgsys.mit.bme.hu/ Imprtant! The prjects must be cmpiled using the fllwing setup: 3
Peripherals being used LEDs The Lgsys Spartan-3E includes 8 LEDs, marked with LD7 (left mst) LD0 (right mst). Pin numbers can be fund in the fllwing table, and indicated n the PCB als. LEDs must be driven using active high vlatge levels. Seven segment display. The fllwing picture summarizes the cnnectin pattern f the 4 digits 7 segment display f the Lgsys Spartan-3E develpment bard. Digits are numbered as DIG3 (left mst )..DIG0 (right mst). All seven segment signals are active lw. (Bth digit and segment signals) Segment driver and dt matrix display line driver signals are cmmn, which might cause aritfacts n the unhandled dt-matrix display. All fur digits can be used in Time Divisin Multiplexing mde, while each digit has a cmmn segment driver. Time Divisin Multiplex (TDM) driving f the 7 segment displays. DIGnX selects the actual digits, while SEGnY (A, B, C, D, E, F, G, DP) asserts the active segment lines f the required number. 4
At first the right mst digit is selected, by driving DIGn0 signal lw. (Active lw drive, DIGn0 = 0, DIGn1=DIGn2=DIGn3= 1). Meanwhile segment driver signals (A-G, DP) are cntrlled t display the crrespnding character. (Eg. T display an 0 character, A=B=C=D=E=F=0, G=1, active lw drive) After that the system will select the secnd digit (DIGn0 = 1, DIGn1=0, DIGn2= DIGn3= 1), meanwhile driving the segment driver signals accrdingly. And s n Fur digits must be selected in a cyclical manner. The TDM frequency must be selected t be higher than human eye s inertia. Usual multiplexing frequency is cca. 500 Hz. (Multiplexing frequency is limited by the circuit t cca. 10 khz). DIP Switches The develpment bard cntains 8 DIP Switch. The pinut can be fund in the fllwing table. (Leftmst switch is marked as 0, right mst is 7.) Buttns: A LOGSYS Spartan-3E develpment bard has 5 buttns. The leftmst buttn is BTN3. The rightmst buttn is called as RST, althugh it is similar t the thers, has n dedicated reset circuit, but mainly used t issue manual RESET t the tested system. Clck circuit: Tw clck surces are available n the bard. Bth will be used in ur design 16 MHz fixed scillatr. Pin number: P56 LOGSYS Develpment prt CLK line, used in USRT data transfer: P129 5
Measurement 2: Design task 1 : CALC_1 circuit: Fur bit wide input perands are set using the dip switches, the peratin is selected by pressing ne f the fur buttns. Results are displayed n the eight LEDs in binary frmat. Operatins are: additin, subtractin, multiplicatin and exclusive r (XOR). Errr cnditin ccurs when the result f the subtractin is a negative number. Errr is displayed by turning all LEDs n A p. ADD Errr signal [7:4] B p. SUB MUL XOR LED [7:0] Sel BTN Remark: All fur peratins can be realized at different abstractin level f hardver descriptin. 1. A trivial apprach wuld be t define a table/array using embedded memry. While we have nly 2 simple 4 bit perands, it wuld need a 256 deep 8 bit wide memry. Let us frget this slutin. (Imagine the memry requirements in case f 16 bit perands!) 2. We can define each peratin using a bit level descriptin. E.g. a simple ne bit adder circuit cnsist f AND/OR and XOR gates. This is als nt the best way, while the synthesis tl able t built up the circuit, but can nt always recgnize the real cntent f the lgic frm this lw level descriptin, and this might results in an un-ptimal mapping t the FPGA primitives. 3. Each peratin can be described using high level peratrs. (like +, -,*, ^ ) This simplifies the implementatin, and results in easy-t-read cde. As we will see divisin peratin can nt be synthesized, therefre algrithmical descriptin is needed. Task: Design the CALC_1 calculatr. Surce cde must be verified using ISE Simulatr. If simulatin results are crrect, implement the design and dwnlad t the FPGA. Check functinality n the develpment bard t. Imprtant! All designed mdules must be glbally synchrnus. All Flip-flp must get the same clck, always blck must use the same clck s rising edge. Please use reset fr flip-flps. 6
Design task 2: CALC_2 circuit: Let us mdify the previus circuit, by replacing the XOR peratin with divisin. Als extend the errr handling with divisin by zer. A p. ADD Errr signal [7:4] B p. SUB MUL DIV LED [7:0] Sel BTN Binary divisin can be implemented in many different ways: 1. We can build a fully cmbinatrial design, as we wuld execute the divisin n paper. 2. We can handle all pssible scenaris with a big case cnditin r as mentined in the frmer task descriptin, using a 256 entry lk-up-table.. 3. Alternatively sequential implementatin is als pssible. (Preferred) Divisr is subtracted frm dividend as many times as the result is bigger than divisr, meanwhile cunting the cycles. Qutient is equal t the cycle cunt. 7
Design task 3: CALC_3 circuit: CALC_2 Calculatr is fully functinal, but the usage is quite incnvenient, while results appear nly n the LEDs. Let us extend the functinality with a numerical (seven-segment) display. The first tw digits shuld display the tw input perands, while the last tw digits shuld be used fr displaying the results in hexadecimal frmat. Last tw digits displays shuld remain blank when n peratin is selected. If errr cnditin ccurs, last tw digits shuld display EE indicating errr. Errr signal [7:4] A p. B p. ADD SUB MUL DIV A p. B p. Result CLK 4 digit display Digit select Digit cntrller 7SEG SEGn [6:0] DIGn Sel BTN Nte: 7SEG mdule is available in the develpment envirnment under: Edit Menu > Language Templates Cding Examples > Misc > 7-Segment Display Hex.. Verilg > Synthesis Cnstructs> 8
Design task 4: CALC_4 circuit - Shuld appear in the final dcumentatin CALC_3 Calculatr is very handy fr engineers, wh understand hexadecimal numbers, but traditinal users might be messed up. Mdify the CALC_3 circuit in that way, that it accepts and displays numbers nly in decimal frmat. Only input numbers in range 0.. 9 shuld be accepted; therwise the crrespnding digit shuld display E indicating errr cnditin. By limiting the input numbers t decimal, the biggest number t be displayed is 9 x 9= 81, which allws us t display the result n the rightmst- tw digits. CALC_4 shuld include a binary-t-bcd unit t cnvert the result in usual decimal human readable- frmat. [7:4] A p. B p. ADD SUB MUL DIV A p. B p. Result CLK >9 >9 BCD Digit selectin Digit cntrller 7SEG SEGn [6:0] DIGn Sel BTN (The usual (Sub <0, DIV B p==0) errr handling is nt depicted here. ) Remark: Binary-t-BCD is nt a simple peratin. Operatin can nt synthesized directly by mst f the synthesiers. 9
Measurement 3: Design task 5: CALC_5 circuit - Shuld appear in the final dcumentatin The CALC_5 calculatr has many differences cmpared t CALC_4 circuit: Input perands and peratins are received thrugh standard USRT (Universal Synchrnus Receive/Transmit) cmmunicatin interface frm a PC terminal windw.. Bth perands might be ne r tw digits (Max. input number is 99) ENTER is validating each input. An input sequence wuld be: Operand A: One r tw digit decimal number ENTER Operand B: One r tw digit decimal number ENTER Operatin cde: + - * / ENTER ESC abrts current calculatin, and resets the calculatr. (Waiting fr Op. A) Nte: In case f tw digits perands, the transmissin rder is tens units The result is displayed n fur digit seven-segment display. The USRT receiver shuld use the standard UART framing, with the fllwing settings: 8 Data bits N parity 1 stp bit The USRT cable shifts data n the rising edge f the USRT_CLK, therefre ideal psitin fr sampling data is at the falling edge USRT_CLK. Please remember, that fully synchrnus design shuld be created, therefre USRT_CLK can nt be cnnected directly t any flip-flp clck input. Falling edge f the USRT_CLK shuld be detected with a dedicated circuit running frm the main 16 MHz clck input. The fllwing figure depicts the standard USRT framing. USRT CLK USRT data IDLE 0 1 1 1 0 0 1 0 1 START 0 IDLE (LSB) (MSB) STOP 10
The required ASCII cdes: Character ASCII cde 0 9 0x30 0x39 + 0x2B - 0x2D * 0x2A / 0x2F ENTER Can be mdified at Lgsys GUI \r: 0x0D (carriage return) \n: 0x0A (new line) \r \n: first: 0x0D, after: 0x0A ESC 0x1B Reccmended architecture: ADD USRT CLK USRT data USRT IF BCD SUB MUL Result BCD Digit selectin 7SEG SEGn [6:0] DIV Digit Cntrller DIGn peratin USRT pinut: USRT_CLK: LOGSYS develpment prt CLK line (P129) USRT RX (input data): LOGSYS cable MOSI (P120) USRT TX (uput data): LOGSYS cable MISO (P143) Test questins: 1. What are the benefits f using high level HDL languages? 2. What des hierarchical design means? 3. What is the difference between structural and behaviral descriptin? 4. What des nn-blcking statement means? 5. Define in Verilg a fur bit wide register with asynchrnus active high reset! 6. What is Time Divisin Multiplexing? 7. What kinds f resurces are available in FPGA devices? 11