WBS 3.1.2 - Calorimeter Trigger Wesley Smith, U. Wisconsin CMS Trigger Project Manager DOE/NSF Review April 12, 2000 1
Calorimeter Electronics Interface Calorimeter Trigger Overview 4K 1.2 Gbaud serial links w/ 2 x (8 bits E/H/FCAL Energy + fine grain structure bit) + 5 bits error detection code per 25 ns crossing US CMS HCAL: FNAL/ Maryland CMS ECAL: Lisbon/ Palaiseau Copper 40 MHz Parallel 4 Highest E t isolated & non-isol. e/γ 4 Highest jets E x, E y from each crate U. Wisconsin Calorimeter Regional Trigger 72 φ x 60 η H/ECAL Towers (.087φ x.087η for η < 2.2 &.174-195η, η > 2.2) FCAL:2x(12 φ x 12 η) US CMS Trigger: Receiver Electron Isolation Jet/Summary US CMS HCAL: U. Nebraska Luminosity Monitor E t sums Cal. Global Trigger Sorting, E t Miss, ΣE t UK CMS: Bristol CMS: Vienna Global Trigger Processor Muon Global Trigger Iso Mu MinIon Tag MinIon Tag for each 4φ x 4η region 2
Receiver Card (WBS 3.1.2.8) Electron Identification Card (WBS 3.1.2.9) Jet Summary Card (WBS 3.1.2.10) DAQ Proc. (WBS 3.1.2.12) 19 X VME R O C Monitor (WBS 3.1.2.13) Clock/Control (WBS 3.1.2.7) C E M Regional Calorimeter Crate (WBS 3.1.2) L T T C EI EI EI EI JS EI EI EI Prototypes (WBS 3.1.2.1) Preprod. ASICs (WBS 3.1.2.2) Test Facilities (WBS 3.1.2.3) Power Supplies (WBS 3.1.2.4) Crate (WBS 3.1.2.5) Backplane (WBS 3.1.2.6) Data from calorimeter FE on Cu links @ 1.2 Gbaud (ptyp. tstd.) Into 133 rear-mounted Receiver Cards (ptyp. tstd. w/ ASICs) 160 MHz point to point backplane (ptyp. tstd.) 19 Clock&Control (ptyp. tstd.), 133 Electron ID (ptyp. tstd.) 19 Jet/Summary, Receiver Cards operate @ 160 MHz 3
Calorimeter Trigger Geometry 1.811 m 1.290 m η=0.0000 η=0.0870 η=0.1740 η=0.2610 η=0.3480 η=0.4350 η=0.5220 η=0.6090 η=0.6950 η=0.7830 η=0.8700 η=0.9570 η=1.0440 η=1.1310 η=1.2180 η=1.3050 η=1.3920 η=1.4790 2.900 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HB/1 EB/1 Tracker EE/1 HE/1 20 21 22 23 24 25 26 27 28 η=1.5660 η=1.6530 η=1.7400 η=1.8300 η=1.9300 η=2.0430 η=2.1720 η=2.3220 η=2.5000 η=2.6500 η=3.0000 Scale 0 0.5 1.0 (meters) 2.935 m 3.900 m 4.332 m 5.680 m 4
φ 3.0 η 0.0 3.0 0 0 9 π 2π φ.35 Cal. Trigger Tower Mapping 1 2 3 4 5 6 7 8.7 η 2.5 10 11 12 13 14 15 16 17 18 crates for barrel & endcap calorimeters + 1 for v. forward. Each crate processes a 0.7 φ x 3.0 η region. Each Receiver/Elec. ID card pair typically covers a.35 φ x 0.7 η region (modifed in high-η endcap region) Calorimeter Regional Trigger Crate Receiver Cards (x7/crate) 5
Receiver Card VME Control DC/DC 3.3V AMP Stripline power High Density Connector Cable Equalization (2 circuits on front & back) Under-board connectors design by J. Lackey 9U x 400 mm DC-to-DC Converter Mezzanine Card Vitesse Interconnect Chip V 7214 V 7214 V 7214 V 7214 V 7214 V 7214 V 7214 V 7214 Rear: 32 Channels = 4 Ch. x 8 mezzanine cards 1.2 GBaud copper rcvrs 18 bit (2x9) data + 5 bit error Vitesse Chip: Converts Serial to Parallel Input Cable Connectors signals Front: Phase Phase Phase Phase Phase Phase Phase Phase Inter Crate Cables & Staging M E M O R Y S U P P O R T LUTs Bndry Scan & Self Test Adder Adder Adder VME Interface Data from Rear @ 120 MHz TTL Phase ASIC: Deskew,Mux @ 160MHz Error bit for each 4x4, Test Vectors Memory LUT @ 160 MHz Adder ASIC: 8 inputs @ 160 MHz in 25 ns. Differential Output@160 MHz C L O C K D I S T R I B U T I O N Staging & Backplane Drivers 6
Electron ID & Jet/Summary Cards Boundary Scan Controller VME Interface Elect ID Boundary Scan Controller VME Interface Electron Isolation Electron Isolation ISO ISO Differential Receivers & Staging C L O C K Differential Receivers & Staging Processes 4x8 region @ 160 MHz Electron isolation on ASIC Lookup tables for ranking Takes Max in each 4x4 D I S T R Jet/ Sum To Trigger Processor Adder Adder Clock Dist. SORT SORT To Muon Trigger LUT (E x & E y ) Summarizes full crate: Sorts 32 e's,4x4 E t Æ top 4 e's, jets LUTs: E x & E y from E t for 4x4 area Adder tree for E t, E x and E y sums Quiet/MinI bits for each 4x4 region M E M O R Y S U P P SORT SORT SORT SORT SORT SORT 7
8 x 13-bit 160 MHz Adder ASIC Vitesse 0.6µ H-GaAs Process: ECL I/O 13 bits per operand x 8 operands Thirteen bit output Latency: 25 ns @ 160 MHz Full Boundary Scan ~11,000 cells 4 Watts Tested > 200 MHz Operated on RC In Production 8
Cal. Trigger Dataflow Test Prototype Crate with 160 MHz Backplane Proto. Receiver Card (rear) Proto. Clock Card (front) Proto. Electron ID Card (front) Full 160 MHz dataflow verified REAR FRONT 9
Prototype Receiver Card 160 MHz Prototype Receiver Card tests: VME Interface checked Adder ASIC's checked Timing checked Intercrate sharing checked 10
Electron ID Card Prototype Card tested: VME Interface working Dataflow from Receiver Card through custom backplane works Timing checked Logic verified 11
ASIC Development - Receiver Prototype Phase ASIC (Receiver Card) Input: 120 MHz TTL data from Gbit Link Mezzanine Card Output: 160 MHz ECL data & error detection Status: Layout & simulation finished, test vectors developed Vitesse design reviews passed, ready for manufacture Prototype Boundary Scan ASIC (Receiver Card) Boundary scan of Receiver Card Input Backplane drivers -- compact circuitry Status: Layout & simulation finished, test vectors developed Vitesse design reviews passed, ready for manufacture Will test with new Receiver Card prototype 12
ASIC Development - EID & JS Electron ID ASIC (Electron ID Card) Implements Electron Isolation algorithm Described in talk of S. Dasu Status: planned for completion by end of summer Design & Schematics Finished Layout & simulation next Sort ASIC (EID & Jet/Summary Card) Integrated backplane receivers & sorting Passes 4 highest rank of 32 inputs Sorts input before passing unto card Status: planned for completion by end of summer Design & Schematics Finished Layout & simulation next Will test with new Electron ID Card prototype 13
Calorimeter Trigger Links 5.5K 0.8 GHz optical links w/ 2 x (2 bits range, 5 bits mantissa H/FCAL Egy) per 25 ns xing HCAL Front End Electronics DETECTOR ECAL Front End Electronics 76K 0.8 GHz optical links w/2 bits range, 12 bits mantissa of ECAL Egy per 25 ns xing COUNTING ROOM 4K 1.2 Gbaud Cu serial links w/ 2 x (8 bits E/H/FCAL Egy + fine grain structure bit) + 5 bits error detection code per 25 ns crossing HCAL Electronics Interface ECAL Electronics Interface 72 φ x 60 η H/ECAL Towers (.087φ x.087η for η < 2.2 &.174-195η, η > 2.2) FCAL:2x(12 φ x 12 η) Cu 80 MHz Parallel 4 Highest E t isol. & non-isol. e/γ 4 Highest std. & τ jets E x, E y from each crate Calorimeter Regional Trigger Receiver Electron Isolation Jet/Summary to Global Cal. Trig. to Global Mu. Trig. MinIon Tag for each 4φ x 4η region (40 Mhz Parallel Cu) 14
Copper Cable Gbit Serial Data Tests Receiver Mezzanine Card Compare Data - Record errors VME Control Equivalization Circuitry for 3/4 channels Receiver (top view) Transmitter Mezzanine Card Memory Transmitter (top view) 120 MHz output to Receiver Card Receiver (bottom view) 120 MHz input Serial Link Test Card includes VME, memories & comparison circuitry to fully test serial links @ 120 MHz TTL from Mezzanine Cards. (U. Wisconsin) Transmitter (bottom view) Mezzanine Transmit & Receive Cards convert 4 x 1Gb/s links to 120 MHz TTL w/ Vitesse 7214 & cable equalization 15
GBit Data Transmission Tests over 20 m copper cable PRELIMINARY! Vitesse 7214 4 x Gigabit Interconnect chip twisted pair cables (Belden 9182 (150 ohm, 22AWG, foamed dielectric,twinax) grouped by fours & terminated with 8-pin DIN style connectors $318 per 500 foot spool ($2.10 per meter). 16
Trigger Link Bit Error Detection Link error code simulation: Between ECAL & HCAL Upper Level Readout & Cal. Regional Trigger 2x(8 bits E T + 1 bit finegrain) + 5 bits error detection code* + 1 bit "Gap Flag" = 24 bits/25 ns Full 5-bit Hamming Code* finds all 1 & 2-bit errors (most common) Also finds more than 96% of any other error type Procedure upon error is to zero and log the error for readout by DAQ Full implementation in Phase ASIC Passed Vitesse Design Review. Bits with errors Number of Patterns Percent of Errors not found 0 1 0.00 1 24 0.00 2 276 0.00 3 2024 3.45 4 10626 3.49 5 42504 3.03 6 134596 0.08 7 346104 0.17 8 735471 0.06 9 1307504 0.14 10 1961256 0.01 11 2496144 0.01 12 2704156 0.02 13 2496144 0.01 14 1961256 0.10 15 1307504 0.15 16 735471 0.06 17 346104 0.30 18 134596 0.08 19 42504 3.24 20 10626 3.23 21 2024 2.77 22 276 0.03 23 24 0.00 24 1 0.00 17
Plans for Next Year ASIC Development Boundary Scan & Phase ASIC Test prototype run from Vitesse Sort & Electron ID ASIC Finish layout & simulation Vitesse to manufacture, then test Next generation prototypes Backplane Designed for final algorithms Receiver Card Used for testing Phase & Boundary Scan ASICs Will be fit with Gbit link mezzanine cards Electron Isolation Card Used for testing Sort & Electron ID ASICs Serial Link Tests Select final cable Integrate new generation Vitesse link chip (7216) provide test boards for integration with HCAL, ECAL 18
Cal Trigger Schedule & Milestones Advance ASIC production on order to put all under contract with committed delivery schedule -- reduces vendor/process risk Delay Jet/Summary Proto. Board since not essential for design validation. Move J/S component tests to Electron ID Card. 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 Oct Apr Oct Apr Oct Apr Oct Apr Oct Apr Oct Apr Oct Apr Oct Apr Oct Apr Oct Apr Start Prototype Boards 10/1/97 Begin ASIC Development 10/1/97 Internal Design Review 1 11/12/98 Prototype Design Finished 9/9/99 Internal Design Review 2 11/4/99 Begin ASIC Preproduction 9/30/99 Proto. Boards & Tests Finished 4/6/01 Review tests of Regional Trigger 4/6/01 Review of Integration of calorimeter trigger 5/25/01 Begin Backplane & Crate Production 8/31/01 ASIC Development Complete 9/25/01 Finish ASIC Preproduction 1/30/02 Begin Trigger Board Production 11/27/01 Begin ASIC Production 2/28/02 Crate & Backplane Complete 9/18/02 Begin Production Board Tests 9/18/02 Designs Finished 6/26/02 Finish ASIC Production 10/31/03 Finish Trigger Board Production 2/10/ Finish Production Board Tests 3/9/0 19
Cal Trigger Personnel Physicists (at Wisconsin): Faculty: W. Smith & new hire Scientists: S. Dasu & P. Chumney (new) Engineers (experienced team at Wisconsin): J. Lackey -- Lead Engineer & Designer Also Lead Engineer for Zeus Calorimeter Trigger M. Jaworski -- Board Layout & Design support Worked on Zeus Calorimeter Trigger H. Zhang -- ASIC Layout/Simulation (new) Worked on Zeus Calorimeter Trigger D. Wahl -- Copper Link Test/Development (new) PSL Engineer, assisted by lead PSL electronics engineer, P. Robl, who worked on Zeus Trigger 20
Issues Committee Concerns: Increase Physicists & Engineering Personnel Done (see previous slide) Apply engineering resources to recover schedule Done: application to ASIC development & Gbit Link Issue at time of last review: Watch ASIC availability issues, as early procurement may become necessary. Entire ASIC production under contract with Vitesse Schedule rearranged to procure all of each ASIC immediately after successful test. Detailed series of reviews set up with Vitesse to provide strict QA/QC & testability Vitesse to deliver fully tested packaged ASICs 21
Conclusions Successful Prototyping Program Crate, Backplane & Clock Card Receiver Card Electron Isolation Card Serial Link Test & Mezzanine Cards Adder ASIC -- now in production Plans for next year Completion of all first prototype & some second. Link prototypes used for integration w/ecal,hcal Cost & Schedule experience: ASIC vendor/schedule accelerated Personnel augmented No use of contingency, on schedule 22