EE 2: igital Logic ircuit esign r Radwan E Abdel-Aal, OE Logic and omputer esign Fundamentals hapter 3 Unit ombinational 4 Sequential Logic esign ircuits Part Implementation Technology and Logic esign harles Kime & Thomas Kaminski 24 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Unit 4: Sequential ircuits (Finite State Machines FSM). Sequential ircuit efinitions, Types of Latches: SR, locked SR, and Latches 2. Flip-Flops: SR,, JK, and T Flip-Flops 3. Flip-Flop Timing Parameters: Setup, hold, propagation, clocking 4. Flip-Flops: haracteristic Tables and Excitation Tables 5. Analysis of Sequential ircuits with various types of flip-flops: eriving the input equations, state table, and state diagram. Timing. 6. esign of Sequential ircuits with various types of flip-flops: etermining the state diagrams and tables, State assignment, ombinational Logic Introduce New needed omponents (memory elements) Analysis esign hapter 3 - Part 2
Introduction to Sequential ircuits Outputs are functions of inputs and some previous (state) outputs External External State Inputs State Outputs A Sequential ircuit (S) consists of: ata Storage (memory) elements: (Latches / Flip-Flops) + ombinatorial Logic: Implements a multiple-output function External Inputs are signals from outside External Outputs are signals to outside State inputs (Internal to S) = Present State at o/p of storage elements State outputs, Next State at i/p of storage elements The storage (memory) elements isolate the next state from the present state, So changes occur only when desired hapter 3 - Part 3 Introduction to Sequential ircuits (S) S (State) (State) ombinational ircuit outputs: Next state: Next State = f(inputs, State) External Output:- Two Possibilities: Mealy ircuits Outputs = g(inputs, State) Moore ircuits Outputs = h(state only) hapter 3 - Part 4 2
Timing of Sequential ircuits Two Approaches Behavior depends on the times at which the storage elements sense their inputs and change their outputs ( next state becomes present state ) Asynchronous (No clock) Behavior defined from knowledge of inputs at any instant of time and the order in which inputs change in continuous time Synchronous (More common) Behavior is determined by the signals at discrete times (clock pulses) Storage elements sense their inputs / change state only according to a timing and synchronizing signal (a clock) Will use mainly the synchronous approach here I/P O/P at the arrival of a clock pulse clock Storage Elements When a clock pulse arrives, the S moves from one state to the next hapter 3 - Part 5 ata Storage Logic Structures for Ss t pd Old I/P Remembered ata In (hange data stored) O/P Output-maintaining feedback elay in A non-inverting Buffer Problem: ata stored only for short time = Propagation delay t pd Non-inverting buffer With feedback- indefinite Write Write Feedback across Two inverting buffers onnected in series Problem: No separate input for data. ifficult to change data stored Set-Reset (momentarily) NOR Latch Now 2 separate inputs: - ata-in (momentarily make the change to be stored) - Feedback to maintain that change hapter 3 - Part 6 3
Basic NOR Set Reset (SR) Latch Set: Make =, Reset: Make = ross-coupling two NOR gates gives the Set Reset Latch: Which has the time sequence Time behavior: = Normal input condition No input change (show last stored I/P) Input R S stored (written) in (remains at O/P after input is removed) R (reset) Both refer to S (set) R S omment Show the last stored data Set to (Write ) Reset to (Write ) Both and = (Avoid)?? Undefined! ( = or ) S =, R = simultaneously is a forbiddenhapter input 3 - Part pattern 7 remembers written after I/P disappeared remembers written after I/P disappeared Basic NOR Set Reset (SR) Latch Reset then Set then Should not try to Set and Reset at the same time! Forbidden I/P omb. Which hanges First?? Unpredictable _b = hapter 3 - Part 8 4
Basic NAN Set Reset (SR) Latch ross-coupling two NAN gates gives the S R Latch: Which has the time sequence Time behavior: = Normal input condition No input change Input S R stored in (remains at O/P after input is removed) R (reset) S (set) S R omment Show the last stored data Set to (Write ) remembers written after I/P disappeared Reset to (Write ) remembers written after I/P disappeared Both and go high (Avoid)?? Undefined! ( could be or ) S =, R = simultaneously is a forbiddenhapter input 3 - Part pattern 9 locked (or ontrolled) S-R NAN Latch Adding two NAN gates to the basic S - R NAN latch gives the clocked S R latch: lock is a gate for S, R = normally S R inputs to the latch = normally (No output change) So this prevents the forbidden conditions S R = with = = Opens the two input NANs for the S R, inverting them. This gives normal S R (not S R) latch operation Allow changes in latch state But here both S R = with = is still a problem means control or clock. hanges in SR affect the latch only during the clock pulse latch This latch is Transparent: i.e. O/P follows the I/P directly when = Freeze (Read) hapter 3 - Part 5
The locked Latch- Totally avoids the SR = Problem! type latch Adding this inverter to the S-R Latch, makes it a Latch We got rid of the unwanted condition (SR = with = ) But also lost SR = (no change)! When =, this latch is transparent: The I/P is effectively connected to output, i.e. follows With = With = : Freeze Output at last value Function Table written when was, (can change only when becomes again) hapter 3 - Part S R To get no change : Must block the clock pulses! ( = last before went from to ) i.e. with = : From Latches to Flip-Flops The transparent latch timing problem Solution: Flip-Flop Master-slave flip-flop Edge-triggered flip-flop Standard symbols for storage elements irect inputs to flip-flops Flip-flop timing Types of flip-flops:, JK, T hapter 3 - Part 2 6
The Transparent Latch as a Storage Element: Timing Problem onsider this sequential circuit: t Y-Y Transparent latch is problematic here! lock Y t W The ombinational Logic part Wide lock Pulse t Y-Y t Y-Y Transparent Latch Suppose that initially Y =. As long as =, the value of Y keeps changing! hanges occur based on the delay in the Y-to-Y loop State Variable The latch was supposed to isolate outputs of the combinational circuit from its inputs. Is it??? If t Y-Y << t W this causes several unwanted state changes to occur during the same clock pulse- unacceptable! esired behavior: Y should change only once per clock pulse, in order to get only one state transition per clock pulse! hapter 3 - Part 3 Solving the Latch Timing Problem Flip flops instead of latches Two approaches: Break the path within the storage element into two successive (mutually exclusive) steps in time: Step -. Register the change in input (then stop) Step - 2. Apply that change to the output Y (then stop) This uses a master-slave (Pulse Triggered) flip-flop OR Use an edge-triggered flip-flop: hange in is sensed and applied to the output in one go at the edge of the clock pulse (+ ive or ive edge) i.e. Effectively as if we have a Zero-width clock pulse, which obviously solves the problem (see previous slide) hapter 3 - Part 4 7
S-R Master-Slave (Pulse-Triggered) Flip-Flop onsists of two clocked S-R latches in series, with the clock to the second latch inverted = : - Master is open st half - Slave is blocked Of clock Pulse From L S R = = S Master R Slave Only input is sensed by master for this pulse duration ( pulse-triggered) while output is unchanged by slave = : - Master is Blocked 2 nd half Of clock Pulse- Slave is open output is changed The path from input to output is thus broken by the different 2 clock levels for the two latches ( = and = ) Sensing I/P then changing O/P are now two separate steps - not one transparent step as the case with the transparent hapter 3 - Part latch 5 X S R X = = To L S-R Master-Slave Flip-Flop: Simulation Ideally, changes in S, R inputs from combinational circuit should arrive to master before the next clock interval (= pulse) arrives. ata appears at slave O/P lock Interval T Set Reset Z In Out elay T/2 = T/2 M X X S X X X Z Z Forbidden ondition S =, R = Still possible hapter 3 - Part 6 8
Edge-Triggered -type Flip-Flop This is a Positive Edge-triggered -type flip-flop Is currently the most preferred FF for building sequential circuits ata The data input is transferred to the output only at the rising edge of the clock, subject to timing constraints on the input relative to effective clock edge: Setup time before edge and Hold time after edge Negative edge triggered FF is also available hapter 3 - Part 7 Flip-Flop Timing Parameters: - ive Edge Triggered FF (Section 6.3) Requirements: t w -clock pulse width (for both low & high) onsider a Negative Edge-Triggered Flip Flop bubble t s : setup time t h : hold time (usually ns) Outcomes: t p : propagation delay Input transitions allowed Valid, Stable Old Old ata ata on on New ata on Output transitions occur input can still change up to here! Better utilization of time faster sequential cct designs compared to Master-Slave FF hapter 3 - Part 8 9
Standard Symbols for Storage Elements Unclocked clocked. Latches (Transparent) 2. Flip Flops SR SR a. Master-Slave (M-S) Pulse-Triggered: O/P determined Postponed during output clock pulse width and indicators changed at its end b. Edge-Triggered: O/P determined & changed on the indicated clock edge S R S R Triggered SR S R (b) Master-Slave Flip-Flops Triggered (c) Edge-Triggered Flip-Flops SR, Active high lk In a sequential that uses M-S different (Pulse S Types of FFs, Ensure that Triggered) all FFs FF circuit M-S change -typetheir outputs I-O Isolation, R at the same clock edge. But Invert with clock signal to some FFs caution! if needed Triggered SR Triggered Triggered Triggered SR, Active high lk, Active high lk Transparent Latches, Provide No I-O isolation One problem with type FF is that no inputs produce no change at the output Solution: - Block the clock pulses - Feed back the to the input when no change is required (See Unit 5) hapter 3 - Part 9 FF irect Inputs When power is turned ON, the state of a sequential circuit FFs could be anything! We usually need to initialize the circuit to a known state before operation starts This initialization is often done directly outside the clocked behavior of the circuit, i.e., asynchronously irect S and/or R inputs that control the state of the latches within the flip-flops are added to FFs for this purpose For the example the flip-flop shown applied to R directly (S=): resets the flip-flop to the state regardless of the clock applied to S directly (R=): sets the flip-flop to the state regardless of the clock Bubble I/P is active low Synchronous (clocked) Edge- Triggered lock action Active Low Asynchronous Action- Regardless of the clock Asynchronous (irect) S,R Till next lock edge Synchronous (clocked) action hapter 3 - Part 2
Other Types of Flip-Flops We know about the master-slave S-R and flip-flops We will briefly introduce the J-K and T flip-flops Implementation Behavior haracteristic Table/Equation: For use in S Analysis Excitation Table/Equation: For use in S esign hapter 3 - Part 2 Analysis haracteristic Basic Flip-Flop escriptors Excitation design In analysis: Given a ircuit: Present state, I/Ps L FF Inputs? FF O/P (Next state)? FF: FF Inputs & Present output Next FF output? haracteristic table - defines the next output of the flip-flop given its present output and its inputs Or haracteristic equation - defines the next output of the flip-flop as a Boolean function of its present output and its inputs In design: Given a state transition behavior? L? FF: Present output & Next output? FF inputs? (that give such behavior) Excitation table - defines the flip-flop inputs that give a required present-to-next output behavior hapter 3 - Part 22
Flip-Flop Analysis esign Analysis esign haracteristic Table Input- riven Analysis (t) (t + ) Operation Reset Set haracteristic Equation (t+) = (t) Excitation Table Output- riven (t +) esign (t) Operation Reset Set oes not depend on the present O/P Next O/P = Present I/P Limitation of FF: No built-in No hange ondition while clock is connected Present I/P = esired Next O/P Hence simplicity of using FF hapter 3 - Part 23 Analysis S-R Flip-Flop haracteristic Table Input- riven Pulse or Edge -Triggered? Given the present FF I/Ps, O/P Next FF O/P =? Improvement on! Limitation: SR=: Undesirable ondition haracteristic Equation Excitation Table Given Present, next O/P s FF Inputs =? Get from above esign Output behavior- riven hange, Or Reset, Or Set hapter 3 - Part 24 2
J-K Flip-Flop- Improvements on SR and types on SR: Avoids the SR =, JK = Toggle, i.e. (t+) = (t) on type: Allows a No hange condition haracteristic Table J K (t+) Operation haracteristic Equation Now OK! (t) (t) No change Reset Set omplement (Toggle) Excitation Table (t) (t + ) J K hange X X X X Operation No change Set Reset No hange, Or Reset, Or Toggle, Or Toggle, Or Set J K (t) (t+) hapter 3 - Part 25 T (Toggle) Flip-Flop FF with only No change & toggle capabilities haracteristic Table T (t+ ) (t) (t) Operation No change omplement (Toggle) haracteristic Equation (t+) = (t) = T (t) Excitation Table T (t+) (t) (t) T Operation No change omplement (Toggle) hapter 3 - Part 26 3
Sequential ircuit Analysis & esign (Present) How many? Log 2 (number of states) Analysis: Given a circuit. escribe how it behaves, in terms of: Present State, Inputs Next State? Outputs?, esign: Given how a circuit behaves, in terms of: Present State, Inputs Next State, Outputs, etermine the circuit Sequential ircuit Analysis: With -type FFs General Model m Present State (state) at time (t) are the O/Ps of an array of flip-flops Next State at (t+) are O(t) combinational fns of {State & Inputs} (External) Outputs at time (t) are a combinational function of State (t) only (Moore) and also Inputs (t) (Mealy) (t) n O (t) Present α n (here α=) State (t) FF Provides isolation between in and out: State (t) is not affected by O(t) until.. Present (t) n State Bits (State variables) (one FF bit) Max # of states for a circuit with 4 FFs?. the next clock pulse comes: How many FFs needed for a circuit with 6 states? t becomes t+, O(t) is moved to FF output, thus becoming State hapter (t+), 3 i.e. - Part next state 28 S R p (t) 4
Sequential ircuit Analysis Given a sequential ircuit Objective: Obtain outputs & state behavior (External outputs and next state) from (External inputs and present state) for all combinations of I/Ps & present state Two equivalent approaches to represent the results of the analysis: State table: A truth table-like approach State diagram: A graphical, more intuitive way to represent the state table and express sequential circuit operation hapter 3 - Part 29 Analysis Example using FF: Given a Sequential ircuit etermine how it behaves External Inputs: x(t) External Outputs: y(t) x State Outputs: A(t), B(t) In Analysis we determine: omb. Equations for the FF inputs then use FF characteristics to get the next state given a present state and inputs omb. Equations for the External Outputs and use them to get the ext outputs given a present state and inputs External Inputs ombinational Logic lock P Feedback Flip Flops A A State AB B y External Output(s) Synchronous or asynchronous? Mealy or Moore? hapter 3 - Part 3 5
Analysis Example : A Mealy ircuit, Ext. Output = F(state, inputs) eriving flip flop input equations MSB Right at the outset, there are things we can do: We can derive Boolean equations for all outputs of the combinational logic (L) circuits Two types of L outputs: Flip flop inputs (Will determine the next state based on FF characteristics) A = AX + BX B = AX External Outputs: Y = (A+B) X + ive Edge Triggered FFs State: AB Note: Flip flop inputs needed to determine next state depend on the type of flip flop used, e.g., SR, etc. hapter 3 - Part 3 State Table haracteristics State table a multi variable table with the following four vertical components: L = ombinational Logic L Inputs: FF = Flip Flop Present State (MSBs) Values of the state variables (FF outputs) for each allowed state External Inputs MSB MSB Outputs: Next-state Value of the state (FF outputs) at time (t+). etermined by: FF inputs (outputs of L) (A) (B) the FF characteristics: Simplest for -type FF: L External Outputs the value of the outputs as a function of the present state only (Moore) or present state & external inputs (Mealy) hapter 3 - Part 32 6
FF Input Equations: One-imensional State Table x (A) # of rows in Table = 2 (# of FFs+ # of external inputs) A A Two State Variables: A, B: 4 states In general, Get from: - Equations for FF input (L) -Then FF haracteristic table or equation For -type FF: Simply i i Purely ombinational (B) B P y 4 states, ext input inputs Inputs Vary + + (A) (B) outputs check hapter 3 - Part 33 The Two-imensional State Table a step closer to the Sate iagram # of rows in Table = 2 (# of FFs) and O/Ps are given separately for each I/P combination x A A Two State Variables A, B 4 states # of bays = # of input combinations (If Moor?) # of bays = # of input combinations (Mealy) B Only Inputs Vary Inputs Vary P y Inputs Vary # of rows = # of states Next State Output (Mealy) = f (State, I/P) = f (State, I/P) hapter 3 - Part 34 7
Sate iagram, Mealy ircuits Input/output irected arc To next state x A A State Transition For a given input value, orresponding O/P is also marked State Number of transition arrows exiting a state circle = Number of combinations of ext inputs, here = 2^ = 2 B P y hapter 3 - Part 35 ombinational O/Ps change combinationally all the time State Variables (FF O/Ps) updated only at clock edge, here etermine FF s ombinationally Here, just before effective clock edge Asyncl l Functional Simulation - Fig. 4-8 Mano & Kime RESET... LOK... Then transfer FF s to FF s on the effective clock edge. 53ns 6ns 59ns 22ns 265ns 38ns 37ns 424ns 477ns 53ns l X... External I/P l NA... l NB... l A... l B... l Y... l i FF I/Ps State X X t t+ t+2 t+3 State variables change only at clock edges External O/P Reset state (all s) to (asynchronously?) Output in Mealy can change asynchronous to clock (if input X is asynchronous) hapter 3 - Part 36 8
Moore and Mealy Models In State iagram Sequential ircuits are also called Finite State Machines (FSMs). Two formal models existaccording to dependencies of External Outputs Moore Model Named after E.F. Moore. External Outputs (O/Ps) are functions of the state ONLY In Timing Waveforms O/Ps are shown next to the state value (inside the state node) O/Ps change only with the state with the clock Sync. to clk Mealy Model Named after G. Mealy External Outputs are functions of the state AN external inputs O/Ps are shown on the state transition arcs- next to the I/P O/Ps can change with I/Ps possibly asynchronous to clock In contemporary designs, FSM are sometimes mixed: Some O/Ps are Moore and some are Mealy hapter 3 - Part 37 Analysis Example 2: A Moore ircuit Output = F (States only) Right at the outset, there are things we can do: erive Boolean expressions for all outputs of the combinational logic (L) circuits These L outputs are: Inputs to the flip flops A = X Y A (the odd fn) Output to the outside world Z = A epends only on state not on inputs, Moore Ext. I/Ps Next = A I/P combinations Affect state transitions only Not the O/Ps = Present A Present A Ext. O/P One +ive Edge Triggered FF, 2 = 2 states Ext. O/P etermined only by the present state (not the I/Ps) Moore Output is determined only by the State ( so in the circle) State, Output How many arcs emanate From each circle? As many as the I/P combinations hapter 3 - Part 38 9
Sequential ircuit Analysis: Using other types of Flip Flops: JK, T type FF was easy to use, as the input from L is the same as the Next state bit (e.g. A(t) = A(t+)) For other types of FFs, this is not so, and you will have to go through either: The haracteristic Table Or the haracteristic Equation hapter 3 - Part 39 Sequential ircuit Analysis Example: Using JK Flip Flops L Equations of FF Inputs JK haracteristic Eqn. - Substituting for FF A: To simplify the derivation of state table, get as SOP A(t+) = BA +(Bx ) A =A B+AB +Ax Gives A Next State - Substituting for FF B: B(t+) = x B +(A x) B = B x +(Ax+A x )B = B x +ABx+A Bx Gives B Next State No external O/Ps! hapter 3 - Part 4 2
Sequential ircuit Analysis Example: Using JK Flip Flops L Equations of FF Inputs All RHS is at t JK haracteristic Eqn. Standard I/P Listing ABx + + Needed only if you use The characteristic table - Substituting for FF A: A+=A(t+) = BA +(Bx ) A =A B+AB +Ax Gives A Next State SOP to simplify plotting in state table J K - Substituting for FF B: ould have used B+=B(t+) = x B +(A x) B the FF = B x +(Ax+A x )B haracteristic Table = B x +ABx+A Bx Gives B Next State (t+) (t) (t) Operation No change Reset Set Toggle hapter 3 - Part 4 Sequential ircuit Analysis Example: Using JK Flip Flops State iagram If FSM is at state S2 and x fixed at : When do we return next to S2? hapter 3 - Part 42 2
Sequential ircuit Analysis Example: Using T Flip Flop L Equations for FF Inputs & Ext O/P T-FF haracteristic Eqn. (t+) = T (t) - Substituting for FF A: A(t+) = Bx A = BxA +A(BX) =A Bx+A(B +x ) =A Bx+AB +Ax A Next State - Substituting for FF B: B(t+) = x B B Next State One external O/P Mealy or Moore? hapter 3 - Part 43 Sequential ircuit Analysis Example: Using T Flip Flop L Equations for FF Inputs & Ext O/P + + T FF haracteristic Eqn. (t+) = T (t) - Substituting for FF A: A(t+) = Bx A = BxA +A(BX) = A Bx+A(B +x ) = A Bx+AB +Ax Gives A Next State - Substituting for FF B: B(t+) = x B Gives B Next State hapter 3 - Part 44 22
Sequential ircuit Analysis Example: Using T Flip Flop Note how O/P y is represented in the state diagram hapter 3 - Part 45 Sequential ircuit esign: The esign Procedure Steps in green are similar to L esing. Specification (Word escription) State iagram (an be symbolic at this thinking stage) 2. State Reduction: Try to reduce the number of states (Will cover later) -This may reduce the number of FFs required 8? 3. State Assignment - Assign binary codes to the symbolic states 4. Obtain a Binary state table. 5. For the selected type of Flip Flops: Use the excitation table to obtain the binary FF inputs 6. erive Optimized logic expressions for each of the: - FF Inputs - External Outputs 7. Generate the logic diagram for the complete sequential cct. hapter 3 - Part 46 23
Sequential ircuits Analysis Versus esign / / A / B / / / / / Analysis 2- esign - Analysis of a given circuit: Given a circuit behavior [state table (state diagram)]: {ircuit, Present state, inputs} Next state?, Outputs? Flip Flop onsideration: (inputs outputs?) FF: Use input-driven haracteristic tables/equations For flip flops: A (t) A (t+) B (t) B (t+) Analysis esign esign to achieve a specified circuit performance Given desired behavior [(state diagram (State table)] get circuit (behavior: Present to next changes Needed FF Inputs? L circuit?) Flip Flop onsiderations: (behavior at O/P inputs that give behavior?) FF: Use output-driven Excitation tables/equationshapter 3 - Part 47 omplete esign Procedure Example: 3 or more successive s detector Specification (word description) Symbolic State iagram Square Moore hapter 3 - Part 48 24
3 s etector Example: with -type FFs Tied to State ircuit etails: State Assignment (- FF) S =A =B hapter 3 - Part 49 3 s etector Example ombinational Logic esign Optimized implementation Obtained from 3 K-maps hapter 3 - Part 5 25
3 s etector Example The ircuit hapter 3 - Part 5 3 s etector Example esign with JK Flip Flops Specified ct Behavior: Need to derive the FF Inputs erived FF A FF B JK Excitation Table L Outputs hapter 3 - Part 52 26
3 s etector Example esign with JK Flip Flops Example: A 3-bit binary up counter esign with T Flip Flops State iagram T FF Simplifies esigning ounter State Table esired Performance Required FF Inputs 27
esign with T Flip Flops Example: A 3-bit binary counter A always toggles (at next clock) A2 toggles (at next clock) If present A, A = A toggles (at next clock) if present A = State Reduction When we are interested only in the input-output sequence and not in the state values themselves (in counters) (without affecting the in-out sequence) Input Sequence 7-State FSM States e, g are equivalent, Same: -Next state - O/P for all input combinations (Important) 56 * * 28
State Reduction When we are interested only in the input-outputs sequences and not in state values (With counters we ARE interested in the states) State Reduction When we are interested only in the input-output sequences and not in state values (With counters we are interested in the states) # of States (originally 7) # of FFs # of Unused States Remove Row 7 3 Remove g row and replace gs with es Remove Row Remove f row and replace fs with ds 6 3 2 5 3 3 Any Advantage? (More on t ares) 29
After State Reduction- Now using 5 states only Reduced 5-State FSM Maintains same input-output sequence as the original 8-state circuit On slide 56 State Assignment: Symbols Binary - Input-output sequence is not affected by the binary assignment - But generally: it affects L circuit cost - 3 Possible state coding schemes: 3 FFs 5 FFs ( FF/State) but simpler L circuit for the FF inputs 3