ontap BOUNDARY SCAN SOFTWARE PRODUCT FEATURES AND SCREEN TOUR FLYNN SYSTEMS CORP.

ontap BOUNDARY SCAN SOFTWARE PRODUCT FEATURES AND SCREEN TOUR FLYNN SYSTEMS CORP. PROVIDING BOUNDARY SCAN SOLUTIONS SINCE 2000

1 ontap Product Documentation Table of Contents Introduction... 4 Overview... 5 ontap Product Outline... 5 Key Features... 6 Key Features (cont d)... 9 Run-Time Test Environment... 9 ProScan Enhanced Test Environment... 9 User-Defined Tests... 9 Essential Utilities and Tools... 9 Critical Circuit and Testability Analysis... 9 Hardware... 9 Technical Support... 9 Pending: Support for the 2013 IEEE 1149.1 Std.... 9 ontap s UI Organization... 9 ontap s GUI Screen Views... 10 Development Screen... 11 The Test Screen... 12 ProScan Screen... 13 Development Environment... 14 Projects Page... 15 Scan Page... 16 Non-Scan Page... 17 Jumpers Page... 18 Guards Page... 19 Cluster Page... 20 Testability Page... 21 TestGen Page... 22 TestPlan... 23 Available Instructions... 24 Test Environment... 25 Selecting a Project Folder... 26

Selecting a Project Folder (cont d)... 27 Selecting and Running the Test... 28 The Test Status... 29 Parallel Test Control... 30 Burn-In Mode... 31 Flash Control... 32 Auto Detect JTAG Chain... 33 View Fails and Report... 34 Prompts... 35 Tap Connect... 36 Tap Connect and Self-test... 37 ProScan... 38 Waveforms... 39 Net Browser... 40 appxam... 41 Guards + Attributes... 42 Pins+Cells... 43 Commands... 44 Breakpoints and single-stepping... 45 ontap Tools... 46 BSLD Syntax Check... 47 DTS Syntax Check... 47 Compose Netlist... 48 Examine SVF... 49 Merge Netlists... 50 Compose SVF File... 51 Summarize and View Test Reports... 52 Add Alternate IDCODES... 53 Debug Tools... 54 ShowMe!... 54 Log TDO Hex DATA to file scandata.txt... 55 Board Netlist Translators... 56 2

Menu Selections... 57 Hardware... 58 TAP CONNECT JTAG Cable... 58 ontap TAP GPIO SERIALIZER... 59 Technical Support... 60 3

Introduction Flynn Systems has been providing automatic test generation software tools for over 20 years. Our extensive boundary scan experience with PC based ontap applications translates to mature and full-featured products for our customers worldwide. This data sheet provides an overview of the ontap Boundary Scan Software and related hardware available from Flynn Systems. Designers and test engineers alike are choosing boundary scan as the optimal technology to economically and effectively add testability for both prototype and manufacturing test and diagnostics of their PCBs. ontap software tools include: netlist-based automatic boundary scan test program generation, pin-level boundary-scan diagnostics, a ProScan waveform display and netlist browser for interactive boundary scan debugging, netlist merging plus many productivity tools, along with over two dozen netlist translators. ontap provides a complete and robust boundary scan test solution (Figure 1), as well as the ability to run multiple parallel chains simultaneously with multiple ontap TAP CONNECT JTAG Cables. A TAP GPIO-Serializer is available to configure multiple chains as one chain and to provide external GPIO signal control. ontap s DLL and batch mode run under independent test executives such as National Instruments LabView. Design engineers find IEEE Std. 1149.1 and IEEE Std. 1149.6 tools to be particularly helpful in testing and clearing faults from prototype boards. The same tests are equally valuable when applied in manufacturing from PCs and in-circuit test equipment. Sharing test development costs in this manner amortizes and protects investments. 4

Overview ontap Boundary Scan Software offers design and test engineers efficient and affordable solutions to test and clear faults from prototype PCBs, as well as providing a suite of tools for manufacturing test and diagnostics. ontap effectively and capably handles difficult problems on complex PCBs. The Challenge Engineers are seeking an economical yet comprehensive capability which will quickly verify the connections on their PCB assemblies. As real estate on PCBs becomes scarce and devices more complex, there is a need for reliable test solutions. Traditional test methods, such as in-circuit test, are limited in their capability to access large, complex devices, such as BGA packages. Our Solution ontap Boundary Scan Software provides the latest technology for obtaining the highest interconnect fault coverage available, along with the capability to configure programmable logic devices, program FLASH memory, and test non-jtag devices, such as SDRAM and DDR memory. ontap Product Outline ontap s three main screens guide the user through test development, debug and run-time test. Software tools include: automatic boundary scan Test Program Generation, Test Execution along with boundary scan diagnostics, interactive boundary scan debugging, In-System Programming (ISP), in-circuit ATE test translators, and a FLASH Programming and ISC (In System Configuration) module. ontap runs USB port applications with the ontap TAP CONNECT JTAG Cable. All licenses are portable, with three portability options available. The ontap TAP GPIO Serializer allows JTAG distribution to multiple JTAG ports of different voltages and locations providing all logic level voltage translations and buffering. ontap Boundary Scan Test Software system requirements: MS Windows 7, 8.x 6 GB of RAM > 5 GB available disk space USB 2.0 only with Windows 7 USB 2.0, USB 3.0 with Windows 8 5

Key Features Complies with IEEE Std. 1149.1 Complies with IEEE Std. 1149.6 tests for differential pairs with capacitive coupling Supports over two dozen industry-standard CAD and netlist formats True Parallel Test Support Module to facilitate development and test for multiple UUTs simultaneously Jumpers and Guards tools provide flexible user intervention BSDL file syntax and semantics checks Automatic boundary scan test generation (ATG) detects all infrastructure, interconnect, cluster, and memory related faults Translator for SVF files and FLASH binary files Pin level diagnostics ProScan Analysis and Debug Environment Waveform display, plus many debug and analysis tools Netlist Browser Pin wiggling Change test plan settings and recompile Breakpoints, single-step, loop Application mode sampling and appxam Group nets and pins related in test solution Shows cell-level values and controls each pin for each test vector step Relates SVF test scans to waveform display Many debug and analysis tools Comprehensive reports of board test coverage showing Infrastructure Interconnect, opens, stuck-at, shorts, faults Control panel to merge fault reports from selected tests FLASH programming module Control panel allows run-time changes to data files and settings. Portable License Option Embedded in USB dongle or TAP CONNECT JATG cable Network License Manager ontap Dual Channel TAP CONNECT JTAG adaptor Cables.9V to 5V 30MHz TCK rate Internal and external voltage references Support independent JTAG chains Self-test Manufacturing Test Only licensing ISP - In-system programming from Vendor SVF files JTAG test and programming Flexible TestPlan FLASH memory programming TAP Integrity tests Interconnect tests (opens, shorts) Exclusive Mid-State Shorts Detection Test Pull-up and Pull-down resistor tests Reads and writes industry-standard SVF file High-level DTS test scripting language with flow control statements for non-jtag test and FLASH programming Cluster and Memory Testing project independent reusable models powerful, flexible C-like modeling language Graphical interface runs with Windows 7 & 8.x ontap TAP CONNECT JTAG cable run multiple chains simultaneously Tests differential pairs with capacitive coupling High-level debugger and test pattern analysis User Defined Tests Bus Management--built-in safety and control of buffer/transceiver enable and direction pins Safe Mode, where only nets having defined devices are tested Transparency feature bypasses series resistors and buffers between boundary scan pins DLL and batch-mode control from test executives, such as LabView C++, C#, and VB links and demo programs 6

Key Features (cont d) Run-Time Test Environment Go/No-go testing includes pin-level diagnostic messages Fault detection and isolation to the net and pin levels ProScan Enhanced Test Environment Net Browser and Pin Wiggler Burn-in mode Repeat tests Data logging User-Defined Tests User Defined Tests for BIST and BSDL private registers User-defined scans to set static values Retry on Fail Program cable self-tests Burn-in mode Debug controls that allow looping and user breakpoints ProScan Net Browser and Pin Wiggler Waveform display with breakpoints and single-step Custom GUI dialogue controls to suit user s application requirements Essential Utilities and Tools Netlist Composer Merge Netlist tool Test Reports shows drive/sense/fail information at each pin and net for each SVF scan Viewer-linked essential files SVF File composer for User-Defined tests Summarize testability and fault coverage reports Critical Circuit and Testability Analysis Jumpers transparent devices between boundary scan pins Identifies JTAG chains Guards interfering buffers on boundary scan nets Hardware ontap TAP CONNECT JTAG Cable available for USB ports USB-based Portable License TAP GPIO Serializer Dynamically controls direction and enables pins on transceivers between boundary scan pins ShowMe! Technical Support Responsive technical support puts customers first Each license includes one full year of technical support Pending: Support for the 2013 IEEE 1149.1 Std. Support for segmented registers, custom scans and initialization scans now available 9

ontap s UI Organization ontap has three screens for creating, running and debugging boundary scan test programs. The screens may be selected from ontap s toolbar menu or from the home page. Figure 1: The main screens organize project tasks. 9

ontap s GUI Screen Views ontap has three screens for creating, running and debugging boundary scan test programs. The screens may be selected from ontap s toolbar menu or from the Home view. The Development screen is where test programs are created. When accessed, 9 notebook-style property pages collect and organize essential boundary scan information (Figure 2). Figure 2: The 9 organizational pages provide the user with a logical, step-by-step guide to test development. The Test screen is where boundary scan tests, cluster tests, flash programming, and in-system programming are performed. Multiple tests may be selected, ordered, and run together. Pin level diagnostic messages show the location of board faults A burn-in feature allows tests to be cycled while a test log is maintained. License may be set for Manufacturing Test Only The ProScan screen provides an integrated development, tests and debug environment in which tests may be run, debugged, and pin values observed. Capabilities include: View cluster test programs View Waveform of SVF files test patterns Set breakpoints and run tests to breakpoints Single step program while observing values of pins, pin groups and variables belonging to cluster test models. Wiggle pins Run application mode signals Use appxam to create cluster tests based on application mode signals Change tests plan settings, such as guards, and recompile 10

Development Screen ontap s Development environment begins with the Projects screen, as shown in Figure 2. It is used to develop boundary scan Serial Vector Format (SVF) files for interconnect test, cluster test and FLASH programming. (Cluster test development and Flash programming are included as standard features in the license configuration.) ontap s intuitive notebook-style pages (Figure 3) organize critical test development tasks and data. The notebook-page design ensures that mission-critical tasks are accomplished. Figure 3: ontap s Development Screen with the Projects page opened. 11

The Test Screen Once the boundary scan tests have been developed and the files loaded, the tests may be run by utilizing the Test screen (Figure 4). Figure 4: Test and programming files are run from the Test screen. 12

ProScan Screen ProScan provides an integrated environment to view, run, and debug tests. After browsing to and loading an SVF vector file, the Test Vectors panel provides a quick view showing which nets and pins have been tested as well as the current status of guards settings and pin properties, such as safe or non-populated, settings (Figure 5). Many tools facilitate debug and development, including break-points, single-stepping, setting guards and pin properties, browsing a circuit, pin wiggling, guards editing, recompiling, and application mode signal sampling. The top right view of the ProScan screen provides controls to select and run SVF files and to show test programs and waveforms associated with SVF files. When running an SVF file for test or programming, associated test messages are shown in the upper left view. When selecting an SVF to show waveforms, the test program, test signals, (i.e., nets and pins), waveforms and cluster test variables are shown in the bottom three split screen views. The bottom left view shows test programs and allows breakpoints to be set. Programs can run up to the breakpoint and then be single-stepped. Figure 5: An integrated screen allows quick access to views and controls for testing, debug, and development. 13

Development Environment ontap s Test Development Environment provides the tools to develop boundary scan projects and tests within projects. Included in the development environment are: Over two dozen netlist readers BSDL syntax check BSDL-circuit location match-up Jumper and transparent device management Static constraints (guards) for each pin Customizable tests Testability warnings and reports Automatic Test Generation for IEEE 1149.1 and IEEE 1149.6 AC testing Clicking the Develop button brings up the Development screen. The Development environment is composed of 9 notebook style Property Pages (Figure 6). The screen s notebook pages are designed to intuitively bring together essential information required to automatically produce comprehensive boundary scan tests. Tests are established by following the notebook tabs from left to right. After clicking Ok to accept the settings on a page, its tab image turns to green (Figure 7). The focus then shifts to the next page. Context help for each page is available by pressing the F1 key when a page has the focus. Figure 6: The notebook tabs guide test development. When one task is complete, the tab turns to green and advances the user to the next task. Figure 7: All tasks have been successfully completed, as indicated by the green tabs. 14

Projects Page Projects and tests within projects are specified on this page. Settings for each test are developed on the succeeding pages. Settings are specific to each test and are saved in a project s project_settings subdirectory as text files. Settings related to an existing test can be copied to a new test name using the Copy Settings tool. After test selections have been made, clicking Open will advance to the next task. Figure 8: Test development begins on the Projects page. 15

Scan Page BSDL files within a project folder are checked for syntax and semantics when entering this page. Drag-and-drop procedures can be used to match BSDL files to JTAG devices and then to order JTAG devices in chain order. An Auto Detect procedure, as well as connectivity from netlists, assists in defining JTAG chains (Figure 9). Figure 9: Use the Scan page to check BDSL file syntax, match BSDL files to JTAG devices and define JTAG chains. 16

Non-Scan Page The Non-Scan page provides information for non-jtag devices and nets. Power and ground nets are identified. ontap provides models for buffers, transceivers, resistors, and logic elements which can be matched to PCB locations. In addition, devices can be tagged as non-installed, safe, or associated with an ontap DTS cluster model, e.g., related to memory test or flash programming. If the Safe test strategy is selected on the Settings page, then only safe devices are tested. Safe devices consist of: JTAG devices, parts matched to ontap models, or devices marked as Safe by a user. The non-jtag model associations allow ontap to calculate test solutions through circuits consisting of modeled devices during automatic test generation. To match a model to one or more devices select the user devices and then drag and drop the ontap model over the selected devices. Right click on a model for a short-hand representation of its functionality. Figure 10: Types of nets and non-scan devices are identified on the Non-Scan page. Right click on a net or group of nets to assign, power, ground, Vref, no-test etc. Right clicking on a model shows the mapping and logic for a model. Right click on a User s Non JTAGs to set attributes for a device. 17

Jumpers Page Jumpers represent connections on a board that are not found in a user s netlist. To add jumpers, click within the From Device -From Pin window, then match up in the To Device-To Pin lists to add jumpers (Figure 11). When selections have been made, the jumpers will show in the Jumpers Summary panel. To delete jumpers, right click the jumper entry from the Jumpers Summary panel to access the menu. Figure 11: Use the Jumpers page to add jumpers connections on a board not found in the netlist. 18

Guards Page The Guards page (Figure 12) is used to assign static or vector-by-vector pin constraints to selected pins or on a device-by-device basis. Guards are required when certain pins, (e.g., memory selects), must be held at a static value throughout a test. Guards are also valuable when debugging, because they allow selected pin drivers to be turned on or off. Figure 12: The Guards page showing the menu to assign pin constraint values. 19

Cluster Page The Cluster page is where devices and cluster test models are selected for cluster (functional) test and flash programming. In addition, assignment of boundary scan pins to cluster device pins, based on Digital Test Syntax (DTS) cluster models, can be validated as well as changed. This page may be ignored for tests such as interconnect that are unrelated to cluster testing. When multiple boundary scan pins are available on a net, this tool allows a selection of boundary scan pins for given cluster device pins. ontap presets the selections or automatically assigns boundary scan pins when a choice is not available. ATG will work its way through non-jtag logic between cluster device pins and boundary scan pins in order to find applicable pins. The user may elect to override ontap s selection with the User Assigns feature. Package pin assignment lists may be inserted into DTS model headers so that the models themselves are reusable independently of specific device packages. The DTS Test Program Format for Cluster Test document in ontap Help describes DTS modeling. Figure 13: Cluster page allows a user to select devices and cluster models for cluster test and Flash programming. 20

Testability Page The Testability page (Figure 14) is used to alert users to conditions such as TAP pins connected to power or ground and cluster test pins that cannot be controlled as required in a test program. When ontap detects testability issues, the page s tab will flash red. This page is concerned only with testability issues and does not report fault coverage issues, which are obtained in the.rpt files and in the Testability Survey.txt file. To dismiss a testability message, first address the issue, then click on it so that it does not continue to contribute to the flashing red image. Figure 14: The Testability page tab will flash red when ontap detects testability issues. 21

TestGen Page The TestGen page allows users to flexibly configure Test Plans for both interconnect and cluster tests before clicking Create Test to initiate the automatic test generation process. ontap s TestGen automatically crafts compact test patterns that provide pin-level fault detection messages for all boundary-scan testable nets on a printed circuit board (PCB). TestGen also creates test vectors to detect faults on the pins of non-scannable components such as clusters, memories, serial, and pull-up/down resistors that are accessible from scannable devices Test Only Safe Circuits may be selected so that tests are not created on nets having unsafe devices. Devices are considered safe if they are JTAG parts, assigned an ontap logic or cluster test model, or have been designated as safe on the Non-JTAG page. Figure 15: The TestGen page showing the TestPlan, center panel, Available Instructions, left, and OPCODE lists, right. 22

TestPlan The TestPlan governs the test program (SVF file) produced by ontap s automatic test generation (Figure 16). A broad range of options are available and instructions from the Available Instructions list may be inserted using a drag-and-drop procedure; for example, a script text file or another SVF file may be inserted. Figure 16: TestGen s TestPlan, center panel 23

Available Instructions In addition to the options available in the Test Plan, Instructions from the Available Instructions list (left panel) may be dragged and dropped into the Test Plan (center panel). The opcode assigned to any JTAG device s instruction register can easily be changed by selecting the device in the Test Plan and then selecting an OPCODE from the TAP OPCODES list (lower left panel). Figure 17: Items from the Available Instructions list may be dragged and dropped into the TestPlan. This provides the flexibility, for example, to insert batch control and data files for boundary register initialization when required. 24

Test Environment Once tests have been developed, the Test environment allows for execution of SVF files for test, flash programming and configuration (Figure 18). In addition, cables may be tested with the Test and Programming Cable feature found under Tap Connect (Figure 33). Figure 18: The Test screen allows for execution of SVF files for test, flash programming and configuration, as well as a selftest feature to test the TAP CONNECT JTAG Cable. Key Features of the Test environment: A scan sequencer which allows multiple SVF files to be selected and run together. The files may be dragged and dropped into a desired order Diagnostic messages are presented to the pin level A project selector and a selection list of tests within each project Test setup messages may be added for each test Auto Detect queries JTAG chain and discovers JTAG chains based on available BSDL files Multiple UUTs True Parallel Test Setup parallel tests Ref setups for Multiple UUTs Burn-in testing and logging ontap TAP CONNECT JTAG Cable self-test Flash Control panel Generates detailed test report Flexible presentation shows adaptor cable assignments when loading tests and test status when running tests Run-time Controls Stop after MAX fails Loop test Set retries-on-fail count View failure and test reports Options to control when test and diagnostic reports are produced A deployment (Deploy Menu) moves essential runtime files to a test_files_for_deployment directory 25

Selecting a Project Folder From the Test screen, selecting the Projects button will display a list of user projects in the right hand panel. Figure 19: Projects may be selected from a user s project list. 26

Selecting a Project Folder (cont d) Selecting a project folder will then list the SVF files in that project folder. Upon loading, the TAP CONNECT channel assignments on the ontap CONNECT JTAG Cable are shown, as seen in Figure x Figure 20: With the project loaded, SVF files and TAP CONNECT channel assignments are shown. 27

Selecting and Running the Test Select a test or group of tests to run, then click Go (Figure 21). Figure 21: Selecting and running one or more SVF files. Figure 22: Test and diagnostic messages are presented in the Message window. 28

The Test Status After selecting Go to run the test, test and diagnostic details are shown in the Messages panel (Figure 23). The details may also be seen by clicking the View Fails or Reports button. View Fails shows pin level diagnostic messages, while Reports shows pin-by-pin and vector drive and sense test details Figure 23: After a test has been run, View Fails and Reports show test and diagnostic details. 29

Parallel Test Control Parallel Test controls, when enabled in licensing, enable true parallel test. The Multiple UUT setting on the Development screen s TestGen page help organize test files for parallel test. The controls here provide the user with a convenient means of assigning SVF files to specific ontap JTAG USB adaptor pod channels and then to run the tests simultaneously. Figure 24: The Test screen with an expanded view of parallel controls. 30

Burn-In Mode The Burn-In button (Figure 25) pops up a dialogue that controls settings for burn-in testing (Figure 26). The execution of one or more tests is continuously repeated and a burn-in log with test and diagnostic messages is maintained. Figure 25: Accessing Burn-in mode controls Figure 26: Burn-in and test settings 31

Flash Control Selecting the Flash control button (Figure 27) will display the panel where run-time settings, such as data files and TCK rates, can be changed (Figure 28). Figure 27: Accessing the Flash Control panel. Figure 28: The Flash control panel allows run-time settings changes when programming Flash memory. 32

Auto Detect JTAG Auto Detect JTAG Chain Auto Detect interrogates the TAP and calculates a chain based only on BSDL files present in the designated folder and independently of netlist files. Results are shown in the Message box (Figure 30). Figure 29: Selecting Auto Detect to find a JTAG chain Figure 30: Auto Detect initiates a query sequence in which ontap searches for and reports a JTAG chain at Channel A. 33

View Fails and Report Selecting the View Fails button will display the.fail file in the text editor. The.fail file provides summarized pinlevel diagnostic messages for interconnect tests related to the following types of circuit faults: Opens faults between specific pins Shorts faults between specific nets Stuck-at faults where a pin is stuck high or low. Pull resistor faults Mid-state (resistive) faults AC as well as DC faults based on support for the IEEE 1149.6 standard. Selecting the Report button will display in the text editor a detailed test report for an SVF file after a test is run. Figure 31: Accessing the View Fails and Report from the Test screen. 34

Prompts The Prompts button can be used to provide instructions that will appear in the Message panel when a user runs an.svf file (Figure 32). Figure 32: Selecting Prompts brings up a dialogue box where prompts may be entered. Figure 33: A sample of a series of prompts that will appear in the Message panel for a user running the tests. 35

Tap Connect The Tap Connect button (Figure 34) displays the cables menu dialogue box. SVF files can be matched to TAP CONNECT channels and TCK rates can be set. Settings are saved in adaptor_<test_name>.txt I files (Figure 35). Figure 34: Selecting the Tap Connect will display the Cables menu dialogue. 36

Tap Connect and Self-test Figure 35: Selecting the Tap Connect will display the Cables menu dialogue. Test Your Cable provides a simple loopback test from TDO pins for the selected TAP letter designator. 37

ProScan ProScan s integrated screen allows quick access to views controls for testing, debug, and development. Figure 36 shows waveforms for a test. Figure 36: ProScan s waveforms panel provides a visual of signal activity on a test that has run and passed. 38

Waveforms As seen in Figure 37, Waveforms show drive and sense test values at each scan pin for each test vector. Clicking on test signals brings together pins and their waveforms that are related in a test solution. In Figure 35, yellow represents drive values and green represents expected capture values. If a test fails, related capture values are shown tinted red (Figure 38). Figure 37: Waveform display showing drive and sense values, with yellow representing drive values and green representing expected capture values. Figure 38: When a test is run, failures show up in ProScan s Test Messages box. Clicking on a scan pin (U1.T7) will locate the failing pin in the Nets +Pins panel, as well as show the failure in the waveform views. The red tint in the waveforms shows the failing test values. In this example, a DIP switch was set to cause a failure condition. 39

Net Browser The netlist browser provides a convenient way to check circuit connections on nets and from device to device. Figure 39: Clicking on a pin in the Nets and Pins list will also select the pin in the netlist browser when Browse Circuit is selected. 40

appxam ProScan s appxam control panel (Figure 40) helps create DTS functional tests based on sampling application mode signals. Signal qualifiers can be set so that samples are included in a test only if the logic conditions of selected pins are true. Selecting the Compile button creates a functional test based on the qualified samples. Figure 40: ProScan s appxam control panel. Figure 41: An example of sampled clock signals when appxam is sampling. 41

Guards + Attributes Setting guards on critical signals during boundary scan tests can help avoid contention and failures. When ProScan shows failure locations, the Net Browser can help trace through a circuit to find the source of a problem, for example a Flash memory device whose data bus needs to be guarded off during a test. In ProScan, guards can be set by simply selecting a pin and then selecting the appropriate guard in the Guards list. The Compile and Run Test buttons below the Guards list facilitate recompiling a test and running the test without leaving the current screen context. Figure42: Setting guards, recompiling, and retesting. 42

Pins+Cells Mousing over a waveform signal shows detail information about the nature of the related boundary register cell and its current status with regard to driving and capturing signals. Figure 43: Use Pins+Cells to view detailed information about related boundary register cells. 43

Commands A list of commands is available to select from many functions, such as running and compiling tests and wiggling pins. Figure 44: ProScan s Commands list. 44

Breakpoints and single-stepping Breakpoints may be set in the Program panel and tests single-stepped from the breakpoint. Program variables as well as waveform signal values are shown when running DTS cluster tests. Right clicking on a Test Program step provides a menu to set a breakpoint, and then clicking Go runs the test up to the breakpoint. The Step button allows a program to be single-stepped from the breakpoint. Figure 45: Setting breakpoints and single-stepping in a Test Program. 45

ontap Tools ontap offers a variety of tools that are essential when developing many boundary scan projects. The Tools menu is accessed from the ontap toolbar. Figure 46: Access the Tools menu from the toolbar. 46

BSLD Syntax Check While ontap checks the syntax when a project is loaded on the Development screen, the BSDL Syntax check can be used to independently check a BSDL file s syntax without first loading a project in Development. DTS Syntax Check Figure 47: When the BSDL Syntax Check tool has been selected, locate the BSDL file, click Open. Any warnings will be shown in a text editor. The DTS syntax can be easily checked in a similar way as the BSDL Syntax Check. Figure 48: When the DTS Syntax Check tool has been selected, browse to the DTS model. When the model is loaded, any errors will be reported in the Check Syntax window. Errors may be viewed in the text editor. 47

Compose Netlist The Compose Netlist (Figure 49) tool uses a two-step process-- Compose and Join Nets--that allows the user to compose a netlist from BSDL files, DTS cluster test models, and ontap s logic models. This tool can be used to create a new netlist or to add devices to an existing netlist. Pins, such as those in FLASH memory, are assigned to JTAG I/O pins. The Compose Netlist tool is particularly useful in facilitating applications that require only the capability to program FLASH and when the test developer does not have access to a CAD netlist. Once the Compose Netlist tool is accessed from the Tools menu, the user will be asked to open the project folder. Circuit locations are added, then matches to either BSDL, DTS or Logic files are required. After the selections are made, an option to Create New Netlist or Insert Into Netlist is given. The second step is accessed by clicking the Join Nets tab. Figure 49: The Compose Netlist tool can be used to create a new netlist or to add devices to an existing netlist. 48

Test Report Files When a test is run ontap produces a <file_name>.test file which is useful for debug. This file parses SVF files and shows drive and capture values at each JTAG I/O pin for each test vector (scan). It superimposes test faults on drive/capture values showing where they occurred during a test. At a glance, the file shows which pins are tested or not tested and, following test execution, shows where in a test failures occur (Figure 50). Figure 50: A sample <file name>.test report file. 49

Merge Netlists The Merge Netlist utility (Figure 51) is especially useful for applications with Multi-Chip Modules (MCM) and when one type of daughter board is used at multiple mother board connectors. The tool allows for two or more netlists to be merged (Figure 52). In instances where one netlist will be merged multiple times, a separate netlist must exist in the merge folder for each instance where the netlist is merged. Figure 51: The Merge Netlist tool. Figure 52: Merging two netlists. 50

Compose SVF File The Compose SVF File tool (Figure 53), accessed from the Tools menu, is used in conjunction with User Defined Tests. Tests may be defined in script files which may then be translated into executable Serial Vector Format (SVF) files. The general approach is to place all of the required BSDL files into a folder and then to relate the BSDL files to circuit locations in declarations at the beginning of the script file. Once BIT_STRINGS are defined, instruction register scans may be created by simply declaring the instruction names to be used. Data scans can be created by concatenating BIT_STRINGS. String variables may be assigned values and then multiple variables may be concatenated. In addition, literal string assignments may be used directly or mixed with variables. Values are always expressed as binary strings, BIT_STRINGS. If zero and one values are present in a TDO string, the corresponding MASK bits will be set to one. If X characters are present in a TDO string, the corresponding mask bits are set to zero Figure 53: Compose SVF File. 51

Summarize and View Test Reports The Testability Survey (Figure 54) compiles overall fault scores for a project that may consist of many individual tests. It presents testability warnings, a pin-by-pin review of fault coverage, and a summary of fault coverage. Reports show fault coverage on a pin and net basis as well as well as on a device basis. Figure 54: Sample Testability Survey Report. 52

Add Alternate IDCODES When alternate IDCODES are required, use the Add Alternate IDCODES menu item located in the Tools and in the test menus. This tool reads the IDCODES in a project, shows any failing bits, and allows measured values to replace original IDCODES as an alternative. Figure 55: The Add Alternate ID Codes tool is located in both the Tools and Test menu. 53

Debug Tools ShowMe! When enabled from the Debug menu, writes a parsed list of test values for each pin and variable in a cluster test to a specified data capture file. The list shows the values in relation to DTS instructions as a test runs. The captured data represent actual values driven and captured from scan pins and are best viewed in a text editor having vertical and horizontal screen splitters such as Textpad or in an Excel spreadsheet. Figure 56: When a test runs, ShowMe! will capture all the variable pin values designated in the ShowMe! control dialogue. 54

Log TDO Hex DATA to file scandata.txt When selected in the Debug menu, Log TDO HEX Data causes all scan data to be written to a scandata.txt file in a project folder. A ^ character tags failing bits in TDO data. ProScan, described in a previous section, test reports, and messages instrumented in cluster tests are particularly helpful during debug. Figure 57: Access the Log TDO HEX DATA from the Debug menu. 55

Board Netlist Translators A list of accepted Board Netlist Files CAD Source ACCEL EDIF Agilent BOARD STATION Cadence Allegro Cadstar FabMaster GenCad GenRad Isis Mentor Neutral Mentor Veribest EDIF Orcad PCAD PADS PowerPCB PC Easy Cadence PST Protel2 Teradyne Teradyne Victory ViewLogic Allegro ViewLogic Generic Zuken Vistula Other EDIF Files / File Extension.edf.board or.board x / y.net and.pkg.net.net and.frs nets.asc + material.asc.net ckt.sdf.neu.edf(or rename.asc-> EDF).net.net.asc or.net.net three pst files.net Ipl.dat.cds.net.net &.pkg.rep +.lst.edif format 56

Menu Selections 57

Hardware TAP CONNECT JTAG Cable The TAP CONNECT JTAG Cable provides JTAG test and programming support for ontap Boundary Scan Software. It offers higher speeds and simplified operation in both single and multiple chain (multiple cables) applications. The cable may be used for the following applications: JTAG Test, including memory and cluster test Flash programming FPGA, CPLD and PROM configuration General purpose I/O The TAP CONNECT JTAG Cable also provides the capability to run two chains at speeds up to 30MHz. The TAP CONNECT JTAG Cable includes either two ribbon cable headers for direct connection to Xilinx, Altera and other style headers, or two flying lead connectors. The TAP CONNECT JTAG Cable attaches to a USB port on a PC with a Hi-Speed USB A-to-Mini cable. Features of the TAP CONNECT JTAG Cable: Supported on ontap and Windows Attaches to USB ports and hubs with off-the-shelf Hi-Speed USB A-A cables Derives all power from USB ports and hubs. Target board Vref voltage provides power only for JTAG pin drive Automatically senses and adapts to target I/O Voltages Adjustable Internal voltage source as alternate Vref Interfaces to devices operating at 0.9 to 5.0 VDC JTAG pin currents +/- 24mA Adjustable TCK clock from 200KHz to 30MHz Drivers provided Compatible with Xilinx Platform Cable USB flying wire leads and High Performance Ribbon Cable JTAG pins compatible with the Xilinx Platform Cable USB, including TCK, TMS, TDI, and TDO. Tri-state, drive, and sense available on the INIT pin Cable adapter available for Altera and other custom headers Hot plug and play Operates in ontap single chain and multi-chain / multi-cable JTAG applications LED indicators show status of both Vref and Cable voltages Suspend state or loss of Vref tri-states outputs on all pins 58

ontap TAP GPIO SERIALIZER The ontap TAP Serializer was designed to allow JTAG distribution to multiple JTAG ports of different voltages and locations providing all logic level voltage translations and buffering. Flynn Systems offers several adapter cables for standard JTAG ports as well as custom adapters. The TAP Serializer allows connectivity from a single host JTAG port and provides up to four independent output ports, with each one capable of operating at any voltage from +1.5VDC up to +5VDC. This eliminates the need for the user to provide level translators and routing logic in their application that is typically used only in bringing up the board and not used during normal circuit operation. The Serializer takes the JTAG source channel from any host JTAG port (must be capable of operation at +3.3V or self-powered) and routes it through level translators to provide up to four, daisy chained, JTAG I/O channels. Each output channel is designed to operate from any voltage from +1.5VDC up to +5VDC. Serializing is performed by routing TDO of the first channel to TDI of the next through the use of jumpers. Each channel has a jumper that, when left open (shunt not installed), passes the data to the next channel. Installing the jumper at any of the channels routes TDO back to the host TDI and thereby selects that channel as the end of the chain. This provides an option to use 1, 2, 3 or 4 channels or select the daisy chain output port to the next Serializer. One channel can be useful when your JTAG port only operates at a fixed voltage. The Serializer then provides the level translators necessary to drive lower voltages without signal degradation. The Serializer operates from a +5VDC wall adapter. Two DC Jacks allow the use of a single wall adapter to power multiple Serializers. A jumper cord (available as an accessory) can be used to jumper power from Serializer to Serializer without the need for multiple wall adaptors that clutter up your power strip. LED indicators for status include a power indicator for the unit and two LEDs per channel that indicate target attached and activity 59

Technical Support Technical Support Flynn Systems Technical Support for ontap can help you get your boundary scan projects up and running quickly! A successful transit through the path in the illustration can be accomplished within a day, often within hours. Given that the source netlist and BSDL files are available and a programming cable is available, the process is straightforward. Although we encourage ontap users to bring applications up themselves, our Technical Support can provide detailed interactive assistance during this process so that the time to achieve a PASS is significantly cut. In addition, context-driven on-line Help is available throughout the ontap screens. Telephone and email support available during business hours. Most issues resolved within one business day. Telephone and on-line assistance bringing up new applications. Screen Share sessions available On-line program updates available for new ontap builds. Assistance with memory/cluster test models. Assistance with FLASH programming models. 60