Logic esign ( Part ) Sequential Logic- Finite State Machines (Chapter ) Based on slides McGraw-Hill Additional material 00/00/006 Lewis/Martin Additional material 008 Roth Additional material 00 Taylor Additional material 0 Farmer Additional material 0 Narahari uick summary Combinational logic circuits Basic gates (OR, AN,.) Combinational devices (Multiplexers, ecoders, Adders, ) We now have a storage device -Latch Implementation of registers and memory Using -latches ok now back to sequential circuits and state machines Recall examples of Vending Machine and Counter Finite State Machines The behavior of sequential circuits can be expressed using characteristic tables or finite state machines (FSMs). FSMs consist of a set of nodes that hold the states of the machine and a set of arcs that connect the states. irected graph to represent a FSM State Machine type of sequential circuit Combines combinational logic with storage Remembers state, and changes output and state at each clock cycle based on inputs and current state State Machine Moore and Mealy machines are two types of FSMs that are equivalent. They differ only in how they express the outputs of the machine. Moore machines place outputs on each node/state Associate an output with each state Mealy machines present their outputs on the transitions. Inputs Combinational Logic Circuit Storage Elements Outputs
States in a FSM The concept of state the state of a system is a snapshot of all relevant elements at a moment in time. a given system will often have only a finite number of possible states. For many systems, we can define the rule which determines under what conditions a system can move from one state to another. So when do they change states? Random times? Only at specific times? Are we ready to design sequential circuits and finite state machines? Is something missing? When do states change in a machine? o we let states change at arbitrary times? What do you think happens in a computer? ed Flip-Flops/Circuits Subsystem in a computer consists of a large number of combinational and sequential devices Each sequential device is like latch which is in one of two states As machine executes its cycle, the states of all sequential devices change with time To control large collection of devices in an orderly (synchronized) fashion, machine maintains a clock Requires all devices to change their states at the same time generates sequence of pulses Much easier to design, debug, implement, and test How do we change latches so that they allow change in state synchronized with the clock? Sequential logic circuits require a means by which events can be sequenced..clock! Introducing - The! A clock controls when stored values are updated Electrical waveform sends pulses through a circuit Oscillating global signal with fixed period 0 One Cycle The clock will act as the heartbeat of our system The number of cycles per second is the clock frequency measured in cycles per second or Hertz (Hz) The clock period refers to the duration of one clock cycle. The period and frequency are inversely related. Typical clock frequency:.ghz =. x0 9 Hz So corresponding clock period = /(. x 0 9 ) =.x0-8 -9 sec That would be: 0. nanoseconds time
Attaching to -Latch Let s attach CLOCK to the WE on -Latch clock WE We create windows of time that we can store data into latch When the CLOCK is HIGH -latch is open When the CLOCK is LOW -latch is closed We have to prepare what we wish to store, right before latch closes open closed open CLOCK time -9 Finite State Machine In general a Finite State Machine consists of An n-bit storage (register?) which stores the state of the machine A block of logic that computes the next state as a function of the current state and the inputs, if any A block of logic which computes the output based on the Inputs current state. Next State Function State Register (storage) Combinational Logic Blocks Output Function Outputs esigning and implementing a FSM. First draw the state diagram Encode each state in binary using N bits These N bits correspond to N state variables that need to be stored. Call them S N- S N- S S 0 State diagram will show transitions from state to state based on value of inputs. Next, derive the truth table (from state diagram) inputs in truth table are N current state variables and the inputs outputs are the values of the state variables in the next state and the output at each state -- common notation is S but confusion with complement operator, so let s use S*. From truth table, derive combinational circuit (boolean function) for each of the next state values State variables are stored in your N storage elements Simple -bit Counter count from 0 to bit encoding A,B of states: 00, 0,0, Counts 00 0 0 boolean functions: A,B current state A*, B* next state A* = (A B) + (A B ) = A XOR B B* = (A B ) + (AB ) = B Two storage elements to store bits A,B Use -latches? State can change at each clock cycle Implement circuit A B A* B* 0 0 0 0 0 0 0 0
-Latch Timing iagram The diagram below is called a Timing iagram Our -Latch is previous-state dependent We can think of this as a time dependency Moving to the right on diagram, represents forward moving time The inputs & outputs to our -Latch are on left Inputs/Outputs can be either HIGH (logic ) or LOW (logic ) Think of this as a time-dependent truth table Logic level = Logic level =0 time Let s Try to Build a Counter using the -Latch We can t use a -latch to build a counter Why not? Let s say at time=0, -latch has: 00 >This is the input to incrementer, so output = 0 >Now 0 is input to the -latch Problem: >We can t guarantee the clock will be low in time to store this new value into the -latch Logic level = Logic level =0 Solving the ed -Latch problem.. we need to decouple circuit that reads current state from circuit that writes in the new/next state In one clock cycle, we can only do one read of a state and one write into the latch build a latch consisting of TWO latches One enabled during clock high to read current state One enabled during clock low to write new state Connect the two Flip-Flop (or master-slave flip-flop) Flip-Flop is a pair of latches Stupid name, but it stuck Isolates next state from current state Latch # inter WE WE Latch # Two phases: = : WE =0: Latch # closed, WE =: Latch # open = 0: WE =: Latch # open, WE =0: Latch # closed -6
Flip-Flop timing iagram Latch # inter Latch # Flip-Flop vs. -Latch We refer to the flip flop as an edge-triggered device. = ONLY when WE changes from 0 to inter WE WE L -closed L -open L -open L -closed L -closed L -open L -open L -closed This differs from latch, which is: level-triggered = anytime WE equals Timing iagram for FF: WE -7-8 -8 Flip-Flop vs. -Latch We refer to the flip flop as an edge-triggered device. = ONLY when WE changes from 0 to This differs from latch, which is: level-triggered = anytime WE equals Timing iagram for -Latch: WE Flip-Flop We can think of the Flip-Flop as a bit storage container with an input,, and an output,. The flip-flop takes a clock input (often denoted with a triangle) A set of flip-flops can be grouped together with common and WE inputs to form a register. A key component in our processor Flip-Flop -9-9 -0
Storage evices R S RS RS Latch Stores Bit, Level-Triggered - forbidden input: S=0, R=0 -Holds ata when RS= Working Counter Use a clocked register (made of flip-flops) -ff + WE -Latch Stores Bit, Level-Triggered -No forbidden inputs (fixes RS Latch) -= when WE= -Holds ata when WE=0 FF CLK -Flip-Flop Stores Bit, Edge-Triggered -No forbidden inputs -= when WE (CLK) transitions from 0 to -Holds ata for WE= or WE=0 -Except when WE transitions from -0 to - Counter Timing iagram Incrementer (+) computes the next value of the state register -ff + Finite State Machine Representation of Counter Reset 000 00 Bubbles represent all possible states for the machine (aka your flip-flop based circuit) 0 00 Arrows show movement from one state to the next 0 6-0 00 0 Transitions occur at pulse of the clock - 6
Truth Table Representation of Counter Present State Next State (t) (t) 0 (t) (t+) (t+) 0 (t+) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Finite State Machine The counter we designed is an example of a finite state machine. In general a Finite State Machine consists of An n-bit register which stores the state of the machine A block of logic that computes the next state as a function of the current state and the inputs, if any A block of logic which computes the output based on the current state. Combinational Logic Blocks Inputs Next State Function State Register Output Function Outputs - -6 One Last Thing Flip-Flop with Additional Write Enable From previous slides, we attached clock to WE of the -flip-flop Now, we add another WE line to the flip flop Just holds onto data already stored in FF Give it the ability to ignore the clock! WE 0 FF Flip-Flop w/we WE -7 Review: esigning and implementing a FSM. First draw the state diagram Encode each state in binary using N bits These N bits correspond to N state variables that need to be stored. Call them S N- S N- S S 0 State diagram will show transitions from state to state based on value of inputs. Next, derive the truth table (from state diagram) inputs in truth table are N current state variables and the inputs outputs are the values of the state variables in the next state and the output at each state -- common notation is S but confusion with complement operator, so let s use S*. From truth table, derive combinational circuit (boolean function) for each of the next state values State variables are stored in your N storage elements 7
Storage Each master-slave flip-flop stores one state bit. Example: Blinking Traffic Sign (from textbook) The number of storage elements (flip-flops) needed is determined by the number of states (and the representation of each state). Each bit can be 0 or = states N bits can represent N states Example: If a FSM has states, then the circuit needs log = storage elements. Fewer the states, less hardware needed Concept of Minimization of States for a given FSM ANGER ANGER ANGER 8
ANGER ANGER ANGER ANGER 9
ANGER ANGER Example: Traffic Sign A blinking traffic sign: How many states states No lights on & on,,, & on,,,, & on (repeat as long as switch is turned on) How many bits to represent the states S S 0 With S S 0 values: 00, 0, 0, Traffic Sign State iagram Switch off State bit S State bit S0 Switch on Outputs Transition on each clock cycle. 0
Note we really have groups of lights to be controlled = control lines X,Y,Z Group : Lights and ; controlled by Z If Z= then Group lights ( and ) are switched on Group : lights & ; controlled by Y Group : Light ; controlled by X 0 all off 0 grp on 00 0 0, all on 0 grp, on 0 When is group on? in states 0, 0 and - but only when the switch IN is on! Logic expressions for X,Y,Z epends on S 0 and S and Input is on If Input is off then X,Y,Z are al 0 can you come up with a logic expression for next state values of S 0 and S? epends on current values of S 0 and S and Input is on Input off then both bits are set to 0 since next state is 00 Next state value of S0 denoted S 0 = if current state is 00 or current state 0 and In= When do we switch to the next state? the two bits of S[:0] are updated at every clock cycle we have to make sure that the new state does not propagate to the combinational circuit input until the next clock cycle. Traffic Sign Truth Tables Outputs (depend only on state: S S 0 ) S S 0 Z Y X 0 0 0 0 0 0 0 0 0 0 Lights and Lights and Light Next State: S S 0 (depend on state and input) Switch Whenever In=0, next state is 00. In S S 0 S S 0 0 X X 0 0 0 0 0 0 0 0 0 0
Boolean functions for light control bits from truth table, consider all rows where outputs = Traffic Sign Logic Z = ((NOT S )S 0 + S (NOT S 0 ) + S S 0 ).In Y = (S S 0 + S (NOT S 0 ) ).In X = (S S 0 ).In flipflop From Logic to Processor esign Combinational Logic ecoders -- convert instructions into control signals Multiplexers -- select inputs and outputs ALU (Arithmetic and Logic Unit) -- operations on data Sequential Logic State machine -- coordinate control signals and data movement Registers and latches -- storage elements Putting it all together The goal: Turn a theoretical device - Turing s Universal Computational Machine - into an actual computer... interacting with data and instructions from the outside world, and producing output data. Smart building blocks: We have at our disposal a powerful collection of combinational and sequential logic devices. Now we need a master plan...
Recall: what are Computers meant to do? We will be solving problems that are describable in English (or Greek or French or Hindi or Chinese or...) and using a box filled with electrons and magnetism to accomplish the task. This is accomplished using a system of well defined (sometimes) transformations that have been developed over the last 0+ years. Problem Transformation - levels of abstraction The desired behavior: the application The building blocks: electronic devices Natural Language Algorithm Program Machine Architecture Micro-architecture Logic Circuits evices What Next? Next topic: The von Neumann model of computer architecture Basic components How instructions are processed The LC computer and instruction set The ISA of LC Programming the LC Assembly Language programming Chapters,,6,7