12.12.216 Chapter 5 Flip Flops Dr.-ng. Stefan Werner /14 Table of content Chapter 1: Switching Algebra Chapter 2: Logical Levels, Timing & Delays Chapter 3: Karnaugh-Veitch-Maps Chapter 4: Combinational Circuit Design Chapter 5: Latches and Flip Flops Chapter 6: Finite State Machines Chapter 7: Basic Sequential Circuits Chapter 9: Number Systems ntroduction to latches Chapter 9: Binary Arithmetic S- Elements JK-Elements Chapter 1: Binary Codes D-Elements T- Elements 2of 18 1
12.12.216 Sequential Circuits primary inputs secondary wi CSefagA or1c: combinational logic external outputs memory primary inputs feedback inputs combinational logic memory outputs from memory 3of 18 mplementation of a S-Latch S S To analyse the circuits function, cut-off the feedback loop 4of 18 2
12.12.216 mplementation of a S-Latch S S Calculate 5of 18 mplementation of a S-Latch S S 6of 18 3
12.12.216 mplementation of a S-Latch S S Calculate 7of 18 mplementation of a S-Latch S S emember: =!!!! 8of 18 4
12.12.216 mplementation of a S-Latch S S rows where = => stable states rows where => unstable states 9of 18 mplementation of a S-Latch S S input is still 1. Let = be (stable state) 2. Change input to =, S= 3. = and S = => = 4. = and = => = 5. soon after: changes to 1 of 18 5
12.12.216 mplementation of a S-Latch n practice: NO-Gates have delay => can be modeled by delay-device S f S= = and set to S== (at the same time) S latch oscilates due to dl delay times Combination =S= is forbidden 11 of 18 Truth table of a S Latch S n n+1 Functionality Both inputs are, 1 1 => the state stores n 1 The reset input is 1, 1 1 => the FF is set to. 1 1 The set input is 1, 1 1 1 => the FF is set to 1 1 1 X The FF s behaviour can not be 1 1 1 X predicted Characteristic Equation: n+1 = S + n 12 of 18 6
12.12.216 Different types of clock inputs To trigger a latch means to make it react to its inputs at a defined time. multiple possibilities to trigger a latch: levels, edges, etc. positive level negative edge/ falling edge clk negative level positive edge/ rising edge 13 of 18 Behavior of a synchronous S Latch -level triggered- The latch is positive level triggered Changes require input AND positive level 14 of 18 7
12.12.216 Behavior of a synchronous S Latch -level triggered- The latch is positive level triggered 1 2 More than one change during positive level phase are possible 15 of 18 Behavior of a synchronous S Latch -edge triggered- The latch is positive edge triggered All edge triggered elements are called flip flops!!! Latches are are always level trigged!!! SET due to change at s ESET due to change at r Nothing happens because no positive edge 16 of 18 8
12.12.216 Triggering a Flip Flop Positive edge triggered flip flops FF can change its state only at a positive clock edge => clock changes from -> Negative edge triggered flip flops FF can change its state only at a negative clock edge => clock changes from -> Two-edges triggered flip flops FF can change its state at a positive clock edge as well as at a negative clock edge 17 of 18 Triggering a latch Positive level triggered negative level triggered 18 of 18 9
12.12.216 Building a JK-FF A JK FF can easily be build using a S FF. 19 of 18 1