Introduction to Computer Engineering EECS 203 http://ziyang.eecs.northwestern.edu/ dickrp/eecs203/ Instructor: Robert Dick Office: L477 Tech Email: dickrp@northwestern.edu Phone: 847 467 2298 TA: Neal Oza Office: Tech. Inst. L375 Phone: 847-467-0033 Email: nealoza@u.northwestern.edu TT: David Bild Office: Tech. Inst. L470 Phone: 847-491-2083 Email: d-bild@northwestern.edu
Outline Finite State Machines 1. Finite State Machines 2. 3. 4. 2 R. Dick Introduction to Computer Engineering EECS 203
Word description to state diagram Design a vending machine controller that will release (output signal r) an apple as soon as 30 have been inserted The machine s sensors will clock your controller when an event occurs. The machine accepts only dimes (input signal d) and quarters (input signal q) and does not give change When an apple is removed from the open machine, it indicates this by clocking the controller with an input of d The sensors use only a single bit to communicate with the controller 3 R. Dick Introduction to Computer Engineering EECS 203
Word description to state diagram We can enumerate the inputs on which an apple should be released For d, i = 0, for q, i = 1 ddd + ddq + dq + qd + qq d(dd + dq + q) + q(d + q) d(d(d + q) + q) + q(d + q) 0(0(0 + 1) + 1) + 1(0 + 1) 4 R. Dick Introduction to Computer Engineering EECS 203
Word description to state diagram 0(0(0 + 1) + 1) + 1(0 + 1) 0 1 A/0 0 B/0 0 C/0 1 1 0 D/1 1 E/0 0 1 5 R. Dick Introduction to Computer Engineering EECS 203
Word description to state diagram 0(0(0 + 1) + 1) + 1(0 + 1) X 0 C/0 X A/0 0 B/0 1 D/1 1 E/0 X 5 R. Dick Introduction to Computer Engineering EECS 203
Word description to state diagram 0(0(0 + 1) + 1) + 1(0 + 1) X 0 C/0 X A/0 0 B/0 1 D/1 1 5 R. Dick Introduction to Computer Engineering EECS 203
State diagram to state table next Current state state i=0 i=1 output (r) A B E 0 B C D 0 C D D 0 D A A 1 E D D 0 6 R. Dick Introduction to Computer Engineering EECS 203
Moore block diagram outputs combinational logic sequential elements feedback combinational logic inputs 7 R. Dick Introduction to Computer Engineering EECS 203
Mealy block diagram sequential elements outputs feedback combinational logic inputs 8 R. Dick Introduction to Computer Engineering EECS 203
Moore FSMs Finite State Machines 0 1 1 A/0 B/0 0 1 0 0 1 D/1 C/0 9 R. Dick Introduction to Computer Engineering EECS 203
Mealy FSMs Finite State Machines 1/0 A 1/X B 0/0 D 0/0 0/1 1/0 0/1 C 1/1 10 R. Dick Introduction to Computer Engineering EECS 203
Mealy tabular form s + /q s 0 1 A D/0 B/X B C/1 B/0 C A/0 B/1 D C/1 C/0 11 R. Dick Introduction to Computer Engineering EECS 203
FSM design summary Specify requirements in natural form Manually derive state diagram Automatic way to go from English to FSM, however more theory required Can minimize state count, however, more theory also required See me if you want more information on this, or take a compilers course and a graduate-level switching theory course, or take my ECE 303 Assign values to states to minimize logic complexity Optimize implementation of state and output functions 12 R. Dick Introduction to Computer Engineering EECS 203
Outline Finite State Machines 1. Finite State Machines 2. 3. 4. 13 R. Dick Introduction to Computer Engineering EECS 203
Back to latches Finite State Machines Latches: Level sensitive Flip-flops: Edge-triggered 14 R. Dick Introduction to Computer Engineering EECS 203
Review: Clocking conventions Active-high transparent D Q CLK Active-low transparent D Q CLK Positive (rising) edge Negative (falling) edge D Q D Q CLK CLK 15 R. Dick Introduction to Computer Engineering EECS 203
Latch and flip-flop equations RS Q + = S + R Q D Q + = D 16 R. Dick Introduction to Computer Engineering EECS 203
Latch and flip-flop equations JK Q + = J Q + K Q T Q + = T Q 17 R. Dick Introduction to Computer Engineering EECS 203
JK latch Finite State Machines K J R S R S latch Q Q Q Q Use output feedback to ensure that RS 11 Q + = Q K + Q J 18 R. Dick Introduction to Computer Engineering EECS 203
JK latch Finite State Machines J K Q Q + 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 hold reset set toggle 19 R. Dick Introduction to Computer Engineering EECS 203
JK race Finite State Machines Set Reset 100 Toggle J K Q Q Race Condition 20 R. Dick Introduction to Computer Engineering EECS 203
Falling edge-triggered D flip-flop Use two stages of latches When clock is high First stage samples input w.o. changing second stage Second stage holds value When clock goes low First stage holds value and sets or resets second stage Second stage transmits first stage Q + = D One of the most commonly used flip-flops 21 R. Dick Introduction to Computer Engineering EECS 203
Falling edge-triggered D flip-flop D D 0 Clk= =1 R Q S Q 0 D D Clock high 22 R. Dick Introduction to Computer Engineering EECS 203
Falling edge-triggered D flip-flop D D 0 Holds D when clock goes low Clk=1= R Q S Q 0 D D Holds D when clock goes low Clock switching Inputs sampled on falling edge, outputs change after falling edge 23 R. Dick Introduction to Computer Engineering EECS 203
Falling edge-triggered D flip-flop D D D Clk= = 0 R Q S Q D? 0 Clock low 24 R. Dick Introduction to Computer Engineering EECS 203
Another view of an edge-triggered DFF R Q clk S Q R Q Q R Q S Q D S Q 25 R. Dick Introduction to Computer Engineering EECS 203
Edge triggered timing 100 D CLK Qpos Qpos Qneg Qneg Positive edge t riggered FF Negative edge t riggered FF 26 R. Dick Introduction to Computer Engineering EECS 203
RS clocked latch Storage element in narrow width clocked systems Dangerous Fundamental building block of many flip-flop types 27 R. Dick Introduction to Computer Engineering EECS 203
JK flip-flop Finite State Machines Versatile building block Building block for D and T flip-flops Has two inputs resulting in increased wiring complexity Edge-triggered varieties exist 28 R. Dick Introduction to Computer Engineering EECS 203
D flip-flop Finite State Machines Minimizes input wiring Simple to use Common choice for basic memory elements in sequential circuits 29 R. Dick Introduction to Computer Engineering EECS 203
Outline Finite State Machines 1. Finite State Machines 2. 3. 4. 30 R. Dick Introduction to Computer Engineering EECS 203
Finite State Machines Mechanical switches bounce! What happens if multiple pulses? Mutliple state transitions Need to clean up signal 31 R. Dick Introduction to Computer Engineering EECS 203
Schmitt triggers Finite State Machines A B High A Low 32 R. Dick Introduction to Computer Engineering EECS 203
Schmitt triggers Finite State Machines A B High V TH A V TL Low 32 R. Dick Introduction to Computer Engineering EECS 203
Schmitt triggers Finite State Machines A B High V TH A V TL Low 32 R. Dick Introduction to Computer Engineering EECS 203
Schmitt triggers Finite State Machines A B High V TH A V TL transition Low 32 R. Dick Introduction to Computer Engineering EECS 203
Schmitt triggers Finite State Machines A B High V TH A V TL transition B Low 32 R. Dick Introduction to Computer Engineering EECS 203
Finite State Machines 5 4 Schmitt trig. RC 0.75 1.65 3 V 2 1 0-1.0e-03-5.0e-04 0.0e+00 5.0e-04 1.0e-03 1.5e-03 T (s) 33 R. Dick Introduction to Computer Engineering EECS 203
Outline Finite State Machines 1. Finite State Machines 2. 3. 4. 34 R. Dick Introduction to Computer Engineering EECS 203
Assigned reading M. Morris Mano and Charles R. Kime. Logic and Computer Design Fundamentals. Prentice-Hall, NJ, fourth edition, 2008 Review Sections 5.1 5.7 If FSMs don t make sense now, please ask questions, or see me FSMs are tricky at first Almost everybody has this moment of epiphany at which they suddenly make sense Section 9.1 9.6 35 R. Dick Introduction to Computer Engineering EECS 203
Computer geek culture references Parsers and lexical analyzers Writing problem-specific languages A. V. Aho, R. Sethi, and J. D. Ullman. Compilers principles, techniques, and tools. Addison-Wesley, MA, 1986 Lex and yacc Flex and bison 36 R. Dick Introduction to Computer Engineering EECS 203