Keeping The Clock Pure. Making The Impurities Digestible

Keeping The lock Pure or alternately Making The Impurities igestible Timing is everything. ig ir p. 99 Revised; January 13, 2005 Slide 0 arleton University Vitesse igital ircuits p. 100 Revised; January 13, 2005 omment on Slide 1

Timing Properties of Flip-Flops Timing Properties of Flip-Flops Simultaneous Signal hanges. Gate Two inputs change at once Result: runt pulse Fig. 1-1 Latch With Feedback Two inputs change at once 1 /2 Result: runt pulse may be captured for a while Two inputs change, a hair late. 1 Result: old captured 0 Two inputs change, a hair early. Result: new captured Runt level is generated when and change together at internal feedback loop. At inputs, changes are offset by δ. δ ifferent internal delays 1 /2 ig ir p. 101 Revised; January 13, 2005 Slide 1 Timing Properties of Flip-Flops Simultaneous changes Flip Flop Timing Properties If two signals change at the same time, the gate output may change its mind, and cause the output to have a runt pulse. Simultaneous change in combinational circuits In combinational circuits, these runt pulses are usually smoothed out as they pass through the next gate. Simultaneous change in latches and flip flops In latches and flip flops, the runt pulse may be fed back and captured in the feedback loop. This is unstable storage, and will decay toward either a 0 or a 1, but it will sometimes stay for a clock cycle or more, enough to corrupt the data. Moving edges a picosecond apart will stop the runt pulse from being captured. Simultaneous changes at flip flop inputs make the output indeterminate However, if changes too close to the clock edge, one cannot be sure if one will capture the desired old signal, capture 1/2, or capture the new signal a clock cycle early. For this reason, we avoid changing too close to the clock active edge. arleton University Vitesse igital ircuits p. 102 Revised; January 13, 2005 omment on Slide 1

Restricted Region for a Family of FF FIG. 1-2. δ 0, -20, V =3.0V Timing Properties of Flip-Flops 10 V =3.2V 20 V =3.3V Run them over temperature range Run over supply voltage range. Get all different internal δ. δ = delay at which one gets the runt level. δ δ Worst case δ, after Worst case δ, before Many supposedly indentical flip-flops -10 V =3.3V 40 V =3.4V 60 δ V =3.2V 70 V =3.6V Specification for a restricted region around the clock edge where must not change. Good for all ff of this design Good for temperature range Good for V range ig ir p. 103 Revised; January 13, 2005 Slide 2 Timing Properties of Flip-Flops A Specification for how far to keep from A Specification for how far to keep from For a single flip-flop the moving the change in a picosecond or less will change one from successful capture, through the runt capture region, and into the premature capture of the new signal. Production (processing) variations If δ is the delay between the (clock) and edges that puts one right in the middle of the runt-pulse region, production variations will cause δ to be different even for flip flops of identical design. Temperature and V variations Temperature and supply voltage changes will cause further changes in δ. Setting the spec To make a specification for the design, one takes the flip flop and obtains the delay over supply voltage, temperature and processing variations. From these one extracts the extreme δmax and δmin. From these the flipflop designer sets up a specification for how close changes can be to (clock) changes. If this spec. is obeyed, the flip flop output will always be correct when operated within the V and temperature ranges. arleton University Vitesse igital ircuits p. 104 Revised; January 13, 2005 omment on Slide 2

Setup Time and Hold Time FIG. 1-3. Timing Properties of Flip-Flops Flip-flops have a restricted region around the active clock edge If the changes in these regions, is idefinite. may follow: - the old input, - the new input, - take a runt 1/2 level. Region where data must hold still INPUT LOK INPUT LOK Setup time Hold time Setup time Hold time (negative) Setup time...the interval before the clock where the data must stay stable. Hold time...the interval after the clock where the data must stay stable. Most modern flip-flops have a zero or a negative hold time. Negative hold time...data can change slightly before the clock edge and still be captured. ig ir p. 105 Revised; January 13, 2005 Slide 3 Timing Properties of Flip-Flops A Specification for how far to keep from Setup Time and Hold Time The restrictive time region around the clock edge is given two time specifications: Setup time..........the interval before the clock where the data must not change. Hold time......... the interval after the clock where the data must not change. ircuit design is easier if the hold time is made short, preferably zero or negative, so modern flip-flops usually have a zero hold time. The designer can slide the position of the restricted region by adding delay in either the clock or data lead. Adding delay in the lead, for example means the setup time will be longer, since must arrive earlier to overcome the delay. However the hold time will decrease by the same amount. With circuit synthesis, the logic synthesiser will check that that data cannot change inside these two specifications. delays delays long delay in long delay in arleton University Vitesse igital ircuits p. 106 Revised; January 13, 2005 omment on Slide 3

Timing Properties of Flip-Flops Synchronous and Asynchronous Signals Fig. 1-4 Summary of the Restricted Region Restricted region: Time interval around clock edge where should not change. Otherwise may not follow. 1) Synchronous Signals Synchronous signal A signal constrained so it cannot change in the restricted region. Asynchronous signal can and will change anywhere. Sample inputs. The upper two are synchronous; The one above the clock is asynchronous; it has a transition inside the restricted region. 2) 3) in LOK Fig. 1-5 in; Synchronous in; Synchronous in; Asynchronous LOK INPUT LOK Restricted Region Restricted Region Setup time Hold time followed did not follow went metastable Assume they don t become asynchronous off stage. ig ir p. 107 Revised; January 13, 2005 Slide 4 Timing Properties of Flip-Flops Synchronous Signals Synchronous Signals The signals which travel around inside digital circuits are synchronous. It is fairly easy to make them synchronous with a limited knowledge of circuit delays. Asynchronous signals may happen when: Signals come in from off chip. Signals come from a circuit driven by another clock. Signals generated by using the clock for something other than latches or flip flops, for example gates in the clock lead, or driving the select on a mux from the clock. arleton University Vitesse igital ircuits p. 108 Revised; January 13, 2005 omment on Slide 4

Timing Properties of Flip-Flops lock-to-output Propagation elay, t HV t prop (clk-to-output) Time from active clock edge until changes. Another name is t HV (time from lock going High to becoming Valid). Any reasonable flip-flop will have LOK t HV lock High to Valid The Output Signal From a locked Flip-Flop is Always Synchronous Any signal passing through a flip-flop is synchronous if t HV > t HOL. elay t HV, moves changes out of the restricted region. The signal below is synchronous. It results from passing signal in through a flip-flop. FIG. 1-6 The output is always synchronous, even if the input is not. Restricted Region in; Asynchronous t HOL t HOL ; Synchronous t HV t HV in LOK LOK If changes, its changes will be a synchronous. ig ir p. 109 Revised; January 13, 2005 Slide 5 Timing Properties of Flip-Flops The Output Signal From a locked Flip- The Output Signal From a locked Flip-Flop is Always Synchronous lock-to-output delay The delay for a change in to reach the output from the clock edge. Flip flop designers should make the clock-to-output delay longer than the hold time. One good way is to make the hold time zero. This saves adding delay in the flip-flop output, which might slow down the circuit. Later we shall see that t HV > t HOL is essential in shift registers. A flip-flop output is synchronous The output is synchronous even if the input is not. The flip flop only changes as a result of the clock. The clockto-output delay always moves the signal out of the restricted region for the next flip flop. There are two exceptions: There areso many gates after the flip-flop the data change is delayed into the next restricted region in the following flip-flops. The input causes a runt level to be captured. In this case we say the flip flop goes metastable. This is considered in another set of notes. arleton University Vitesse igital ircuits p. 110 Revised; January 13, 2005 omment on Slide 5

Timing Properties of Flip-Flops lock-to-lock Logic Propagation elays. Maximum Logic Propagation elays Synchronous circuit are made of flip-flops with logic between them. FIG. 1-7 One flip-flop feeding through logic into another flip-flop. 1 takes t HV to get out of FF1. The propagation delay through the gate(s) is t P. 2 must reach the FF2 at least t SETUP before the next clock edge. 1 1 t HV t P t SETUP 2 FF2 2 tlok thv + tp + tsetup t LOK Alternative forms: - t P t LOK - t SETUP - t HV t P(MAX) = t LOK - t SETUP - t HV ig ir p. 111 Revised; January 13, 2005 Slide 6 Timing Properties of Flip-Flops Maximum lock-to-to-lock Propagation Maximum lock-to-to-lock Propagation elay This is the main timing constraint in digital circuits. Not meeting this constraint is called a setup-time violation. arleton University Vitesse igital ircuits p. 112 Revised; January 13, 2005 omment on Slide 6

Minimum Logic Propagation elays. Timing Properties of Flip-Flops Happens when t HV < t HOL. lock two flip-flops on the same edge. For a long hold time, FF1 can flip within the long t HOL, and send its new output to FF2 fast enough to flip FF2 on the same clock edge. To avoid double flips:- t HOL t HV + t P or t P t HOL - t HV The minimum allowable propagation delay:- t P(MIN) = t HOL - t HV t HV 1 1 FF1 t P 2 FF2 Fig. 1-8 2 How can a FF have t HV < t HOL? If there were two flip-flop designs. One FF1 could have a short t HV and FF2 a long t HOL. A slow rising edge on the clock could also do this. ig ir p. 113 Revised; January 13, 2005 Slide 7 Timing Properties of Flip-Flops Maximum lock-to-to-lock Propagation Minimum logic propagation delay A circuit which cannot meet this timing constraint is said to have a hold-time violation. In circuits with any logic between flip flops, the logic delay is almost certainly enough so hold time violations cannot occur. Shift registers do not have logic between the flip flops. They are susceptible to hold-time violations. Flip flops shold not have t HV < t HOL Properly designed flip flops do not. Not all flip flops are properly design. Also some very high-speed flip-flops are so hard to make work, that this problem may be forgiven. arleton University Vitesse igital ircuits p. 114 Revised; January 13, 2005 omment on Slide 7

Timing Properties of Flip-Flops Minimum Propagation elay; ifferent Picture. The minimum delay appears when the hold time is longer than t HV. Then: 1 can flip 1 of FF1, and travel through the gate and reach FF2 inside its hold time. FF2 may also change on the first clock edge! t HOL Excessively long hold time t HV 1 1 LK FF1 2 2 FF2 t P Very small 1 LK 1 t HV t HV t HV t P(MIN) t HOL 2 2 t HV 2 is just a little early, inside the hold time. 2 changed, when it should have waited till the next active clock edge. t HOL = t HV + t P(MIN) Fig. 1-9 ig ir p. 115 Revised; January 13, 2005 Slide 8 Timing Properties of Flip-Flops Maximum lock-to-to-lock Propagation Hold-Time Violations Hold problems can be cured by inserting a pair of inverters in the offending lead. Synthesizers will do this automatically if the fix-hold option is specified. arleton University Vitesse igital ircuits p. 116 Revised; January 13, 2005 omment on Slide 8n

lock Skew. lock Skew. lock skew When the clock edge does not reach all the flip-flops at the same time. Positive skew The data and clock are delayed in the same direction. The right flip-flop receives the delayed clock. 1 1 t 2 P t SKEW 2 Fig. 1-10 Negative skew The data and clock are delayed in opposite directions. The right flip-flop receives the early clock. 1 1 t P 2 t SKEW 2 Fig. 1-11 ig ir p. 117 Revised; January 13, 2005 Slide 9 lock Skew. arleton University Vitesse igital ircuits p. 118 Revised; January 13, 2005 omment on Slide 9

lock Skew. Positive lock Skew Increases the Effective lock Period If there is a positive skew, there is more time to get to FF2 1 FF1 t SKEW LOK 1 LOK 2 FF2 2 t LOK 1 t SKEW LOK 1 LOK 2 2 t LOK + t SKEW Fig. 1-12 ig ir p. 119 Revised; January 13, 2005 Slide 10 lock Skew. Positive lock Skew Increases the Effective lock Period arleton University Vitesse igital ircuits p. 120 Revised; January 13, 2005 omment on Slide 10

lock Skew. Maximum Logic elays With lock Skew Positive Skew Increases t P(MAX) With positive skew, there is more time to get to FF2, t P(MAX) is increased by the amount of the skew. 1 t HV t P FF1 LOK 1 t SKEW LOK 2 t SETUP FF2 2 t LOK 1 t SETUP t SKEW LOK 1 LOK 2 1 t HV t P(MAX) 2 t SETUP t LOK + t SKEW 2 Fig. 1-13 t LOK + t SKEW = t HV + t P(MAX) + t SETUP ig ir p. 121 Revised; January 13, 2005 Slide 11 lock Skew. Maximum Logic elays With lock Skew arleton University Vitesse igital ircuits p. 122 Revised; January 13, 2005 omment on Slide 11

lock Skew. Minimum propagation delay limit with skew With positive clock skew, the clock to FF2 is delayed. t SKEW acts like an increase in the hold time of FF2. Skew may make the effective t P < t P(MIN). 1 (a) t HV 1 1 t P LOK 1 1 t HV t P t P(MIN) Gate with t P <t P(MIN) t SKEW LOK 2 2 2 t SKEW 2 2 2 is just inside the hold time 2 changed too soon. t HOL t HV + t P t SKEW + t HOL Fig. 1-14 t HV + t P(MIN) = t SKEW + t HOL ig ir p. 123 Revised; January 13, 2005 Slide 12 lock Skew. Maximum Positive Skew For A Shift Maximum Positive Skew For A Shift Register The minimum logic delay t P(MIN) is worse with positive skew. The minimum logic delay needed to avoid the restricted region is increased. All flip-flops should have t HV t HOL, so t P(MIN) = 0. Note one cannot have a negative t P. With skew one may require t P(MIN) > 0. t SKEW + t HOL = t HV + t P(MIN) t P t HOL + t SKEW - t HV PROB 1.1 FIN THE MAXIMUM ELAY IN THE LOK BUFFERS FOR THE SHIFT REGISTER SHOWN. Solution t HV =2 t HV =2 1 1 t P =0 2 2 t P =0 3 t SKEW1-2 t SKEW2-3 LOK 1 LOK 2 LOK 3 3 t P ( to ) = 0 ns t HV = 2 ns max t HOL = -1 ns min For 1 to 2 For 2 to 3 t P t HOL + t SKEW - t HV t P t HOL + t SKEW - t HV 0-1 + t SKEW1-2 - 2 0-1 + t SKEW2-3 - 2 t SKEW1-2 +3 t SKEW2-3 +3 t SKEW1-3 = t SKEW1-2 + t SKEW2-3 +6 elay LOK1 to LOK2 may be up to 3 ns. elay LOK1 to LOK3 may be up to6 ns. arleton University Vitesse igital ircuits p. 124 Revised; January 13, 2005 omment on Slide 12

lock Skew. Maximum Negative Skew For A Shift Register PROB 1.2. The clock delays are opposite to the data delays, t SKEW is negative. Find the maximum delay in the clock buffers. t HV =2 t HV =2 1 1 t P =0 2 2 t P =0 3 t SKEW t SKEW LOK 1 LOK 2 LOK3 Solution For 1 to 2 3 Fig. 1-15 t P ( to ) = 0 ns t HOL = -1 ns min t HV = 2 ns max t SKEW is negative that is t SKEW = - t SKEW t P t HOL + t SKEW - t HV 0-1 - t SKEW1-2 - 2 +3 - t SKEW1-2 +3 t SKEW1-2 > - t LOK Pos skew can be up to 3 ns. Any negative skew up to a clock cycle is ok In shift registers, route the clock against the shift. ig ir p. 125 Revised; January 13, 2005 Slide 13 lock Skew. Maximum Positive Skew For A Shift Shift Registers Should Have The ata Flow Opposite the lock Flow arleton University Vitesse igital ircuits p. 126 Revised; January 13, 2005 omment on Slide 13

lock Skew. Maximum and Minimum elay With Bounded Skew Know max skew in clock network on t know sign. Must assume worst case sign, positive when calculating t P(MIN) negative when calculating t P(MAX). Sumary of Min and Max t P Skew has unknown sign For t P(MIN) (use + skew) For t P(MAX) (use - skew) t P t HOL + t SKEW - t HV t P t LOK + t SKEW - t SETUP - t HV t P(MIN) = t HOL + t SKEW - t HV t P(MAX) = t LOK - t SKEW - t SETUP - t HV ig ir p. 127 Revised; January 13, 2005 Slide 14 lock Skew. Maximum Positive Skew For A Shift Allowed Logic elays With Skew PROB 1.2 MAXIMUM AN MINIMUM ELAY WITH BOUNE SKEW Two registers of flip-flops have a clock skew which is between -3 and 3 ns. 1 is the collective name for any or all outputs of the right-hand register. 2 is the same for the inputs of the right-hand register. Find t P (MIN) and t P (MAX). 50 MHz delay 3 Solution: For t P(MIN) (use + skew) t SKEW = t EGE-LOK2 - t EGE-LOK2 delay 3 t SKEW 3 ns LOK 1 1 LOK t LOK = 20 ns 2 1 t HOL = 0 ns min 1 2 1 1 2 OMBINATIONAL 1 thv = 2 ns max 1 LOGI 1 t 1 t P(MIN) =? 1 SETUP = 4 ns max 1 t P(MAX) =? 1 1 1 For t P(MAX) (use - skew) t P t HOL + t SKEW - t HV t P(MIN) = 0 + 3-2 = 1 ns t P t LOK + t SKEW - t SETUP - t HV t P(MAX) = 20 + (- 3) - 4-2 = 11 ns arleton University Vitesse igital ircuits p. 128 Revised; January 13, 2005 omment on Slide 14

lock Skew. Summary of Simple Propagation elay Bounds positive skew- lock delay in the same direction as data-flow delay. t SKEW = t ESTINATION-LOK-EGE - t SOURE-LOK-EGE t P(MAX) = t LOK + t SKEW - t HV - t SETUP t P(MIN) = t SKEW + t HOL - t HV Positive skew: allows longer logic delays forces the minimum delay to be longer. Negative skew: allows a shorter minimum logic delay forces the maximum logic delays to be shorter. Rule of thumb for maximum clock skew a) Assume very fast paths between flip-flops t P(MIN) =0. b) Assume proper hold time in flip-flops t HOL 0. Approximate bound on skew is - t SKEW t HV ig ir p. 129 Revised; January 13, 2005 Slide 15 lock Skew. A Bound on Skew is Known but Not The A Bound on Skew is Known but Not The Sign A designer may have a good idea how much skew is in the clock system, but he/she may not know where the individual flip flops will be connected, and cnnot tell the sign of the skew. Then designs must be done so that either positive or negative skew is acceptable. arleton University Vitesse igital ircuits p. 130 Revised; January 13, 2005 omment on Slide 15

The Temptation To Gate The lock. Gating the lock Gating the lock A simple way to disable a flip-flop. It may save area or power. Problems: 1) Adds clock skew. 2) an cause a false clock edge. 3) Full-scan testing will not test it. 4) Many synthesis tools and FPGAs do not support it. FIG. 1-16 Two methods of disabling flip flops (a) Approved method of enabling/disabling a flip-flop. No clock skew, no false clock edges, scan testable, tools support, FPGA support. (b) lock gating, the high risk way to enable/disable the flip-flop. Saves power by not clocking nonflipping flip-flops. (a) INPUT ABLE(H) LOK 1 1 MUX G1 1/1 1 1 (b) INPUT ABLE(H) LOK 1 1 ig ir p. 131 Revised; January 13, 2005 Slide 16 Gating the lock A Bound on Skew is Known but Not The To Gate or Not to Gate Gating the lock There is a great temptation to gate the clock, particularly by inexperienced designers. Many of the reasons for gating the clock are unnecessary, and not worth the troubles it causes. The only common valid reason for gating the clock is to save clock power. A common pseudo reason is a change in data rate. This is better done by using enabled flip flops, and disabling the flip flops instead of gating the clock. Tool Support If you wish to gate the clock. check that your synthesis tool, and your test insertion/generation tools will support it. arleton University Vitesse igital ircuits p. 132 Revised; January 13, 2005 omment on Slide 16

Problems from lock Gating lock Skew From Gating the lock Gating the lock lock skew reduces t P margins. overed in last section. False lock Edges. signal may cause false GLK edges. hanges in must be restricted. FIG. 1-17 False clock edges caused by the signal rising while the clock is high. will cause false clocking if it rises when the clock is high (φ high ). should rise when clock is low (φ low ). Restricted Region must not rise herein INPUT LK 1 1 GLK LK Problem edge φ high No problem φ low Problem edge GLK Proper (though skewed) clock edge False clock edges ig ir p. 133 Revised; January 13, 2005 Slide 17 Gating the lock Gating the lock auses Problems Gating the lock auses Problems lock Skew Adding Gates in the clock line causes skew. This will lower the bounds on the minimum and maximum propagation delays through the logic, according to: t P(MIN) = t SKEW + t HOL - t HV t P(MAX) = t LOK - t SKEW - t HV - t SETUP arleton University Vitesse igital ircuits p. 134 Revised; January 13, 2005 omment on Slide 17

Gating the lock Two ases Of lock Gating Restrict changes to avoid false clock edges.. ase a) AN gate, NOR gate may change only in the last half cycle INPUT LK 1 1 GLK IN LK 1 GLK 1 LK No! ase b) OR gate, NAN gate may change only in the first half cycle IN LK 1 GLK 1 INPUT (a) 1 1 LK GLK LK No! ig ir p. 135 Revised; January 13, 2005 Slide 18 Gating the lock Gating the lock auses Problems FIG. 1-1 False clock edges, when the first half-clock-cycle is restricted Restricted Region IN LK (a) 1 GLK 1 LK GLK φ high OK edge False False No upward transitions allowed in the restricted region ( φ high ). Restricted Region IN _N LK (b) GLK 1 1 _N LK GLK φ low OK edge False OK No downward transitions allowed in the restricted region ( φ low ). arleton University Vitesse igital ircuits p. 136 Revised; January 13, 2005 omment on Slide 18

Gating the lock etails of Gating With OR or NAN Gates FIG. 1-18 False clock edges, when the second half-clock-cycle is restricted Restricted Region IN _N LK 1 GLK 1 _N LK φ low No upward transitions allowed in the restricted region (φ low ). GLK OK edge False OK Restricted Region INPUT LK 1 1 GLK LK GLK φ high No downward transitions allowed in the restricted region (φ high ). OK edge False False ig ir p. 137 Revised; January 13, 2005 Slide 19 Gating the lock Gating the lock auses Problems arleton University Vitesse igital ircuits p. 138 Revised; January 13, 2005 omment on Slide 19

Gating the lock lock Gating Summary 1) must not change in the first half cycle changes in the last half of the clock cycle. Gives more time to generate the, but It has both an upper and lower bound on its delay. It must be glitch free in the first half cycle. This is very difficult to design! counter t P T LK /2 < t P < T LK No glitches in first half ABLE_ON_7_OUNT INPUT LK 1 1 INPUT LK 1 1 _N LK 1 1 2) must not change in the second half cycle changes in the first half of the clock cycle. The signal must be generated quickly within 1/2 cycle It must be glitch free in the last half cycle but there it has settled down. This is simple to design except for speed requirement. _N LK 1 1 LK 1 1 ig ir p. 139 Revised; January 13, 2005 Slide 20 Gating the lock Generating the Enable Signal Generating the Enable Signal With AN gating If the signal has more than minimal complexity, it is hard to make it glitch free. See the unit on hazards with multiple input changes. Most logic is designed with only an upper bound on t P. The lower bound is usually zero which is easy to meet. onsider a gate with t P(min) =0.2, t P(nom) =0.3, t P(max) =0.4. t LK =1.0. Two of these gates in series easily meet the the max. specification, but violate the min. specification. This illustrates that it is more difficult to meet the double specification. Hazards In the first half of the clock cycle, the flip flop outputs have recently changed, and it is difficult to avoid multivariable-change hazards. With OR gating Here the signal must be complete and stable in the first half of the clock cycle. However there is no minimum timing specification to meet. Hazards In the second half of the clock cycle, the signal is stable, there are no changes to create new glitches, and the circuit does not have to be hazard free. arleton University Vitesse igital ircuits p. 140 Revised; January 13, 2005 omment on Slide 20

Gating the lock Safe lock-gating Using a Latch. (safe except for skew!) -RAW is latched and applied to an AN gate. lock high (φ 1): Glitches in -RAW are stopped by the latch in store mode. lock low (φ 2): Glitches in -RAW are stopped by the AN gate. This method is good for shutting down a subcircuit for several cycles. For example shutting off the floating point unit in a microcomputer. FIG. 1-19 A clock gating method with no false clock edges. 1 and 2 are enabled when -RAW is high. The latch stops glitches when the clock is high. The AN stops glitches when the clock is low. SHUT OWN LOGI TRANSPART LATH 3 1 -RAW 1 LK OMB LOGI GLK GLK 1 1 1 1 1 2 ig ir p. 141 Revised; January 13, 2005 Slide 21 Gating the lock Generating the Enable Signal arleton University Vitesse igital ircuits p. 142 Revised; January 13, 2005 omment on Slide 21

FIG. 1-20 Gating the lock Waveforms for a gated clock with no false edges. GLK is enabled for -RAW high. The latch ensures the will not change in the restricted region for AN type gating. SHUT OWN LOGI LATH -RAW 1 3 1 LK LATH OMB LOGI GLK 1 1 1 1 1 2 LK -RAW GLK 1st half LATH STORES LATH TRANSP T LATH STORES ABLE LATH STOPS GLITH AN GATE STOPS GLITH When gating the clock to save power: One normally gates many flip-flops at once. For one flip-flop, the power for the extra latch may be more than the saving. One normally shuts off the clock for many cycles at a time. The clock skew is minimized if an AN is placed in every clock line. The full-scan test people will not like this. ig ir p. 143 Revised; January 13, 2005 Slide 22 Gating the lock Gating With a Latch and a Gate Gating With a Latch and a Gate This method avoids: ritical timing in the generating logic oncern about glitches in the generating circuits However: It still adds clock skew which reduces the bounds on the propagation delay. If used on one or two flip flops. the latch will consume more power than one saves by gating the clock. Hence one needs to shut down a reasonable number of flip flops with one clock control. arleton University Vitesse igital ircuits p. 144 Revised; January 13, 2005 omment on Slide 22

Multiple locks Multiple locks Why Two lock Frequencies? The internal clock for (Pentium, Alpha, Power P, Spark, Xeon) is too fast for the board circuitry. With both slow and fast logic, save power by using a slow clock for the slow logic. Basic Methods Enabled Flip-Flops lock all flip-flops at high-speed and enable the flip-flops at a lower speed. Is the safest (easiest) method. Will not give much power saving. Gate lock INPUT Gate the high-speed clock with a slower signal. 1 Will give medium power reduction. 1 Will use less power in the flip-flops, LK But: harging and discharging the clock line at high speed wastes power. Gated clock are subject to false edges and skew. ivide the clock ivider can supply different frequencies to different flip-flops. an give lower power. But:- Watch skew between the main and divided clocks. LK 1 1 ivider/counters may glitches which will poison clock lines. 1 1 LK/2 ig ir p. 145 Revised; January 13, 2005 Slide 23 Multiple locks Multiple locks Multiple locks Why not to use multiple clocks It saves having to make multiple clock distribution networks on chip. These networks take a lot of space and are difficult to layout. It saves having to keep active edges synchronized within some small skew. Why use multiple clocks locking flip flops faster than necessary for the data rate, wastes power. If two data rates are completely asynchronous, and their data rates are near the maximum clock speed desired for the chip, it may be necessary to clock the data streams at their own clock rate. arleton University Vitesse igital ircuits p. 146 Revised; January 13, 2005 omment on Slide 23