Latches, Flip-Flops, and Registers (Chapter #7) Dr. Ouiem Bchir The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney.
Sequential Logic Circuits Sequential switching circuits have the property that the output depends not only on the present input but also on the past sequence of inputs. In effect, these circuits must be able to remember something about the past history of the inputs in order to produce the present output. We say a circuit has feedback if the output of one of the gates is connected back into the input of another gate in the circuit so as to form a closed loop. Spring 2015 CSC 220 - Dr. Ouiem Bchir 2
Basic Memory Elements Spring 2015 CSC 220 - Dr. Ouiem Bchir 3
Latch Flip Flop Basic Memory Elements - Clock input is level sensitive. - Output can change multiple times during a clock cycle. - Output changes while clock is active. - Clock input is edge sensitive. - Output can change only once during a clock cycle. - Output changes on clock transition. Spring 2015 CSC 220 - Dr. Ouiem Bchir 4
SR Latch: Behavior S R Q + 0 0 Q 0 1 0 1 0 1 1 1 Not allowed If S = 1 (Set), Q + = 1 If R = 1 (Reset), Q + = 0 If S = R = 0, Q + = Q (no change) S = R = 1 is not allowed. Spring 2015 CSC 220 - Dr. Ouiem Bchir 5
SR Latch: Symbol always complementary Spring 2015 CSC 220 - Dr. Ouiem Bchir 6
SR Latch: Characteristic Equation Characteristic Equation: Q + = S + R'.Q (S.R = 0) Spring 2015 CSC 220 - Dr. Ouiem Bchir 7
Gated D Latch A gated D latch has two inputs a data input (D) and a gate input (G). The D latch can be constructed from an S-R latch and additional logic gates. When G = 1, the value of D is passed to Q. When G = 0, the Q output holds the last value of D (no state change). This type of latch is also referred to as a transparent latch. Spring 2015 CSC 220 - Dr. Ouiem Bchir 8
Gated D Latch: Symbol and Truth Table No invalid inputs! Spring 2015 CSC 220 - Dr. Ouiem Bchir 9
Gated D Latch: Characteristic Equation Characteristic Equation: Q + = G'.Q + G.D Spring 2015 CSC 220 - Dr. Ouiem Bchir 10
D Flip-Flop (edge-triggered) A D flip-flop has two inputs, D (data) and Ck (clock). The small arrowhead on the flip-flop symbol identifies the clock input. Unlike the D latch, the flip-flop output changes only in response to the clock, not to a change in D. If the output can change in response to a 0 to 1 transition on the clock input, we say that the flip-flop is triggered on the rising edge (or positive edge) of the clock. If the output can change in response to a 1 to 0 transition of the clock input, we say that the flip-flop is triggered on the falling edge (or negative edge) of the clock. An inversion bubble on the clock input indicates a falling-edge trigger. Spring 2015 CSC 220 - Dr. Ouiem Bchir 11
D Flip-Flop Q + = D Characteristic Equation Spring 2015 CSC 220 - Dr. Ouiem Bchir 12
D Flip-Flop: Timing Diagram Which clock edge is the D flip-flop triggered on? Spring 2015 CSC 220 - Dr. Ouiem Bchir 13
SR Flip-Flop An S-R flip-flop is similar to an S-R latch in that S = 1 sets the Q output to 1, and R = 1 resets the Q output to 0. The essential difference is that the flip-flop has a clock input, and the Q output can change only after an active clock edge. Spring 2015 CSC 220 - Dr. Ouiem Bchir 14
SR Flip-Flop Operation summary: S = R = 0 no state change S = 1, R = 0 set Q to 1 (after active Ck edge) S = 0, R = 1 reset Q to 0 (after active Ck edge) S = R = 1 not allowed Spring 2015 CSC 220 - Dr. Ouiem Bchir 15
T Flip-Flop The T flip-flop, also called the toggle flip-flop, is frequently used in building counters. It has a T input and a clock input. When T = 1 the flip-flop changes state after the active edge of the clock. When T = 0, no state change occurs. Spring 2015 CSC 220 - Dr. Ouiem Bchir 16
T Flip-Flop: Timing Diagram Spring 2015 CSC 220 - Dr. Ouiem Bchir 17
Registers Spring 2015 CSC 220 - Dr. Ouiem Bchir 18
Registers Several D flip-flops may be grouped together with a common clock to form a register. Because each flip-flop can store one bit of information, a register with n D flip-flops can store n bits of information. A load signal can be ANDed with the clock to enable and disable loading the registers. A better approach is to use registers with clock enables if they are available. Spring 2015 CSC 220 - Dr. Ouiem Bchir 19
Register with Tri-state Output Spring 2015 CSC 220 - Dr. Ouiem Bchir 20
Shift Register A shift register is a register in which binary data can be stored and shifted either left or right. The data is shifted according to the applied shift signal; often there is a left shift signal and a right shift signal. A shift register must be constructed using flip-flops (i.e. edgetriggered devices); it cannot be constructed using latches or gated-latches (i.e. level-sensitive devices). Spring 2015 CSC 220 - Dr. Ouiem Bchir 21
Shift Register: 4 bits Spring 2015 CSC 220 - Dr. Ouiem Bchir 22
Shift Register (4 bits): Timing Diagram Spring 2015 CSC 220 - Dr. Ouiem Bchir 23
4-bit PI PO Shift Register Spring 2015 CSC 220 - Dr. Ouiem Bchir 24
4-bit PI PO Shift Register: Operation Spring 2015 CSC 220 - Dr. Ouiem Bchir 25
4-bit PI PO Shift Register: Timing Diagram Spring 2015 CSC 220 - Dr. Ouiem Bchir 26