EECTRICA ENGINEERING DEPARTMENT California Polytechnic State University EE 361 NAND ogic Gate, RS Flip-Flop & JK Flip-Flop Pre-lab 7 1. Draw the logic symbol and construct the truth table for a NAND gate. 2. The threshold voltage is 1.4 Volts for the NAND gate shown. Sketch V o for each of the two input signals described below. Be certain to label both the voltage axis and the time axis with numerical values. Include a sketch of V 1 on the same graph as V o. +5V + + V 1 V 0 A. V 1 = 100 z square wave which varies between 0V and +5V. B. V 1 = 100 z triangular wave which varies between 0V and +5V. 44
3. The cross-coupled NAND gates form a RS flip-flop. Complete below truth table. Note: 0 1 indicates a transition from 0 to 1. 4. The clock pulses shown are applied to the JK flip-flop clock input. Sketch output. CK t t 45
EECTRICA ENGINEERING DEPARTMENT California Polytechnic State University EE 361 NAND ogic Gate, RS Flip-Flop & JK Flip-Flop Pre-lab 7 Objective Examine the NAND logic gate and study its use in a RS flip-flop. astly, investigate a JK flipflop operation in toggle mode. Workbench Equipment Digital Oscilloscope, Keysight InfiniiVision MSO-X2022A Function Generator, Agilent 33120A or Agilent 33220A DC Power Supply, Agilent E3640A Check-out Equipment, 20-111 window Scope Probe (10:1), 2 Banana to grabber 2 pair, 2 red / 2 black BNC to grabber lead Background NAND ogic Gate The NAND logic function is equal to an inverted AND logic function. A NAND gate is an electronic circuit usually consisting of at least one transistor switch. The NAND logic symbol along with an example of a NAND simplified circuit is shown in Figure 6-3. V CC R B R A A B F A D 1 B D 3 D P 4 D 2 F (a) (b) Fig. 7-1 (a) NAND Symbol (b) NAND Circuit The NAND circuit of Figure 7-1 (b) operates as follows: when both inputs A and B are in a 1 state (+5V), diodes D 1 and D 2 are reverse biased and all V cc source current flows through R B, D 3, D 4 and base-emitter of BJT to ground. This forward biases the base-emitter junction and turns BJT on thereby effectively connecting the output (node F) to ground ( 0 = 0V) since V CE = 0V ideally. For the inputs of Figure 7-1 (b) to be recognized as a 1, A or B must be greater than the threshold voltage, which is about 1.4 volts. An input voltage below the threshold voltage equals a 0. If either or both inputs has a 0 (0V), at least one input diode will be forward-biased and conduct current. Thereby current is drawn away from the base of the BJT, and the voltage at node P will not be large enough to forward-bias the base-emitter junction. Therefore the BJT is 46
off and zero current ideally flows through R A and the voltage at the output node F will ideally equal V cc source voltage = 1. RS Flip-Flop A flip-flop is a logic circuit which can store (retain) data ( 0 s and 1 s). Storage of data occurs when an output remains the same for a change of input. An example of an RS flip-flop logic circuit is shown in Figure 7-2. RS is shorthand for Reset / Set. Fig 7-2 RS Flip-Flop An RS flip-flop circuit is referred to as cross-coupled NANDs. The term cross-coupled refers to the connections between the output of one NAND gate and an input of the other NAND gate in a crossing fashion as depicted in Figure 7-2. The truth table for the RS flip-flop of Figure 7-2 is shown in Figure 7-3. Fig 7-3 RS Flip-Flop (Figure 7-2) Truth Table All RS flip-flops have four states; set, reset, ambiguous and storage. Set means output = 1 and output = 0 Reset means = 0 and = 1 Ambiguous Set Reset Storage Ambiguous refers to both outputs having the same value which contradicts the Boolean algebra definition of the term not which means opposite of. This state is not acceptable and should be avoided in most cases. Storage, the Xs = no change in output. So, when both inputs S and R are equal to 1 both outputs and remain the same. This means the outputs now have data ( 0 s or 1 s) from a previous time since it takes a finite amount of time for an input to change value, therefore storage of data has occurred. 47
7400 NAND GATE IC Important Information Pin Diagram: VCC 4B 4A 4Y 3B 3A 3Y 14 13 12 11 10 9 8 7400 1 2 3 4 5 6 7 1A 1B 1Y 2A 2B 2Y GND Operational Notes: Input signals must never exceed V CC, nor fall below ground. Unused TT inputs float high. This means that if an input is unconnected, the gate will interpret this input as a high or 1 input. If, however, the input is supposed to be fixed at a high state, it should be connected to V CC. Although it is not always shown explicitly on diagrams, a 0.01 to 0.1 µf decoupling capacitor should be used in each circuit. It must have short leads, be connected from V CC to ground, and be as near as possible to the IC. The purpose of this capacitor is to prevent high frequency noise from damaging the IC, or affecting results. Avoid using long wires in circuits because they contribute to stray capacitance and can adversely affect results. Make sure to apply V CC to pin 14 and ground to pin 7. If you reverse the Vcc and ground connections the IC will burn. 48
JK Flip-Flop The JK flip-flop has several advantages over the RS flip-flop. First, there isn t an ambiguous state in the JK truth table (see Figure 7-4). In addition, the JK flip-flop is an edge-triggered device and therefore JKs can be easily synchronized by connecting clock inputs together. Note: Xs = don t care INPUTS OUTPUTS CR CK J K X X X O O TOGGE Storage State Fig. 7-4 JK Flip-Flop Truth Table astly, JK flip-flops have a toggle state. When in toggle mode, the outputs of a JK will equal their opposite state on every high to low (trailing-edge) transition of the clock (CK) input. The toggle state makes the JK flip-flop very suitable for use in binary counters. 74107 JK Flip-Flop Important Information Pin Diagram: VCC 14 CR1 CK1 K2 CR2 CK2 J2 13 12 11 10 9 8 J K K J 1 2 3 4 5 6 7 J1 1 1 K1 2 2 GND Operational Notes: Input signals must never exceed V CC, nor fall below ground. Unused TT inputs float high. This means that if an input is unconnected, the gate will interpret this input as a high or 1 input. If, however, the input is supposed to be fixed at a high state, it should be connected to V CC. Although it is not always shown explicitly on diagrams, a 0.01 to 0.1 µf decoupling capacitor should be used in each circuit. It must have short leads, be connected from V CC to ground, and be as near as possible to the IC. The purpose of this capacitor is to prevent high frequency noise from damaging the IC, or affecting results. Avoid using long wires in circuits because they contribute to stray capacitance and can adversely affect results. 49
Make sure to apply V CC to pin 14 and ground to pin 7. If you reverse the Vcc and ground connections the IC will burn. Procedure 1: NAND Gate & NAND Gate Connected as an Inverter (NOT gate) Select one NAND gate of the 7400 IC. Connect a hookup wire to each input (A & B) and connect output (F) to a 100Ω resistor in series with a red ED connected to ground as shown in the above diagram. o Connect hookup wire to +5V for a 1 input and connect hookup wire to ground for a 0 input. Verify NAND truth table by making voltage measurements at both inputs and at its output (F). Record in Table 7-1. A (V) B (V) F (V) F ( 0 or 1 ) Table 7-1 NAND Truth Table Build the circuit of Figure 7-5. Set function generator (i Z mode) to a square wave 0V to +5V at 1,000z. Note: ED and resistor removed from NAND gate output. +5V Input A + + V 1 V O Fig. 7-5 NAND as an Inverter (NOT gate) Observe both Vo and V 1 on scope and capture display. et input A float by disconnecting from +5V. Does V o change? o A disconnected input for this type of IC, TT, is read as a 1. Set function generator (i Z mode) to a triangular wave 0V to +5V at 1,000z. Observe both V o and V 1 on scope and use the scope vertical positioning knobs to superimpose V o onto V 1 so the two waveforms intersect. Make reference (ground) same 50
horizontal line on scope display for both signals. Use cursors to measure the intersection voltage and record below, it should be approximately 1.4V. Capture display. Intersection voltage = Procedure 2: RS Flip-Flop Connect two NAND gates as shown in Figure 7-6. o For each output ( and not) connect 100Ω resistor in series with a red ED connected to ground as done in procedure 1. o Use hookup wire for inputs S and R. Verify RS flip-flop truth table by completing Table 7-2. Fig. 7-6 Cross-Coupled NAND Gates Procedure 3: JK Flip-Flop Table 7-2 Verification of RS Flip-Flop Truth Table Select one JK flip-flop of the 74107 IC and connect in toggle mode as shown in prelab #4. Use Agilent E3640A power supply for V cc = +5V. Use function generator (i Z mode) to apply a 0 to 4V 400z square wave with a 50% duty cycle. o Duty cycle refers to the amount of time a square wave is equal to its largest amplitude (4V in this case) compared to its period. Observe on scope output and CK input, capture scope image and record frequency. output frequency = z which is approximately X CK input frequency While observing both the output and clock input on the scope, vary the duty cycle of the clock input between 20% and 80%. o Be prepared to explain observation as a postlab question. Observe both outputs on scope and verify the output is 180 out of phase with. 51
Discussion 1. What logic operation does the circuit of Figure 7-5 perform? 2. ow does the NAND gate experimental threshold voltage (observed in procedure 1) compare (%error) to the theoretical threshold voltage of 1.4V? 3. In the cross-coupled NAND gate circuit of Figure 7-6, what would the and outputs equal if both inputs were grounded? Is this an acceptable state? 4. If two inverters (NOT gates) are connected to the inputs of the RS flip-flop of Figure 7-6 as shown below, how would the truth table of Figure 7-6 change? Show how Table 7-2 would be modified by clearly drawing a new table. 5. The JK flip-flops used in this experiment have active clears. 6. What type of triggering is used by the JK flip-flops, negative or positive? 7. For a J-K flip-flop, how could you most easily obtain a signal 180 o out of phase with the output? 8. In procedure 3, how does the output frequency compare to the clock input frequency? 9. In procedure 3, what effect did changing the duty cycle have on the output signal of the flip-flop? Why? int: A major use of a toggling flip-flop is to obtain a 50% duty cycle pulse, regardless of the input duty cycle. 52