Chapter 5 Synchronous Sequential Logic Chih-Tsun Huang ( 黃稚存 ) http://nthucad.cs.nthu.edu.tw/~cthuang/ Department of Computer Science National Tsing Hua University Outline Introduction Storage Elements: Latches Storage Elements: Flip-Flops Analysis of Clocked Sequential Circuits State Reduction and Assignment Design Procedure Fall 2010 CS2102 Chih-Tsun Huang 2
Sequential Circuits A sequential circuit consists of a combinational circuit to which storage elements are connected to form a feedback path Binary information stored in the memory elements at any given time defines the state of the sequential circuit. (inputs, current state) => (outputs, next state) The behavior is specified by a time sequence of inputs and internal states. Fall 2010 CS2102 Chih-Tsun Huang 3 Synchronous vs. Asynchronous Sequential Circuits Synchronous Behavior is defined from the input signals at discrete instants of time Clocked sequential circuits Most commonly used No instability problems Asynchronous Behavior depends on the value and change order of input signals at any instant of time Can be viewed as combinational circuit with feedback Fall 2010 CS2102 Chih-Tsun Huang 4
Synchronous Sequential Circuits Synchronization usually is achieved by a timing device: clock generator Clock generator generates a periodic train of clock pulses distributed throughout the system to trigger the memory elements (flip-flops) Fall 2010 CS2102 Chih-Tsun Huang 5 Latches Latches are level sensitive devices Flip-flops are edge-sensitive devices Latches are asynchronous sequential circuits State changes whenever inputs change Building blocks of flip-flops Not practical for use in synchronous sequential circuits Fall 2010 CS2102 Chih-Tsun Huang 6
SR Latches SR latch is a basic memory element which can store one bit of information Consists of two cross-coupled NOR gates or two cross-couple NAND gates two- input signals: set (S)/reset (R) Two output signals: Q/Q Two useful states: set state (Q=1, Q =0)/reset state (Q=0, Q =1) Fall 2010 CS2102 Chih-Tsun Huang 7 SR Latch with NOR Gates (1/2) (S, R) must go back to (0,0) before any other change to avoid the occurrence of the undefined state Fall 2010 CS2102 Chih-Tsun Huang 8
SR Latch with NOR Gates (2/2) Fall 2010 CS2102 Chih-Tsun Huang 9 SR Latch with NAND Gates (1/2) (S,R) must go back to (1,1) before any other change to avoid the occurrence of the undefined state Fall 2010 CS2102 Chih-Tsun Huang 10
SR Latch with NAND Gates (2/2) Fall 2010 CS2102 Chih-Tsun Huang 11 Gated SR Latch (Clocked SR Latch) (1/3) Use C (clock) to enable/disable the SR latch C=0, no change C=1, operates as normal SR latch Fall 2010 CS2102 Chih-Tsun Huang 12
Gated SR Latch (Clocked SR Latch) (2/3) The designer must make sure that the input signals do not change during the time window around falling edge of C The window starts at setup time (t setup ) before the falling edge of C and ends with hold time (t hold ) after the falling edge of C Fall 2010 CS2102 Chih-Tsun Huang 13 Gated SR Latch (Clocked SR Latch) (3/3) Fall 2010 CS2102 Chih-Tsun Huang 14
Gated D Latch (1/2) D latch has only one input D (the data input) Constructed from a gated SR latch by connecting the D input to S input and D to R Avoiding undesirable condition (S=R=1) Transparent Fall 2010 CS2102 Chih-Tsun Huang 15 Gated D Latch (2/2) Fall 2010 CS2102 Chih-Tsun Huang 16
Flip-Flops Trigger The state of a latch or flip-flop is switched by a change of the control input Level sensitive (level-triggered) The state transition starts as soon as the clock is during logic 1 (positive level-sensitive) or logic 0 (negative level-sensitive) level Edge-triggered The state transition starts only at positive (positive edge-triggered) or negative edge (negative edgetriggered) of the clock signal Fall 2010 CS2102 Chih-Tsun Huang 17 Edge-Trigger D Flip-Flop Master-slave D flip-flop Two separate latches A master latch (positive-level sensitive) A slave latch (negative-level sensitive) Fall 2010 CS2102 Chih-Tsun Huang 18
Edge-Trigger D Flip-Flop with Three SR Latches Fall 2010 CS2102 Chih-Tsun Huang 19 Setup Time and Hold Time Setup time D input must be maintained at a constant value prior to the application of the positive clock pulse Data to the internal latches Hold time Data input must not change after the application of the positive clock pulse Clock to the internal latch Fall 2010 CS2102 Chih-Tsun Huang 20
Graphic Symbol Edge-triggered D flip-flops The most economical and efficient Positive-edge and negative-edge Graphic symbol Fall 2010 CS2102 Chih-Tsun Huang 21 Types of Flip-Flops Four major commonly used FFs SR (set-reset), JK, D (data), T (toggle) FFs (assume only positive-edge-triggered FFs) Characteristic table Defines the next state Q(t+1) (i.e., the state that results from a clock transition) as a function of the inputs and the present state Q(t) (i.e., the state present prior to the application of a clock edge) Characteristic equation of each FF Can be derived from the characteristic table using map method Fall 2010 CS2102 Chih-Tsun Huang 22
JK Flip-Flop Fall 2010 CS2102 Chih-Tsun Huang 23 T Flip-Flop Fall 2010 CS2102 Chih-Tsun Huang 24
Characteristic Tables and Characteristic Equations Characteristic Equations Fall 2010 CS2102 Chih-Tsun Huang 25 Direct Input The state of FFs are unknown when power is on The direct input can force the FFs to a known state before the system starts. Preset/Set/PRS: set the FF to 1 Clear/Reset/CLR: set the FF to 0 Synchronous vs. asynchronous direct input Whether the input is controlled by the clock (synchronous) or not (asynchronous) Fall 2010 CS2102 Chih-Tsun Huang 26
D Flip-Flip with Asynchronous Reset Fall 2010 CS2102 Chih-Tsun Huang 27 Analysis of Clocked Sequential Circuits Obtain a table or a diagram for the time sequence of inputs, outputs, and internal states State table or the state diagram (inputs, current state) => (outputs, next state) The same information available in state table can be represented graphically in a state diagram A state diagram is a directed graph, where the node represents a unique state, and each arc a unique state transition. The derivation of a state diagram from a state table is unique and vice versa. Fall 2010 CS2102 Chih-Tsun Huang 28
Analysis Procedure Derive excitation equations (input equations) Derive state and output equations Generate state and output tables Generate state diagram Develop timing diagram Simulate logic schematic Fall 2010 CS2102 Chih-Tsun Huang 29 Example 1 (1/3) Flip-flop excitation/ input equation State equation 1 1 Output equation Fall 2010 CS2102 Chih-Tsun Huang 30
Example 1 (2/3) Generate state and output tables Fall 2010 CS2102 Chih-Tsun Huang 31 Example 1 (3/3) Generate state diagram Fall 2010 CS2102 Chih-Tsun Huang 32
Example 2: D Flip-Flops Excitation/input equation State equation State table Generate state diagram Fall 2010 CS2102 Chih-Tsun Huang 33 Example 3: JK Flip-Flops (1/2) Excitation/input equation State equation Fall 2010 CS2102 Chih-Tsun Huang 34
Example 3: JK Flip-Flops (2/2) State table Generate state diagram Fall 2010 CS2102 Chih-Tsun Huang 35 Example 4: T Flip-Flops (1/2) Excitation/input equation State equation Output equation Fall 2010 CS2102 Chih-Tsun Huang 36
Example 4: T Flip-Flops (2/2) State table Generate state diagram Fall 2010 CS2102 Chih-Tsun Huang 37 Mealy and Moore Models of Finite State Machines Mealy model Outputs are functions of both the present state and input Moore model Outputs are functions of the present state only Fall 2010 CS2102 Chih-Tsun Huang 38
State Reduction and Assignment State reduction Reduction on the number of flip-flops (states) and the number of gates For an FSM with m gates, we need log FFs Definition for FSM equivalence 1. Given any input sequence, starting from any identical initial state, they produce the same output sequence 2. Two states, and in an FSM are said to be equivalent ( ), iff,,, and,, where f: output function, h: next-state function, x: set of inputs Fall 2010 CS2102 Chih-Tsun Huang 39 State Reduction Procedure 1. Find rows in the state table that have identical next state and output entries. They correspond to equivalent states. If there are no equivalent states, stop. 2. When two states are equivalent, one of them can be removed. Update the entries of the remaining table to reflect the change. Go to Step 1. Fall 2010 CS2102 Chih-Tsun Huang 40
State Reduction Example (1/2) state a a b c d e f f g f g a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0 Fall 2010 CS2102 Chih-Tsun Huang 41 State Reduction Example (2/2) state a a b c d e d d e d e a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0 Fall 2010 CS2102 Chih-Tsun Huang 42
State Assignment Different state assignments (encodings) result in different circuits for the intended FSM There is no easy state-encoding procedure that guarantees a minimal-cost or minimum-delay combinational circuits Exploration of all possibilities is impossible Heuristic approaches are often used Binary encoding Minimum-bit change Prioritized adjacency One-hot encoding Fall 2010 CS2102 Chih-Tsun Huang 43 State Assignment Example Fall 2010 CS2102 Chih-Tsun Huang 44
Design Procedure Design description or timing diagram Develop state diagram Generate state and output tables Minimize states Encode inputs, states and outputs Derive state and output equations Choose memory elements (DFFs, JKFFs, TFFs) Derive excitation equation and optimize logic implementation Derive logic schematic and timing diagrams Simulate logic schematic Verify functionality and timing Fall 2010 CS2102 Chih-Tsun Huang 45 Sequence Detector Example Detect three or more consecutive 1 s in a string of bits through an input line If detected, output = 1; otherwise output = 0 Fall 2010 CS2102 Chih-Tsun Huang 46
Synthesis Using D Flip-Flops (1/2) Flip-flop input equations Output equation: Fall 2010 CS2102 Chih-Tsun Huang 47 Synthesis Using D Flip-Flops (2/2) Logic diagram Fall 2010 CS2102 Chih-Tsun Huang 48
Excitation Tables Given the state transition table, we wish to find the FF input conditions that will cause the required transition Straightforward for D FFs Excitation tables for JK and T FFs are needed Can be derived from the characteristic table/equation Fall 2010 CS2102 Chih-Tsun Huang 49 Synthesis Using JK Flip-Flops (1/3) Fall 2010 CS2102 Chih-Tsun Huang 50
Synthesis Using JK Flip-Flops (2/3) Fall 2010 CS2102 Chih-Tsun Huang 51 Synthesis Using JK Flip-Flops (3/3) Logic diagram Fall 2010 CS2102 Chih-Tsun Huang 52
Synthesis Using T Flip-Flops (1/2) Flip-Flop Inputs T A T B Fall 2010 CS2102 Chih-Tsun Huang 53 Synthesis Using T Flip-Flops (2/2) Logic diagram Fall 2010 CS2102 Chih-Tsun Huang 54
An n-bit Binary Counter 3-bit binary counter No input (except clock) The output can be the states Fall 2010 CS2102 Chih-Tsun Huang 55 Synthesis Using T Flip-Flops (1/2) Fall 2010 CS2102 Chih-Tsun Huang 56
Synthesis Using T Flip-Flops (2/2) Fall 2010 CS2102 Chih-Tsun Huang 57