A Modified Static Contention Free Single Phase Clocked Flip-flop Design for Low Power Applications

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.8, NO.5, OCTOBER, 08 ISSN(Print) 598-657 https://doi.org/57/jsts.08.8.5.640 ISSN(Online) -4866 A Modified Static Contention Free Single Phase Clocked Flip-flop Design for Low Power Applications Jin-Fa Lin and Ming-Yan Tsai Abstract A modified static contention free truesingle-phase clocked (TSPC) flip-flop with - transistor only is proposed in this paper. It is optimized by a recently presented TSPC based flipflop design and achieves circuit simplification. The optimized measure leads to a new flip-flop design featuring better and various performances. Based on post-layout simulation results using the TSMC CMOS 40nm technology, the proposed design outperforms the conventional TGFF by 49.% in energy consumption (at 0% data activity switching) with the same layout area. Index Terms Low power, flip-flop, low voltage I. INTRODUCTION Since the developments of Internet of Things (IoT) and wearable devices are growing, the need for ultra-low power consumption SOC chip is increasing as well. The performance is no longer the focus of these researches; instead, the power consumption and layout area are key points in the design. The most efficient way to reduce power is to lower the voltage, so the researches of circuit operation in sub-threshold and near-threshold voltage have been proposed and discussed widely []. Digital circuit designs often employ extensive FF for data buffering or pipelining, and the circuit efficiency of FF designs largely affects the overall power consumption and chip area []. In this letter, we revisit the basic FF problem. A transmission gate based FF (TGFF) design is used most widely, due to its fully static operation, robust voltage scaling, and none data contention. However, a major drawback of TGFF is the excessive working load to the clock signal, which leads to considerably dynamic power even in low or zero switching activity. Many low power FF designs have been proposed to overcome this problem. For the FF design presented in [, ], although the dynamic power consumption, particularly in low switching activities, can benefit from the aggressive circuit simplification measures, the robustness in low V DD operations is compromised due to a weakened charging P-logic. This design is further simplified in [4] and the transistor-count reduces from to 9. By employing pass transistor logic (served as an extra charging path) to speed up the setup time, the overall performance of design [4] is better than that of design [, ]. However, the nmos type pass transistor served as an auxiliary charging path fails in low voltage operations, which limits its applications. Design [5] is based on conventional dynamic TSPC FF circuitry but modified for fully static operations. The height of its nmos logic increases to. This calls for large sized transistors leading to a larger layout area [7]. In this letter, a novel TSPC based FF design featuring a true-single-phase clock operation is presented, to maintain the advantages in low operating voltage while reducing clock load. The design also exhibits a better layout area and a shorter critical path comparing with previous design. Manuscript received Feb. 0, 08; accepted Jul. 5, 08 Information and Communication Engineering, Chaoyang University of Technology, Taiwan E-mail : jflin@cyut.edu.tw II. PROPOSED DESIGN A FF design called ACFF is proposed in []. In this

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.8, NO.5, OCTOBER, 08 64 Master M M5 M6 M8 M 4 CK M CK 4 net M net M M9 / M7 M M4 CK netb M5 M0 M4 CK M6 Slave M 4/ M7 M4 n /.5 M8 M9 CK M0 M M Fig.. MOS schematic of SSCFF design [5]. Master Slave M5 M6 M8 M 4 CK M net M M4 CK 4 CK net M / M9 netb M M7 M M5 M0 M4 CK M 4/ M6 M n /.5 M7 M8 CK M9 M0 M equal to input. In this phase, previous data of output will be maintained by slave latch through transistors M7-M. When CK= and node net=0, node net will charge up to V DD through transistor M6. When CK= and node net=, node net will discharge to 0 through M9- M0, and input will be transmitted to output through M-M6. In conclusion, net and netb both equal to input. In this design, transistor M5 is used to eliminate the glitch of n in conventional TSPC design, when CK rises and =0 [6]. The accuracy of circuit remains the same whether transistor M6 exist or not. In other words, transistor M6 is unnecessary and thus can be removed. The optimized FF design is (a).5.0 CK -.5.0 -.5.0 netb -.5.0 net -.5.0 n -.5.0 - n n.5n n.5n n.5n 4n 4.5n 5n t(s) (a) (b) Fig.. Proposed FF design (a) MOS schematic, (b) Post-layout simulation waveforms. design, as the switching activity rises, the slave-latch encounters data contention and power saving reduction. It even brings on the concern of higher operating voltage. In addition, the level restoring pair of the master-latch also causes a longer setup time. Finally, there are floating problems in some nodes inside this circuit, so there will be limitations when using ACFF design [4]. A static contention free single phase clocked flip-flop design (as Fig. ) is proposed to overcome these problems [5]. It is composed of a conventional TSPC with 9 blue transistors and additional 5 transistors. Master latch is composed of transistors M-M, and slave latch is composed of M-M4. The operation is fully static. When CK=0, node net will charge up to V DD (conducting by transistor M8), and node netb will TGFF (b) (c) SSCFF Proposed Fig.. FFs performances (a) Power performance at different activity, (b) PDP performances at different process corners, (c) PDP performance at different supply voltage.

64 JIN-FA LIN et al : A MODIFIED STATIC CONTENTION FREE SINGLE PHASE CLOCKED FLIP-FLOP DESIGN FOR LOW Table. Comparison of FF Designs @.0GHz/TT-Corner FF Designs TGFF SSCFF Proposed Number of Transistors 4 4 Normalized Layout Area (μm ).0.07.0 Setup Time (ps) 4.57 9. 7.5 Hold Time (ps) -8..9.44 Clock-to- Delay (ps) 68.07 67.58 60.86 PDP(5%Activity) fj 7 0.4 0.6 Average Power(00%) μw 6.00 4.44.8 Average Power(50%) μw.00 9.7 8.67 Average Power(5%) μw 8.8 6.4 5.96 Average Power(.5%) μw 7.06 5.0 4.6 Average Power(0%) μw 5.80.69.0 90p 85p 80p C to (ps) 75p 70p 65p 60p TGFF SSCFF 55p Proposed FF 50p 0p 0p 40p 60p 80p 00p 0p 40p 60p 80p 00p CK input slew(ps) Fig. 4. Input slew dependency. Fig. 5. Monte-Carlo simulation results at 0.4 V. proposed as Fig.. Since the height of nmos transistors in series reduces from to compared with that of SSCFF design [5], smaller sized transistors can be adopted to achieve the design. The speed, power consumption, and layout area are all better than previous designs. In the simulated waveform chart (as Fig. (b)), as we can see both nodes net and netb are the same when CK=. Meanwhile, there is also no any glitch problem in output n (at rising edges of clock). III. SIMULATION RESULTS The proposed design is compared with the other two static FF designs, the TGFF and the SSCFF. Note that, a TSPC based FF design using 8-transistors is proposed in [7]. However, there are floating problems in some nodes inside this FF design, so it is not included in the discussion. The target technology is the TSMC 40nm CMOS process. The size of transistor depends on the optimization of power-delay-product (PDP) and the function at normal V DD (.0v). Five test patterns are applied. Each of them corresponds to a different data switching probability. The simulation results are summarized in Table. First, the layout-area of proposed design equals TGFF. Because the proposed design lowers the linked height of nmos tree, it can use lesser and smaller transistors to reduce the total layout-area. On the other hand, despite the number of transistor of SSCFF and TGFF are the same, the layout-area of SSCFF is 7% (approximately one polypitch width) larger than TGFF due to its need for larger transistor [5]. Second, the proposed design has the best power efficiency. The power consumption (at 5% data switching) of the proposed design is 6.8%, less than TGFF design. When the data switching activity is 0%, the power saving is 4.% better than TGFF. As the data switching activities decline, the power saving is more significant. In other words, the power arising from the clock signal dominates the case. Third, the setup time of the proposed design is lower than both SSCFF and TGFF designs due to the optimized circuit. Fourth, besides TGFF, the hold time of SSCFF and the proposed design are both positive. Finally, the proposed design is better than SSCFF and TGFF in both clock-to- delay and

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.8, NO.5, OCTOBER, 08 64 PDP C. When the data switching activity is 0%, the PDP saving of the proposed design is 49.% and 9.7% better than TGFF and SSCFF, respectively. Fig. shows the average power consumption at different data switching activity, the PDP C at different process corners and the PDP C at different supply voltages. All FFs work properly with process variations. The performance edge of the proposed design outperforms in all cases. This is mainly attributed to the optimization measure in the proposed design to remove one transistor along the critical path, which lowers the level of transistor stacking from to ad facilitates the use of smaller sized transistors lowering the power consumption. Fig. 4 presents the tolerance to clock skew of these three designs. The clock input slew ranges from 0ps to 00ps to test the performance of clock-to- delay in each FF design. The result shows that the proposed design and SSCFF are better than TGFF due to both designs are true-single-phase circuit structure. The proposed design has smaller transistor size and fewer MOS, so it has the better tolerance to clock skew. Fig. 5 presents the Monte-Carlo simulation results of PDP C derived by executing 000 runs at 0.4V supply voltage. The plot has a format of power consumption as the X axis and the clock to delay as the Y axis. Therefore, the closer the point is to the lower left part of the plot, the better performance this design stands for. The simulation points correspond to the same FF design are marked with the same symbol ("circle" for our design, "cross" for the TGFF design and "triangle" for the SSCFF design) while symbol colors are used to distinguish the process corners. From the simulation results, the advantage of the proposed design is well kept in all simulation trials. V. CONCLUSIONS A novel TSPC based FF design supporting low power operation is presented. The proposed design successfully removes one redundant transistor from previous design and thus achieves better various performances. Conducted evaluations show that the design is the most power-economical in all compared designs. The proposed design can be employed in cell library design targeting low voltage and low power applications. ACKNOWLEDGMENTS This work was supported by the Ministry of Science and Technology, Taiwan under contract No. 06--E- 4-0-. The authors would like to thank National Chip Implementation Center (CIC), Taiwan for technical support in simulations. The authors also thank Mr. Chen- Chang Lai and Mr. Yu-Min Chi for their assistance in simulation and layout. REFERENCES [] M. Alioto, Ultra-low power VLSI circuit design demystified and explained: A tutorial, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no., pp. 9, Jan. 0. [] K. T. Chen, et al.: A 77% energy saving - transistor single phase clocking D-flip-flop with adoptive-coupling configuration in 40nm CMOS, ISSCC Dig. Tech. Papers, Feb. 0, pp. 8-9. [] N. Kawai, et al.:, A fully static topologicallycompressed -transistor flip-flop with 75% power saving, IEEE J. Solid-State Circuits, vol. 49, no., pp. 56 5, Nov. 04. [4] Jin-Fa. Lin, et al.: "Low-power 9-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes," IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 5, pp. 0 044, Nov. 07. [5] Y. Kim, et al.: A static contention-free singlephase-clocked 4 T flip flop in 45 nm for lowpower applications, IEEE ISSCC Dig. Tech. Papers, Feb. 04, pp. 466 467. [6] J. Yuan and C. Svensson, New single-clock CMOS latches and flip flops with improved speed and power savings, IEEE J. Solid-State Circuits, vol., no., pp. 6 69, Jan. 997. [7] F. Stas and D. Bol, 0.4V 8fJ/cycle retentive true-single-phase-clock 8T flip-flop in 8nm FDSOI CMOS, in Proc. IEEE ISCAS, Mar. 07, pp. 779 78.

644 JIN-FA LIN et al : A MODIFIED STATIC CONTENTION FREE SINGLE PHASE CLOCKED FLIP-FLOP DESIGN FOR LOW Jin-Fa Lin received his master s degree in electrical engineering from National Chung Cheng University, Chiayi, Taiwan, in 997 and his Ph.D. in engineering science and technology from National Yunlin University of Science and Technology, Yunlin, Taiwan, in 008. In 00, he joined the Department of Information and Communication of Chaoyang University of Technology, Taichung, Taiwan, where he is currently an Assistance Professor. His research interests include asynchronous VLSI designs, low-power VLSI circuit designs, and low voltage embedded memory circuit design. Ming-Yan Tsai received the B.S. degree in the Department of Information and Communication from Chaoyang University of Technology, Taichung, Taiwan, in 06. He is currently working toward the M.S. degree in Electronic Engineering at the National Yunlin University of Science & Technology, Yunlin, Taiwan. His research interests are in the areas of low power and low voltage embedded memory circuit designs.