EECS 373 Design of Microprocessor-Based Systems A day of Misc. Topics Mark Brehob University of Michigan Lecture 12: Finish up Analog and Digital converters Finish design rules Quick discussion of MMIO in C (time allowing) Discuss student presentations
Announcements HW5 out today. Due Tuesday Oct 23 rd. 2
Analog and Digital Converters Last time we made it through the basic ideas. The world is analog our computers are digital. So we need to convert analog values to digital ones. There are two main issues: Rounding error: we are taking real numbers and converting them to digital values. This is called quantization error. Sampling: we are taking a value continuous in time and only measuring it at discrete times. 3
Quantization error Ideal transfer function Ideal transfer with ½ LSB offset Here we take all values from 0 to ⅛ and call them 000. Here we shift over the value by ½ LSB. This means the ideal transfer function and the actual one are never more than ½ LSB (1/16 in this case) off. http://www.embedded.com/showarticle.jhtml?articleid=60403334 4
Questions on conversion and quantization error. Say you have an ideal 3-bit analog to digital converter (ADC) with a full scale value of 4V and a ½ LSB offset. How big is an LSB? What digital values would you get for each of the following analog inputs? 2.3V 1.2V 0.1V What values would an ideal 3-bit DAC generate from the above digital outputs? How much error is there? 5
Sampling and aliasing What sample rate do we need? Too little: we can t reconstruct the signal we care about Too much: waste computation, energy, resources If there are frequency components more than ½ f samples we are going to get aliasing. Need an analog filter fsamples 2 f max 6
Converter Architectures. There are a huge number of converter architectures. Take EECS 511 which is basically an ADC class. There is a lot to it. We re just looking at the basics This course covers most of the well known analog to digital conversion schemes. These include the flash, folding, multi-step and pipeline Nyquist rate, architectures. Oversampling converters are also discussed. Practical design work is a significant part of this course. Students design and model complete converters 7
DAC #1: Voltage Divider Vref R Din 2 2-to-4 decoder Fast Size (transistors, switches)? Accuracy? Monotonicity? R R Vout R
DAC #2: R/2R Ladder Vref R R R 2R 2R 2R 2R 2R Iout D3 (MSB) D2 D1 D0 (LSB) Size? Accuracy? Monotonicity? (Consider 0111 -> 1000)
ADC #1: Flash Vref Vin R + _ priority encoder 3 R R + _ + _ 2 1 2 Dout R Vcc 0
ADC #2: Single-Slope Integration Vin Vcc I + _ C done Start: Reset counter, discharge C. EN* n-bit counter CLK Charge C at fixed current I until Vc > Vin. How should C, I, n, and CLK be related? Final counter value is Dout. Conversion may take several milliseconds. Good differential linearity. Absolute linearity depends on precision of C, I, and clock.
ADC #3: Successive Approximation (SAR) 1 Sample Multiple cycles Requires N-cycles per sample where N is # of bits Goes from MSB to LSB Not good for high-speed ADCs 12
Errors and ADCs Figures and some text from: Understanding analog to digital converter specifications. By Len Staller http://www.embedded.com/showarticle.jhtml?articleid=604 03334 Key concept here is that the specification provides worst case values.
Integral nonlinearity The integral nonlinearity (INL) is the deviation of an ADC's transfer function from a straight line. This line is often a best-fit line among the points in the plot but can also be a line that connects the highest and lowest data points, or endpoints. INL is determined by measuring the voltage at which all code transitions occur and comparing them to the ideal. The difference between the ideal voltage levels at which code transitions occur and the actual voltage is the INL error, expressed in LSBs. INL error at any given point in an ADC's transfer function is the accumulation of all DNL errors of all previous (or lower) ADC codes, hence it's called integral nonlinearity.
It s a promise it won t be worse than X. Differential nonlinearity DNL is the worst cases variation of actual step size vs. ideal step size.
Sometimes the intentional ½ LSB shift is included here!
Full-scale error is also sometimes called gain error full-scale error is the difference between the ideal code transition to the highest output code and the actual transition to the output code when the offset error is zero.
Errors Once again: Errors in a specification are worst case. So if you have an INL of ±.25 LSB, you know that the device will never have more than.25 LSB error from its ideal value. That of course assumes you are operating within the specification Temperature, input voltage, input current available, etc. INL and DNL are the ones I expect you to work with
Glitches x z Full adder (from Wikipedia) y Consider the adjacent circuit diagram. Assuming the XOR gates have a delay of 0.2ns while AND and OR gates have a delay of 0.1ns, fill in the following chart. Only selected causality arrows shown
Glitching: a summary When input(s) change The output can be wrong for a time However, that time is bounded And more so, the output can change during this computation time even if the output ends up where it started!
Effect of Glitches Think back to EECS 370. Why don t glitches cause errors? The trick is that the inputs all change at the same time In this case, the ID/EX registers all change some time shortly after the rising edge of the clock. And we ve chosen the clock period such that the next edge doesn t happen until the combinational logic has stopped glitching. In fact, we use the worst-case combinational logic delay in the whole system when determining the clock period!
So, how can glitches hurt us? There are a handful of places: Asynchronous resets If you ve got a flip-flop that has an asynchronous reset (or preset ) you need to be sure the input can t glitch. Clocks That pretty much means you need a flipflop driving the input (which means you probably should have used a sync. reset!) If you are using combinational logic to drive a clock, you are likely going to get extra clock edges. Traditionally, CLR is used to indicate async reset. R or reset for sync. reset. If clk is high and cond glitches, you get extra edges!
Design rules 1. Thou shalt not use asynchronous resets 2. Thou shalt not drive a clock with anything other than a clock or directly off of a flip-flop s output X X
Really? Seriously? People do use asynchronous resets and clock gating! Yep. And people use goto in C programs. Sometimes they are the right thing. But you have to think really hard about them to insure that they won t cause you problems. Our simple bus used combinational logic for the clock Works because REQ goes low only after everything else has stopped switching So no glitch. Not fun to reason about Avoid unless you must Then think really carefully.
Setup and hold time The idea is simple. When the clock is changing if the data is also changing it is hard to tell what the data is. Hardware can t always tell And you can get meta-stable behavior too (very unlikely but ) So we have a guard band around the clock rising time during which we don t allow the data to change. See diagram. We call the time before the clockedge setup time and the time after hold time
So what happens if we violate set-up or hold time? Often just get one of the two values. And that often is just fine. Consider getting a button press from the user. If the button gets pressed at the same time as the clock edge, we might see the button now or next clock. Either is generally fine when it comes to human input. But bad things could happen. The flip-flop s output might not settle out to a 0 or a 1 That could cause later devices to mess up. More likely, if that input is going to two places, one might see a 0 the other a 1 Important: don t feed an async input to multiple places!
Example A common thing to do is reset a state machine using a button. User can reset the system. Because the button transition could violate setup or hold time, some state bits of the state machine might come out of reset at different times. And you quickly end up at a wrong or illegal state.
So Dealing with inputs not synchronized to our local clock is a problem. Likely to violate setup or hold time. That could lead to things breaking. So we need a clock synchronization circuit. First flip-flop might have problems. Second should be fine. Sometimes use a third if really paranoid Safety-critical system for example. Figure from http://www.eeweb.com/electronics-quiz/solving-metastability-design-issues, we use the same thing to deal with external inputs too!
Design rules 3. Thou shalt use a clock synchronization circuit when changing clock domains or using unclocked inputs! /* Synchonization of Asynchronous switch input */ always@(posedge clk) begin sw0_pulse[0] <= sw_port[0]; sw0_pulse[1] <= sw0_pulse[0]; sw0_pulse[2] <= sw0_pulse[1]; end always @(posedge clk) SSELr <= {SSELr[1:0], SSEL}; Also, be aware most FPGA libraries have resources to make dealing with multiple clock domains e Bi-directional queues generally.
Student presentations Each project group will give a 10-12 minute technical talk in class. Each group will have one graded practice session. The goal of these presentations are to educate students about a wide variety of embedded systems topics Provide students with the opportunity practice preparing and giving technical talks to their peers. Each group should send me an e-mail: CC all group members Have 373 Presentation as the subject List 3 ideas for topics. 31