Unit 11 Latches and Flip-Flops 1
Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables, there are 2 n possible binary input combinations. For each binary combination of the input variables, there is one possible output. 2018/2/5 Combinational Logic PJF- 2
Combinational Circuits (cont.) Hence, a combinational circuit can be described by: 1. A truth table that lists the output values for each combination of the input variables, or 2. m Boolean functions, one for each output variable. n-inputs Combinational Circuit m-outputs 2018/2/5 Combinational Logic PJF- 3
Combinational vs. Sequential Circuits Combinational circuits are memory-less. Thus, the output value depends ONLY on the current input values. Sequential circuits consist of combinational logic as well as memory elements (used to store certain circuit states). Outputs depend on BOTH current input values and previous input values (kept in the storage elements). 2018/2/5 Combinational Logic PJF- 4
Combinational vs. Sequential Circuits n-inputs Combinational Circuit Combinational Circuit m-outputs (Depend only on inputs) n-inputs Combinational Circuit Next state Storage Elements m-outputs Present state Sequential Circuit 2018/2/5 Combinational Logic PJF- 5
Sequential Logic Output depends not only on current input but also on past input values, e.g., design a counter Outputs from the system are fed back as new inputs Need some type of memory to remember the past input values 2018/2/5 feed Sequential back Circuits PJF - 6
Memory Elements Memory elements are needed in most digital logic circuits to hold (remember) logic values 2 basic types of memory elements: Latches Level-sensitive to inputs Flip-flops Edge-triggered on active edge of clock 7
Set-Reset (SR) Latch (NOR) The simplest memory element is a set-reset (SR) latch Cross-coupled NOR gates Active high inputs :R (reset) and S (set) Only one input can be active to avoid undefined state Outputs: Q and Q => Q = current state of latch 8
Set-Reset (SR) Latch (NOR) an input S = 1 sets the output to Q = 1 an input R = 1 resets the output to Q = 0 with the restriction that R and S cannot be 1 simultaneously 9
Set-Reset (SR) Latch (NOR) Characteristic Equation (next-state equation) 10
Set-Reset (SR) Latch (NAND) 11
Set-Reset (SR) Latch (NAND) Characteristic Equation (next-state equation) 12
Timing Diagram Timing Diagram for S-R Latch 13
Gated Latches Gated latches have an additional input called the gate or enable input When the gate input (enable) is inactive, which may be the high or low value, the state of the latch cannot change. When the gate input is active, the latch is controlled by the other inputs and operates as indicated in the preceding section. 14
SR Latch with Gated Input 15
Gated D Latch One way to eliminate the undesirable condition of the indeterminate state in SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done in the D latch. 16
Gated D Latch 17
Flip-Flops The state of a latch or flip-flop is switched by a change in the control input. This momentary change is called a trigger and the transition it causes is said to trigger the flipflop. The D latch with pulses in its control input is essentially a flip-flop that is triggered every time the pulse goes to the logic 1 level. As long as the pulse input remains in the level, any changes in the data input will change the output and the state of the latch. 18
Clock Response in Latch A positive level response in the control input allows changes, in the output when the D input changes while the clock pulse stays at logic 1. 19
Clock Response in Flip-Flop 20
Edge-Triggered D Flip-Flop The first latch is called the master and the second the slave. The circuit samples the D input and changes its output Q only at the negative-edge of the controlling clock. D 1 1 0 0 1 1 Y 1 1 0 0 1 1 Q? 1 1 0 0 1. CLK 21
Edge-Triggered D Flip-Flop Timing Diagram for D Flip-Flop (Falling-Edge Trigger( 22
Graphic Symbol for D Flip-Flop 23
Timing terminology and constraints for a FF Setup time t su : Amount of time the input must be stable before the clock transitions high (or low for negative-edge triggered FF) Hold time t h : Amount of time the input must be stable after the clock transitions high (or low for negative-edge triggered FF) Clock width t w : Minimum clock width that must be met in order for FF to work properly Propagation delays t p-lh and t p-hl : Propagation delay (high to low, low to high) 24
Determination of Minimum Clock Period 25
S-R Flip-Flop 26
J-K Flip-Flop 27
T Flip-Flop 28
Flip-Flop Characteristic Tables 29
Characteristic Equations D flip-flop Characteristic Equations Q(t + 1) = D JK flip-flop Characteristic Equations Q(t + 1) = JQ` + K`Q T flip-flop Characteristic Equations Q(t + 1) = T Q = TQ` + T`Q 30
Flip-Flops with Additional Inputs Flip-flops often have additional inputs which can be used to set the flip-flops to an initial state independent of the clock 9/15/09 - L20 Flip Flops D Flip-Flop with Clear and Preset 31
Flip-Flops with Additional Inputs Clr and Pre are often referred to as asynchronous clear and preset inputs because their operation does not depend on the clock. 32 Timing Diagram for D Flip-Flop with Asynchronous Clear and Preset
Flip-Flop with Clock Enable In synchronous digital systems, the flip-flops are usually driven by a common clock so that all state changes occur at the same time in response to the same clock edge. When designing such systems, we frequently encounter situations where we want some flip-flops to hold existing data even though the data input to the flip-flops may be changing. 33
Flip-Flop with Clock Enable One way to do this is to gate the clock has some potential problems Better way is to use a flip-flop with a clock enable (CE). Such flip-flops are commonly used in CPLDs and FPGAs. 34
HomeWork Solve the following problems from the textbook unit 11: 2, 4, 6, 9, 10, 13, 14, 16, 24 35
Finally. Any Questions?