What Does it Take to Build a Complete Test Flow for 3-D IC?

What Does it Take to Build a Complete Test Flow for 3-D IC? Brio Keller, Bassilios Petrakis, Cadece Thaks to : Sadeep Goel, TSMC EDPS, Moterey, CA April 5-6, 202

Ackowledgemets TSMC Ashok Mehta imec Erik Ja Mariisse Cadece Sergej Deutsch (ow at Duke Uiv.) Vivek Chickermae, Subhasish Mukherjee 2 202 Cadece Desig Systems, Ic. All rights reserved.

Purpose 3D stackig of ICs is a hot DFT topic Usig s as die itercoects has may advatages 3D DFT is eeded to do modular testig of Die iteral logic Die itercoects Presetatio focuses o Modular testig techiques of 3D stackig ICs with A tool flow for automatic isertio of 3D wrappers Method ca be exteded to other itercoect types (e.g., iterposers) 3 202 Cadece Desig Systems, Ic. All rights reserved.

Presetatio outlie Itroductio 3D-DFT requiremets 3D-DfT architecture 3D wrapper geeratio flow Results Coclusios 4 202 Cadece Desig Systems, Ic. All rights reserved.

. itroductio Through Silico Vias (s) 3D chip stackig with wire-bods Heterogeeous techologies Dese itegratio, small footprit Through-Silico Vias Metal vias that provide itercoects from frot-side to back-side through silico substrate beefits Eve deser itegratio High desity, low capacitace Icreased badwidth Icreased performace Lower power dissipatio Lower maufacturig cost? board System-i-Package (SiP) board -Based 3D-SIC 5 202 Cadece Desig Systems, Ic. All rights reserved.

2. 3D-DFT requiremets Test access distictly differet Pre-Bod Test Focus o die-iteral circuitry Origial thick or thied-dow wafer Probe access at DUT Probe o micro-bumps or dedicated s Mid-Bod / Post-Bod / Fial Tests Focus o itercoects ad die-iteral circuitry Test access (probe or socket) at bottom die Require DfT to propagate test stimuli/resposes up/dow through stack Requiremets Modular test: core, die, itercoect TestTur: test up till this die TestElevator: test higher-up die die top die middle die bottom die 6 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Example fuctioal desig Die 3 Core 3 2 stacked dies, possibly core-based Iter-coect: s Extra-coect: pis Die 2 Core 2. Core 2.2 Die Core. Core.2 Core.3 pi pi pi pi 7 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Example fuctioal desig 2 stacked dies, possibly core-based Iter-coect: s Extra-coect: pis Die 3 Core 3 BIST Example existig desig for test Core: iteral sca,, LBIST, MBIST; wrappers, TAMS Stack product: IEEE std 49. Die 2 Core 2. Core 2.2 Die Core. Core.2 Core.3 IEEE 49. Boudary Sca pi pi pi pi pi pi 8 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Example fuctioal desig 2 stacked dies, possibly core-based Iter-coect: s Extra-coect: pis Example Existig Desig-for-Test Core: iteral sca,, LBIST, MBIST; wrappers, TAMs Stack product: IEEE Std 49. 3D-DFT Architecture Test wrapper per die Based o IEEE 49. or 500 Two etry/exit poits per die:. Pre-bod : extra probe s 2. Post-bod : extra s [Mariisse et al. VTS 0 / 3DIC 0] Die 3 Core 3 Die 2 Core 2. Die BIST Core. Core.2 Core.3 Board Core 2.2 IEEE 49. Boudary Sca pi pi pi pi pi pi 9 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Modes of operatio Pre-bod Die test Post-bod Die /2/3 test Itercoect -2 + 2-3 Die 3 Core 3 BIST Post-packagig Serial debug 0 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Modes of operatio Pre-bod Die test Post-bod Die /2/3 test Itercoect -2 + 2-3 Post-packagig Serial debug Die 3 Core 3 BIST Die 2 Core 2. Core 2.2 itest tur Die Core. Core.2 Core.3 IEEE 49. Boudary Sca pi pi pi pi pi pi 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Modes of operatio Pre-bod Die test Post-bod Die /2/3 test Itercoect -2 + 2-3 Post-packagig Serial debug itest tur Die 3 Core 3 BIST Die 2 Core 2. Core 2.2 elevate Die Core. Core.2 Core.3 IEEE 49. Boudary Sca pi pi pi pi pi pi 2 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Modes of operatio Pre-bod Die test Post-bod Die /2/3 test Itercoect -2 + 2-3 Post-packagig Serial debug itest tur elevate Die 3 Core 3 BIST Die 2 Core 2. Core 2.2 elevate Die Core. Core.2 Core.3 IEEE 49. Boudary Sca pi pi pi pi pi pi 3 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Modes of operatio Pre-bod Die test Post-bod Die /2/3 test Itercoect -2 + 2-3 Post-packagig Serial debug extest tur extest elevate Die 3 Core 3 BIST Die 2 Core 2. Core 2.2 extest elevate Die Core. Core.2 Core.3 IEEE 49. Boudary Sca pi pi pi pi pi pi 4 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Modes of operatio Pre-bod Die test Post-bod Die /2/3 test Itercoect -2 + 2-3 Post-packagig Serial debug Die 3 Core 3 BIST Die 2 Core 2. Core 2.2 Die Core. Core.2 Core.3 IEEE 49. Boudary Sca pi pi pi pi pi pi Board 5 202 Cadece Desig Systems, Ic. All rights reserved.

to/from top die Wrapper Boudary Register Wrapper Boudary Register Parallel TAM WPIs 3. 3D-DFT architecture Schematic view: wrapped die 6 202 Cadece Desig Systems, Ic. All rights reserved. WPO* m WPI* WPOs WSO WSI WSC 6 Die x switch box switch box Serial TAM m sca chai WSIs WSOs sca chai WSCs 6 WIR Wrapper Boudary Register Wrapper Boudary Register switch box switch box to/from bottom die Parallel TAM Serial TAM

to/from top die Wrapper Boudary Register Wrapper Boudary Register Parallel TAM WPIs WPOs switch box switch box Serial TAM WSIs 3. 3D-DFT architecture Schematic view: wrapped die Serial Test Access Mechaism (TAM) Istructios Low-badwidth test data Typical usage: board-/system-level debug 7 202 Cadece Desig Systems, Ic. All rights reserved. m WPO* m WPI* WSO WSI WSC 6 Die x sca chai sca chai WSOs WSCs 6 WIR Wrapper Boudary Register Wrapper Boudary Register switch box switch box to/from bottom die Parallel TAM Serial TAM

3. 3D-DFT architecture Schematic view: wrapped die Serial Test Access Mechaism (TAM) Istructios Low-badwidth test data Typical usage: board-/system-level debug to/from bottom die Wrapper Boudary Register Die x sca chai sca chai Wrapper Boudary Register to/from top die m Parallel TAM High-badwidth test data Typical usage: Volume productio testig i semicoductor factory Parallel TAM Serial TAM WPO* m WPI* WSO WSI WSC 6 switch box WIR switch box WPIs WPOs WSIs WSOs WSCs 6 Parallel TAM Serial TAM 8 202 Cadece Desig Systems, Ic. All rights reserved.

Die N sca chai sca chai switch box switch box WIR Wrapper Boudary Register Wrapper Boudary Register switch box switch box Wrapper Boudary Register Wrapper Boudary Register switch box switch box Die m WPO* m WPI* sca chai WPIs WSIs 6 WSO 3. 3D-DFT architecture Schematic view: stack WSI WSC 6 sca chai Wrapper Boudary Register Wrapper Boudary Register switch box switch box Boudary Sca Register Boudary Sca Register Fuctioal I/Os / WPI/WPO WPO* WPI* switch box switch box TDO WSO TRSTN* WIR WSI TMS TCK WSC Adapter 49. TDI 6 9 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Flexible istructio set-up Implemeted istructios decided at desig-time Differet istructios eable differet test access paths Serial Prebod Itest Tur Parallel Postbod Bypass Itest Extest Bypass Tur Elevator Flexible test schedulig decided at test-time Iclusio/exclusio of tests for differet phases of test flow Reorderig of tests (reject-orieted aalysis, abort-o-first-fail) 20 202 Cadece Desig Systems, Ic. All rights reserved.

3. 3D-DFT architecture Test mode set-up example Die (bottom) Die 2 Die 3 (top) WPO* WPO* WPO* WPI* TDO switch box sca chai sca chai WBR switch box WPI* switch box sca chai sca chai WBR switch box WPI* switch box sca chai sca chai WBR switch box TRSTN* TMS TCK TDI 49. WIR 6 WSO WSI WSC WIR2 6 WSO WSI WSC WIR3 ParallelPostbod BypassElevator ParallelPostbod ItestTur ParallelPostbod BypassTur Note: Figure abstracts from fuctioal circuitry ad oly shows DfT features 2 202 Cadece Desig Systems, Ic. All rights reserved.

4. 3D wrapper geeratio flow DfT Isertio with Ecouter RTL Compiler 3D Wrapper Isertio WIR Isertio Desig Library User-defied Parameters Wrapper Cell Isertio Bypass Register Isertio Multimode Sca Chai Cofiguratio JTAG Isertio JTAG Isertio TAP Cotroller Isertio Boudary Cell Isertio JTAG-to-500 Wrapped Desig 22 202 Cadece Desig Systems, Ic. All rights reserved.

4. 3D wrapper geeratio flow JTAG isertio JTAG macro isertio (TAP cotroller, IR, decode logic) Boudary cell isertio at Desig bottom I/Os JTAG-to-500 Library (prevetig pis) Operatio sequece a. JTAG: User-defied WIR Parameters Program b. 500: WIR loadig 2a. JTAG: sca 2b. 500: sca Requires JTAG-to-500 adapter toward/from exteral I/Os 3D Wrapper Isertio (RC) WIR Isertio Wrapper Cell Isertio Bypass Register Isertio Multi-Mode Sca Chai Cofiguratio J TDI TCK JTAG Isertio J J J J J Wrapped Desig BPO[0] BPO[] OEN BPI[0] BPI[] BPI[2] WPO WPI WSI WSO w w w w JTAG Isertio w TAP Cotroller Isertio w Boudary Cell Isertio JTAG-to-500 WSC sca chais WIR JTAG-to- 500 w w w w w w toward/from top die WPIs WPOs WSOs WSIs TMS TRST JTAG Macro TDO 23 202 Cadece Desig Systems, Ic. All rights reserved.

4. 3D wrapper geeratio flow 3D wrapper schematic view 24 202 Cadece Desig Systems, Ic. All rights reserved.

5. Results 3D-DFT wrapper ad ski model TSMC test chip 65m CMOS Fuctioal desig 727 fuctioal I/Os 229,249 std. cells 28,224 flip-flops Area 2,070,536µm2 3D wrapper area:.0% of the chip std. cell area egligible for realistic desigs DfT Area: 3D Wrapper Die sca chai sca chai IEEE 49. Boudary Sca +7.8% +.0% +0.6% 25 202 Cadece Desig Systems, Ic. All rights reserved.

6. Coclusio Summary: DFT for pre- ad post-bod 3D chip stackig usig Through-Silico Vias has much potetial 3D test challeges iclude pre-bod ad post-bod testig 3D-DfT architecture Test-oly s for pre-bod testig Serial ad Parallel test access mechaisms TestTurs: to upper dies i stack TestElevator mode: for test paths to/from upper dies 3D wrapper isertio flow Iserts 500-style wrappers ad 49. for bottom die Geerates iput to ru ATPG Idustrial case study: egligible area costs of 3D wrapper 26 202 Cadece Desig Systems, Ic. All rights reserved.

27 202 Cadece Desig Systems, Ic. All rights reserved.