Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 0 Office Hours: BKD 360-7 Monday 9:00-0:30, :30-3:30 Tuesday 0:30-:30
Announcement HW4 posted on the course web site Chapter 5: 4(b,c,e), 20a, 22a, 56 Write down all the steps that you have done to obtain your answers. Due date: July 6, 2009 (Thursday) There will be a quiz today. 2
Review NAND gate is a universal gate. NOR gate is a universal gate. 3
NAND Gate as a Universal Gate NAND gates are sometimes called universal gates because they can be used to produce the other basic Boolean functions. A Inverter A A B AND gate AB A B A + B A B A + B OR gate NOR gate 4
Example Implement the following logic circuit using only NAND gates: Solution: C Negative-OR NAND C 5 C
Example Implement the following logic circuit using only NAND gates: Solution: Negative-OR NAND It is easy to turn AND-OR configuration into a NANDgate-only circuit 6
NOR Gate as a Universal Gate NOR gates are also universal gates and can form all of the basic gates. A Inverter A A B OR gate A + B A B AB A B AB AND gate NAND gate 7
Example Implement the following logic circuit using only NOR gates: Solution: 8
Combinational Logic We studied the theoretical principles used in combinational logic design. We will build on that foundation and describe many of the devices, structures, and methods used by engineers to solve practical digital design problems. A complex circuit or system is conceived as a collection of smaller subsystems, each of which has a much simpler description. 9
Digital System Concept A digital system is an arrangement of the individual logic functions connected to perform a specified operation or produce a defined output. 0
Combinational Building Blocks There are several straightforward structures that turn up quite regularly as building blocks in larger systems. Encoder Decoders Comparators Multiplexers Where can we find these building blocks?
Fixed-function IC An integrated circuit (IC) is an electronic circuit that is constructed entirely on a single small chip of silicon. Two broad categories of digital ICs.. Fixed-function logic 2. Programmable logic In fixed-function logic, the logic functions are set by the manufacturer and cannot be changed. 2
Fixed-function IC package 3 Cutaway view of DIP (Dual-In-line Pins) chip
Complexity Classifications Fixed-function digital lcs are classified according to their complexity. Small-scale integration (SSI) up to ten equivalent gate circuits on a single chip basic gates and flip-flops. Medium-scale integration (MSI) from 0 to 00 equivalent gates on a chip. encoders, decoders, counters, registers, multiplexers, arithmetic circuits, small memories Large-scale integration (LSI) Very large-scale integration (VLSI) Ultra large-scale integration (ULSI) 4
SSI 74x00 5
MSI For the next couple lectures, we will study most of these 74-series MSI. 6
MSI 7 DECODER C D B A GN G2N O0N O2N O5N O0N ON ON O3N O4N O4N O3N O2N O7N O6N O5N O9N O8N 7454 inst BCD TO DEC D B C A O7N O8N O9N O0N O3N O2N ON O6N O5N O4N 7442 inst BCD TO 7SEG LTN B C D RBIN BIN A OB OC OE OD OF OG OA RBON 7447 inst2 COMPARATOR A3 B2 A2 AEBI AGBI ALBI A0 B0 B3 A B ALBO AGBO AEBO 7485 inst3 3:8 DECODER A B G C G2AN G2BN Y0N YN Y2N Y3N Y4N Y5N Y6N Y7N 7438 inst4 2:4 DECODER A A2 B B2 GN G2N Y0N Y20N Y3N Y2N YN Y2N Y22N Y23N 7439 inst5 ENCODER N 2N 3N 6N 5N 4N 9N 8N 7N CN BN AN DN 7447 inst6 ENCODER 5N 0N N 2N 3N 4N EIN 6N 7N AN A0N A2N EON GSN 7448 inst7 MULTIPLEXER GN C B A D5 D0 D D4 D3 D2 D6 D7 Y WN 745 inst8 MULTIPLEXER A B SEL B2 A3 B3 A2 B4 GN A4 Y2 Y Y4 Y3 7457 inst9 PARITY GEN. B A F E D I C G H EVEN ODD 74280 inst0 4 BIT ADDER CIN A A2 B2 A3 A4 B4 B B3 SUM4 COUT SUM SUM2 SUM3 74283 inst
Simple Decoder A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. Two simple decoders that detect the presence of the binary code 00 are shown below. The first has an active HIGH output; the second has an active LOW output. A 0 A X A 0 A X A 2 A 2 A 3 A 3 Active HIGH decoder for 00 Active LOW decoder for 00 8 (A 0 is the LSB and A 3 is the MSB)
Exercise Assume the output of the decoder shown below is a logic. What are the inputs to the decoder? A 0 = 0 A = A 2 = 0 A 3 = 9
Binary-to-Decimal Decoder The binary-to-decimal decoder shown here has 6 outputs one for each combination of binary inputs. 4-bit binary input 0 A 0 A A 2 A 3 Bin/Dec 0 2 3 4 5 6 7 8 9 0 2 3 4 5 0 The bubbles indicate active- LOW outputs. Decimal outputs 20
Application: Port Address Decoder Decoder can be used in computers for input/output selection. Computers communicate with peripherals by sending and/or receiving data through what is known as input/output (I/O) ports. A decoder can be used to select the I/O port so that data can be sent or received from a specific external device. 2
2:4 decoder 2-to-4 line decoder with enable input 22
Exercise Find the truth table of the -to-2 line decoder below. Then, implement the -to-2 line decoder. I Y0 Y 23
74x39: Dual 2:4 Decoder Two independent 2:4 decoders The outputs and the enable (E) input are active-low. When E is HIGH all outputs are forced HIGH. Most MSI decoders were originally designed with active- LOW output. E O 3 24 Notice that all of the signal names inside the symbol outline are active-high, and that bubbles indicate active-low inputs and outputs.
25 74x39
74x39: Logic diagram Active- LOW Enable This is a usual 2:4 decoder. 26 Active-LOW output because NAND gates are used instead of AND gates
Example: Building a larger decoder Construct a 3-to-8 decoder from two 2-to-4 decoders Notice that this part is equivalent to a :2 decoder. How can we add an active-high enable input? 27 Low order bits (A, A 0 ) select within decoders. High order bit (A 2 ) controls which decoder is active.
Building larger decoder from smaller ones To construct (k+n)-to-2 n+k decoders, can use. 2 n of k-to-2 k decoders with enable input and 2. one n-to-2n decoders. The connections are: For each of the k-to-2 k decoder with enable input, all have k input we put in A 0 A k-. The enable line of the r th decoder is connected to D r of the n-to-2 n decoders. The inputs of the n-to-2 n decoder get A k to A n+k-. Basically, each k-to-2 k decoder works on the last k bits. We use the first n bit, via the n-to-2 n decoder, to select which one (and only one) of the k-to-2 k decoders will be enabled. 28
Example Construct a 4:6 decoder with an active-low enable from three 2:4 decoders. 29
74x38: 3:8 Decoder Active-LOW outputs Three enable inputs. 30
Example Construct a 4:6 decoder with an active-low enable (EN) from two 74x38 decoder. 3
Example Construct a 5:32 decoder with two activelow enable and one active-high enable from four 74x38 and one 74x39. 32
74x54: 4:6 Decoder A LOW level on each chip select input is required to make the enable gate output (EN) HIGH. Include two active-low chip select (CS) lines which must be at the active level to enable the outputs. These lines can be used to expand the decoder to larger inputs. Alternative logic symbol 33 inst DECODER A B C D GN G2N 7454 O0N ON O2N O3N O4N O5N O6N O7N O8N O9N O0N ON O2N O3N O4N O5N
34 5:32 Decoder
Decoder as general purpose logic Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n -line decoder and m OR gate Observe that the 3:8 decoder generates all possible minterms. 35
Example Implement a full adder circuit with a decoder and OR gates S = X,Y,Z (,2,4,7) C = X,Y,Z (3,5,6,7) 36 Inputs Outputs X Y Z C A B C in C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 out S S 0 0 0 0
Other Decoders In general, a decoder converts coded information, such as binary number, into non-coded form. Later, (if time permitted) we will talk about other types of decoder. 37