Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Digital Fundamentals CETT 1425 Lab 7 Asynchronous Ripple Counters Name: Date: Objectives: To design a MOD 11 asynchronous ripple counter. To define the operation of a ripple counter using a state transition diagram. To construct and evaluate a MOD 11 asynchronous ripple counter. To calculate and measure the output frequency of an asynchronous ripple counter. Suggested Reading Chapter 7, Digital Systems, Principals and Applications; Tocci Equipment: Circuit simulator (MultiSIM or an equivalent) Introduction: An asynchronous binary counter, referred to as a ripple counter, can be constructed in the following manner using J-K flip-flops (FF): Q 2 J K... Q J K Q J K The first FF in the chain, which represents the least significant bit (LSB), is clocked from an external source. The clock input of the remaining FFs is driven from the normal output (Q) of the previous FF in the counter chain. The J-K flip-flops are placed in the TOGGLE mode by connecting the J and K inputs to. Page 1 of 6
The MOD number of a counter is equal to the number of complete states that a counter goes through before it recycles back to its starting state. To construct a ripple counter with a MOD number X 2 N (where N = number of FFs in counter), use the following general procedure: 1. Determine the minimum number of FFs such that 2 N X. 2. Connect the output of a NAND gate to the asynchronous CLEAR inputs of all the FFs. 3. Determine the binary value of the MOD number X. For each bit that is a 1, connect the corresponding Q output of the FF to an input of the NAND gate. The operation of a ripple counter, and other sequential circuits, can be described graphically using a State Transition Diagram. Output State 1 Output State 2 Output State 3 The output state, indicated by a binary number, is shown inside the each circle (e.g. state Q 2 =1, Q 1 =0, Q 0 =1 in a 3-bit counter would be represented by 101 in one circle). The arrows connecting one circle to another indicate a transition between states and the inputs that cause the change. In the case of a ripple counter, each arrow represents the occurrence of a clock pulse. A ripple counter can also be used as a frequency divider. The output frequency of the last FF (MSB) is equal to the input clock frequency divided by the MOD #. f ( c l o c k ) f ( M S B ) = M O D # If the counter MOD number is less than the maximum MOD number (MOD # < 2 N ) then the waveform at the final FF, and possibly other FF outputs, will not have a 50% duty cycle. This is due to the counter being designed to skip states that would normally be part of the count sequence. Page 2 of 6
Procedure: 1. Using the general procedure described in the introduction, design a MOD 11 ripple counter. Show all of the steps used in the design process. Draw the schematic for the counter (use a straight edge when drawing the wires in the schematic). Page 3 of 6
2. Draw the State Transition diagram for the MOD 11 counter. (look back on page 2) 3. Construct the counter circuit in MultiSIM or an equivalent circuit simulator. Use a negative-edge triggered J-K FF with active-low asynchronous inputs (74LS107). Use a toggle switch for the clock input for the first FF in the counter. Tie the asynchronous CLR inputs to. Use TTL symbols for the J-K flip-flops. PRINT OUT A COPY OF THE CAPTURED SCHEMATIC AND ATTACH TO THE LAB. Page 4 of 6
4. Evaluate the circuit and record the results in the following table: Clock Q3 (MSB) Q2 Q1 Q0 (LSB) 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 5. Calculate the frequency (f) and period (T) of the final FF output (Q3) based upon a 10kHz clock signal. 6. Disconnect the toggle switch from the clock input. Connect a function generator to the clock input. To get a 0 5 V square wave, select a 50% duty cycle, 10 khz square wave with an amplitude of 2.5V and an offset of 2.5V. (Connect the + output to the clock input and the common input to ground. The output should not be connected). Use an oscilloscope to measure the period of the Q3 output waveform. Connect the output of the function generator (clock input) to Channel A and the Q3 output to Channel B. Tie the ground input to Ground. Set the time base to 0.5ms/div. Select DC and 5V/div for each channel. Set the Y-position to 1.00 for Channel A and -1.00 for Channel B. Turn on the simulator. After the waveforms have filled a screen, turn the simulator off and measure the period of the Q3 signal (use the screen cursor markers to make the measurement). PRINT THE XY-PLOT (Scope Screen) AND ATTACH TO THE LAB. To print the scope screen, activate Word with a blank sheet. In multisim, click on the blue oscilloscope display border and push Alt- Print Screen (at the left top of the keyboard. Then go into word and do a Cntl-V on the blank sheet. Save the sheet on a floppy and take it to a computer with an attached printer. Record the clock period and calculate the Q3 frequency. T Q3 = f Q3 = Page 5 of 6
Review Questions: Answer the following questions after the lab is completed. 1. If something happened that caused all of the FF outputs in the MOD 11 counter to be set to a logic 1, what would happen to the counter? 2. What is the maximum MOD # of a counter constructed with 6 flip-flops? 3. A 90 MHz clock signal is applied to a ripple counter. The output frequency of the final flip-flop is 4.5 MHz. How many flip-flops are used in this counter circuit? Ripple 90 MHz Counter 4.5 MHz 4. The clock period of a ripple counter must be longer than the total propagation delays through all of the flip-flops. For proper operation, the period / frequency should be: T m i n = N t p d t p d = p r o p a g a t i o n d e l a y 1 f m a x = N t p d If the propagation delay is 15ns for a J-K FF, what is the largest MOD counter that can be constructed to ensure the counter will operate for frequencies > 12 MHz? Page 6 of 6