EE 367 Lab Part 1: Sequential Logic

EE367: Introduction to Microprocessors Section 1.0 EE 367 Lab Part 1: Sequential Logic Contents 1 Preface 1 1.1 Things you need to do before arriving in the Laboratory............... 2 1.2 Summary of material covered in Part 1........................ 2 1.3 Pre-lab questions, part 1 (due at the beginning of the second lab session)...... 2 2 Tutorial: The flip-flop, work-horse of a microprocessor 3 2.1 Operation of the Rising Edge Triggered Flip-Flop................. 4 2.2 Timing iagram................................... 4 3 Tutorial: Latch-Logic-Latch Circuits 6 3.1 Latch-Logic-Latch Operation:............................ 9 3.2 Latch-Logic-Latch and a microprocessor instruction................. 11 4 Construction: Flip-Flop Circuit 11 4.1 Construction practices and quality.......................... 11 4.2 Assembly Your Bread Board............................. 12 4.3 Connect the Power Supply.............................. 12 4.4 Install Components.................................. 15 4.4.1 Pin numbering and connections for an integrated circuit.......... 15 4.5 Wire the circuit of figure 9.............................. 15 4.5.1 Wiring.................................... 15 4.6 Attach LEs for monitoring............................. 16 4.6.1 Arranging LEs for monitoring....................... 16 4.6.2 Set and Clear the flip flop.......................... 16 4.7 Probing with the multimeter and logic probe..................... 16 5 Test and emonstrate 17 6 Post-Lab uestions, Part 1 (due 1 week after you complete the evaluation sheet for Lab Part 1) 17 1 Preface In this laboratory exercise you will build and test a simple Flip-Flop circuit using the 74LS74 logic chip. You will examine the function of clock signals, synchronous and asynchronous inputs, and other aspects of clocked logic. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-1

EE367: Introduction to Microprocessors Section 2.0 The circuits you build this week are temporary, at the end of Part 1 you will remove all of the components. Starting with Part 2, the circuits you build will be part of the Really Small Processor (the RSP), which you will be developing and programming throughout the semester. 1.1 Things you need to do before arriving in the Laboratory Acquire the EE 367 Laboratory Manual (this document), EE 367 Reference Materials and EE 367 parts kit. Read this Handout Answer the Pre-lab questions, section 1.3. Answers to the Pre-lab questions are due at the beginning of your second lab section. Review the EE 367 Laboratory Reference Materials. Materials is required at several points in Lab Part 1. Information from the Reference Read and consider the questions at the end of this handout. 1.2 Summary of material covered in Part 1 Tutorial: The Flip-Flop, Work-Horse of a Micro-Processor Tutorial: Latch-Logic-Latch Circuits Construction: Flip-Flop Circuit 1.3 Pre-lab questions, part 1 (due at the beginning of the second lab session) First read the tutorial sections, sections 2 and 3. 1. (3 Points) raw a timing diagram similar to the practical case of figure 5, below, for the case where signal A 0 makes its transition first. Note: For each timing diagram that you draw, be sure that subsequent events appear to the right of causative events, and show causality arrows. 2. (3 Points) True or False: A logic circuit can be designed so that two or more signals will consistently arrive at the inputs of a logic gate at exactly the same time. 3. (4 Points) Consider the example latch-logic-latch cycle with the transition A 0 = 0, B 0 = 0 A 0 = 1, B 0 = 1, (a) What are the correct beginning and ending outputs? Make a table like table 2, below, for this transition. (b) etermine a transient signal that might arise with this transition. raw a timing diagram similar to figure 5 showing the inputs and outputs with possible transient signals. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-2

EE367: Introduction to Microprocessors Section 2.0 2 Tutorial: The flip-flop, work-horse of a microprocessor igital systems, such as computers, store and manipulate data. ata manipulations, such as adding two numbers, are the work of combinatoric logic such as AN or OR gates. Storing data is the work of sequential logic, which is to say flip-flops. The flip-flop is the most commonly used flipflop. It is the work-horse of microprocessors and many other electronic systems. The schematic symbol of a flip-flop is illustrated in figure 1. Set ata Set Output Clock Inverted Output Clear Clear -- 4 Inputs -- -- 2 Outputs -- ---- Flip-Flip ---- Figure 1: The 74LS74 rising edge triggered flip-flop has 4 inputs and 2 outputs. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-3

EE367: Introduction to Microprocessors Section 2.2 2.1 Operation of the Rising Edge Triggered Flip-Flop Flip-flops have synchronous and asynchronous inputs. Synchronous Inputs: Clock and -input. The timing of output actions corresponding to these inputs is controlled by and synchronized with the clock input. As the name suggests, data is transferred from the input to the output at the instant of the rising edge of the clock signal. Asynchronous Inputs: Set and Clear. Output actions corresponding to asynchronous inputs occur immediately, no matter what the clock. Typically, set, clear or reset inputs will act asynchronously. Active Low Signals: The signal may be called set-bar or clear-bar, indicating that the input causes the named action when the signal is low. The signal is said to be exerted or activated when it causes its output. Thus the signal Set is exerted when 0 volts are applied to the Set pin. Signals of this type are called Active Low or Negative Logic signals. While active low signals can be a bit confusing at first, in fact the majority of control signals (such as Set and Clear) are active low. This is because transistor-transistor-logic (TTL) is engineered to take essentially zero power to exert a high, whereas some power is required to exert a low. Since signals like Set and Clear are more often released than exerted, power is saved by making them active low. The truth table of the 74LS74 rising edge triggered flip-flop is seen in table 1. As seen in the table, the asynchronous inputs Set and Clear dominate: when these signals are exerted the output is set or cleared. Signals and Clock are marked X, or don t care because it doesn t matter what the or clock inputs are if either set or clear is exerted. It is also seen that exerting Set and Clear simultaneously is not allowed, doing so will give unpredictable results. The set and clear signals are used, for example, to initialize each flip-flop when a microprocessor is reset. Otherwise, neither Set nor Clear is exerted and the and Clock inputs take over. On the rising edge of the clock signal, the -input value is stored in the flip-flop and exerted at the output. If the clock is high, low or a falling edge, the internal state and output do not change. Background 2.2 Timing iagram Because flip-flops store data, time and what is stored at each instant in time are essential to understanding and engineering their operation. This is why the operation of sequential logic is often illustrated with a timing diagram, such as figure 2. In the timing diagram, causality is shown by a link made with a curved arrow. The input(s) at the tail of the arrow cause the output(s) at the head of the arrow. Events in the timing diagram of figure 2 are marked A... M, and are described below. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-4

EE367: Introduction to Microprocessors Section 2.2 Item Action Input Signals Outputs Set Clear Clock 1 Set 0 1 X X 1 0 2 Clear 1 0 X X 0 1 3 Not Allowed 0 0 X X - - 4 Clock (=0) 1 1 0 0 1 5 Clock (=1) 1 1 1 1 0 6 Otherwise 1 1 X 1, 0, 0 0 Legend: X on t care - Output indeterminate 0, 0 Previous (stored) values Rising edge Falling edge Table 1: Truth table of the 74LS74 rising-edge triggered flip-flop. B C E F G H J K L M Clock Set CL A Time Figure 2: Example timing diagram. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-5

EE367: Introduction to Microprocessors Section 3.0 A. The output is indicated to be either a 1 or a 0; depending on unknown prior signals. B. The Set signal goes low, setting the output to 1 (high, or +5 volts); goes to 0 (low, or 0 volts). C. The data signal changes, but the output does not change, because only determines the output on a rising clock edge.. is high on the rising edge of the clock, and so remains high. E. is low on the rising edge of the clock, and so goes low. goes high. F. The input changes from low to high to low, but there is no rising edge of the clock during this interval, and so the input has no effect on the output. G. is high on the rising edge of the clock, and so goes high. goes low. H. Again, there is no rising clock edge, so the input does not influence the output. J. The Clear signal is exerted, so goes low. Notice that the tail of the arrow marks the level, not the edge. It is only the clock input which exerts its influence with an edge. K. The clock has a rising edge; but the Clear signal is exerted, so the clock and signals have no influence. L. Clear has been released, at L Set is exerted, and so goes high. goes low. M. Set has been released, and so the and clock inputs control the output. 3 Tutorial: Latch-Logic-Latch Circuits To understand why the flip-flop is the workhorse of many systems, one must understand why the latch-logic-latch configuration is so often used. To understand why the latch-logic-latch is used, one must understand the transient signals that combinatoric logic can generate. First, three definitions: A Latch: (noun) one or several flip-flops which can store data. ata at the inputs are read at specific instants in time, and stored until cleared or replaced with new data. See the 74LS273 or 75LS374 data sheets, in the Reference Materials. Some authors make a distinction between a latch and a flip-flop based on whether the device is level or edge triggered. We do not make this distinction. A latch is any device which may latch data (see to latch below). An example 8-bit latch is seen in figure 3. It consists of 8 flip-flops in parallel. The flipflops are clocked together and may be reset together. Two such latches are used in the Really Small Processor. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-6

EE367: Introduction to Microprocessors Section 3.0 ata Input Signals 0 1 2 3 4 5 6 7 Clock Input CP Master Reset MR CL CL CL CL CL CL CL CL 0 1 2 3 4 5 6 7 Latched Output Signals 8-Bit Latch with Master Reset, 74LS273 Figure 3: 8-bit latch with master reset. To Latch: (verb) to latch is to store data into a device containing one or (usually) a parallel bank of flip-flops, as in the data are latched into the F register. ata are stored at a specific instant, controlled by a clock signal. When the clock signal causes the data to be recorded, we say the data are latched ; the usage latch the data indicates to clock the flip-flop, and cause the data to be stored. Register: a collection of flip-flops which can store a word of data, for example 8, 16, 32 or 64 bits. A register is an example of a latch (noun). The distinction comes in how the data are used. We refer to a parallel bank of flip-flops as a register if the data held is processed (say by addition or subtraction or incremented). We refer to a parallel bank of flip-flops as a latch if the data simply held for later transfer to another location (no processing). One can say: clock the register to latch the data. You will work extensively with three different sets of registers this semester: Processor Registers: registers of the Programmers Model; these registers are explicitly activated by PIC18 assembly language instructions. They are the W and Status registers. I/O Registers: registers at addresses F80h to FFFh which control PIC18 input and output, including Port A (F80h), Port B (F81h) and Port C (F82h). RSP Registers: two registers you will build in Lab Part 4, Reg F and Reg G. Consider the one-bit adder circuit of figure 4. This circuit is called a one-bit (binary) adder because output signal S 0 is the sum of input bits A 0 and B 0, while output signal C 0 indicates whether there should be a carry. In a processor, signals A 0 and B 0 are the 0 th bits of adder input words A and B; signals S 0 and C 0 are the 0 th bits of the sum and carry outputs, respectively. An 8-bit adder will have bits 0 7. Table 2 indicates a transition of the inputs and outputs of the adder circuit. In state n, the input is A 0 = 1, B 0 = 0 and the output sum is 1, and the carry is 0. State n+1 is as shown. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-7

EE367: Introduction to Microprocessors Section 3.0 B 0 A 0 S 0 A 0 B 0 S 0 C 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 C 0 Figure 4: One-bit adder; operands: A 0, B 0 ; sum output: S 0 ; carry output: C 0 A 0 B 0 S 0 C 0 State n 1 0 1 0 State n+1 0 1 1 0 Table 2: Signals corresponding to a 1-bit adder and an input transition. A 0 A 0 B 0 B 0 S 0 S 0 C 0 Ideal C 0 Practical Figure 5: Practical combinatoric logic circuits have propagation delay and produce transient pulses. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-8

EE367: Introduction to Microprocessors Section 3.1 Ideally, the input signals change instantly to their new values, and the output signals change instantly to the new result. For the ideal timing shown in figure 5, the transitions occur instantaneously and together. But practically, the transitions occur with some slope and may be shifted in time. As the diagram shows, shifted signals can result in brief pulses, called transient or glitch signals, in the output. These transients carry no useful information and may cause incorrect signals in subsequent logic circuits. Time shifts of the input signals, such as seen on the practical side in figure 5, can arise for many reasons: because the signals come from different sources, or one gate may react more rapidly than another, or one connection may have more capacitance or less resistance, or because wire lengths might be different. Practically speaking, no two pulses ever arrive perfectly simultaneously. Combinatoric logic always produces glitch pulses. The latch-logic-latch cycle is used to ensure that the outputs of the logic circuit are read only after all 3.1 Latch-Logic-Latch Operation: A latch-logic-latch configuration for the one-bit adder is shown in figure 6 with timing diagram in figure 7. The latches on the input and output of the logic circuit control when signals A 1 0, B1 0, S 0 and C 0 can change. The inputs to the logic, signals A 1 0 and B1 0, can change only on the rising edge of data clock signal k d ; while the (latched) output signals, S 0 and C 0, can change only on the rising edge of results clock signal k r. A 0 B 0 C 1 C 0 0 k d ata Latch Clock A ata Latch B ata Latch A 1 0 B 1 0 k r S 1 0 Result Latch Clock Result Latch Result Latch Figure 6: One-bit adder; operands latched, result latched. S 0 EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-9

EE367: Introduction to Microprocessors Section 3.1 A B C E F G Asynch. Inputs A 0 B 0 k d Latched Inputs A 1 0 B 1 0 Asynch. Result S 1 0 C 1 0 * * k r Latched Result S 0 C 0 Latch Logic Latch Input ata Latches Clocked ^ ^ Result Latches Clocked * Transient Signals Figure 7: Timing diagram for the one-bit adder; operands latched, result latched. Signal k d clocks the data latches; signal k r clocks the result latches. Several important moments in the timing diagram are annotated in figure 7: A. At A, some time before the clock signal K d, it does not matter what inputs A 0 and B 0 are. B. At B, data signals A 0 and B 0 stabilize to the values to be processed during the current clock cycle. Signals A 0 and B 0 must hold steady values during the setup time of the flip-flops. C. At C, the input data is clocked into the Input ata Latches by clock signal k d.. After the propagation delay of the latches, data signals A 1 0 and B1 0 are presented to the logic circuit. No two logic signals are ever perfectly simultaneous, and so the combinatoric logic may produce transient pulses in signals S0 1 and C1 0. E. After an interval sufficient for all propagation delays, all transient signals have died out and logic output signals S0 1 and C1 0 become steady and hold their final values. These values must persist on the Result Latch inputs for the flip-flop setup time. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-10

EE367: Introduction to Microprocessors Section 4.3 F. Result Latch Clock Signal k r clocks the result latch so that the logic output signals S0 1 and C0 1 are latched into the Result Latches. G. After a propagation delay, the outputs of the Result Latch, signals S 0 and C 0 are guaranteed to be valid. The sequence of steps A-G may seem complex at first. It is detailed, but the essential actions are: Latch: Logic: Latch: latch the input data, after all propagation delays steady data will be presented to the logic circuit. do the needed logical operation on the latched input data. After sufficient time all glitch pulses have passed. latch the result, so that a steady result can be presented to the next logic stage. While the sequence may seem complex, designing clocked logic is actually very straight forward, because signals march through the circuit in a well controlled way. 3.2 Latch-Logic-Latch and a microprocessor instruction Microprocessors execute assembly language instructions, which are the low-level commands which the silicon itself can execute. Most assembly language instructions are executed with one or several latch-logic-latch cycles. The data to be processed is latched into registers and held at steady values; combinatoric logic processes the data (such as logic for add with carry); and - after a suitable propagation delay - the result is latched into a register. The clock rate of the processor is the reciprocal of the time between k d and k r in figure 7. For example, the 16.0 mega-hertz processor clock of the PIC18 microprocessor allows 31.25 nanoseconds between the data latch clock pulse and the results latch clock pulse. 4 Construction: Flip-Flop Circuit 4.1 Construction practices and quality Read the section: Guidelines for Breadboard Construction in the EE 367 Laboratory Introduction. Your work will be evaluated in part on the criteria specified there. uality construction, furthermore, will reduce your debugging challenges. Pay particular attention to the wiring color code. Correct color coding will aid in debugging later, and is required. Read the section: ebugging Strategies in the EE 367 Laboratory Introduction. It provides some insight that relates to construction quality and debugging. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-11

EE367: Introduction to Microprocessors Section 4.3 4.2 Assembly Your Bread Board Bananna plugs must be attached correctly, so that only plastic touches the metal. 4.3 Connect the Power Supply See the bread board layout diagram, figure 8. (1) Assemble your breadboard. Put the green terminal in the V ground position, and red terminal in the V cc position. Also install the other 2 terminals. (a) Connect ground to PSS-2B. (b) Connect V cc to PSS-2R. Note: Accidentally reversing the power supply connection can destroy every chip in the circuit. Always wire +5V connections with Red, ground connections with Green, and always connect the power supply correctly. (c) If the +5 volt supply of your power supply is adjustable, use the multimeter to set the power supply voltage to +5 volts. Measure from a test point on PSS-2R to ground on PSS-2B. Note: It is handy to know if power is on or off. Connect a red LE across the terminals of the PSS-2 bus. The LE leads also provide a place to touch the multimeter leads. (2) The 2-wide bread-board strips are power distribution strips. Connect each of the red strips to +5V and each of the blue strips to Ground. Note: Always use the most direct routes and square corners for your wiring. See the construction guidelines in the Laboratory Introduction. In this case, the shortest route is to connect each power distribution strip to the PSS-2 bus. (3) Before installing any components, check the power supply voltages on all of the power distribution strips. Whenever any electronic device does something it shouldn t, a good thing to check first is the power supply voltage. Trouble Shooting Tip EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-12

EE367: Introduction to Microprocessors Section 4.3 a b c d e f g h i j 1 16 5 SW st J 3 IP Switch 5 (Grn) (Grn) (Red) (Yel) SW cl SW 10 SW ck 15 LE st LE cl 20 LE LE ck 25 ** 1 14 J 1 10 15 20 25 (Red) (Red) 30 LE LE 35 7 LS04 8 1 14 J 2 30 35 40 LS74 40 7 8 45 45 50 50 55 55 60 60 B R 63 63 B R B 2 ** Momentary contact (pushbutton) switch Figure 8: Bread board layout for Sequential Logic experiment (etail). EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-13

EE367: Introduction to Microprocessors Section 4.3 Green * +5V J 1,1 LE st +5v 1 2 SW st SW ** SW ck * * +5V +5V 11 +5V * J 1,6 13 12 J 1,5 10 J 1,2 Red LE Yellow LE ck +5v 2 +5v 3 Green LE cl +5v 4 Set Clear 1 J 2,1 Output 5 Inverted Output 6 J 1,3 5 6 J 1,4 9 8 Red LE LE Red +5v +5v 3 4 SW cl * 2K - 20K Ω ** Momentary Contact Switch Note: Current limiting resistor built into EE-367 specified LE. Legend: 1 pin number. Figure 9: Sequential logic schematic. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-14

EE367: Introduction to Microprocessors Section 4.5.1 4.4 Install Components Install Integrated Circuits (ICs) J 1, J 2 and J 3 as seen in figure 8. Follow the layout shown in figure 8 exactly. 4.4.1 Pin numbering and connections for an integrated circuit To function correctly, the connections to an integrated circuit must be made to the correct pins. A top view of 14, 16 and 20 pin IC s is seen in figure 10. Note: pin numbering 14-pin IC 16-pin IC 20-pin IC (with notch) (with dimple) (with notch) 1 2 3 4 5 6 7 GN V cc V cc 14 13 12 11 10 9 8 1 2 3 4 5 6 7 16 15 14 13 12 11 10 8 GN 9 1 2 3 4 5 6 7 8 9 10 GN V cc 20 19 18 17 16 15 14 13 12 11 Figure 10: IC pin numbering. Top view of standard IC s. The pins are numbered counter-clockwise, with a mark (most often a notch or dimple on the chip) indicating the position of pin 1. Two pins are for the power connections to ground and V cc ; these are typically in the lower- Power left and upper-right corners. V cc is +5 volts for LS series chips. (V cc can range from 1.8 Supply to 15 volts for other types of chips.) Connections The power supply must be connected, or the chip won t work. The chip uses active transistors to drive the output; and these require power. 4.5 Wire the circuit of figure 9 4.5.1 Wiring (1) Note that signal pin numbers are given in figure 9. By convention, the power supply pins on t are not indicated; but, of course, the V cc (+5V) and GN connections must also be wired to each chip. forget V cc and GN Power supply wiring doesn t change, whereas other wiring undergoes changes or corrections. If the power supply wires are installed first, they will be below and out of the way of on each chip. other wiring. Construction EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-15 Tip

EE367: Introduction to Microprocessors Section 5.0 (2) Figure 9 shows four signals generated by switches. The assignment of signals to switches is seen in the layout diagram, figure 8. (a) Signals Set, Clear and are generated by switches 6, 7 and 8 of the 8-position IP switch. A schematic of the IP switch is provided in the Laboratory Introduction. (b) The clock signal is generated by momentary contact, or push-button switch. Note: Pin numbers are given for the circuit of lab part 1. For subsequent circuits, students will determine the pin numbers. 4.6 Attach LEs for monitoring 4.6.1 Arranging LEs for monitoring Your kit includes Red, Green and Yellow LEs. These LEs have internal current limiting resistors, and may be connected directly to the outputs of the TTL ICs. A driver IC (J 1 in figures 8 and 9) is used to drive the LEs. Note that the driver is an inverter and the LE anode is wired to +5 volts. When the signal, for example Set at J 1 pin 1, is high, the output of the driver goes low, and the LE illuminates. TTL devices can generally sink much more current than they can source using the inverter as a driver takes advantage of this characteristic. Background 4.6.2 Set and Clear the flip flop Using the IP switches, generate set and clear signals to set and clear the flip-flop. Monitor the flip-flop output with the LEs. 4.7 Probing with the multimeter and logic probe Later we will work with more complex circuits and will not have LEs on every signal line, and so the multimeter and logic probe will be valuable tools. (1) Using the multimeter measure these voltages (see question 1, below): (a) The power supply voltage. (b) Set the flip flop and measure the voltage of the output when the output is high (a logic one, but probably less than 5 volts). (c) Clear the flip flop and measure the voltage of the output when the output is low (a logic zero, but probably more than 0 volts). (2) Using the logic probe, observe the clock signal generated with the momentary contact switch. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-16

EE367: Introduction to Microprocessors Section 6.0 5 Test and emonstrate (1) Test and demonstrate the operation of your circuit by exercising each of the ways to activate the output: (a) With a clear signal; (b) With a Set signal; (c) With a rising clock edge and = 0; (d) With a rising clock edge and = 1. (2) Using the input switches, generate the input signals of the timing diagram of figure 2. (3) Make up and test an input sequence (see question 2, below). (a) Make up a sequence of input signals different from that shown in figure 2, and which demonstrates actions (1a)-(1d), above. (b) raw a timing diagram showing the input signals (the top 4 signals of figure 2) for your input sequence; and complete the diagram with the corresponding output signals, based on you knowledge of the operation of the rising edge triggered flip-flop. (c) Apply your input signals, record the observed flip-flop response in two additional lines in the timing diagram. 6 Post-Lab uestions, Part 1 (due 1 week after you complete the evaluation sheet for Lab Part 1) Some of the questions below are meant to be challenging problems requiring thought about logic circuits and why systems are designed as they are. Feel free to ask for assistance from the TA s or Instructor as you work through the questions below. Note that the student s process of formulating and asking a question is itself a part of the learning process. (1) (6 points) What are your voltage measurements made in section 4.7? Are the voltages you measured on the output valid low and high voltages? (2) (8 points) Include the timing diagram you drew in section 5 item 3, above. id operation of the circuit verify the timing diagram you drew? If not, why not? Is the flip-flop triggered when you depress switch SW ck or release it? Why? EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-17

EE367: Introduction to Microprocessors Section 6.0 (3) (6 points) A 1-bit adder is shown in figure 4. (a) What are the names of the 2 gates? (b) Write the truth table for the circuit. (4) (Extra Credit) Section 3.2 discusses the need and importance of clocked logic for a micro-processor. However, clocked logic is not without its costs. Consider the issue, and write a paragraph discussing what costs clocked logic might incur and indicating how you might solve the problem of transient signals without a clock. Suggested reading: Computers Without Clocks, by Ivan E. Sutherland and Jo Ebergen, Scientific American, August 2002. EE-367 Lab Part 1: Sequential Logic (Revised: Jan 23, 2016) Page 1-18