Schaltwerke und Automaten

Schaltwerke und Automaten Grundlagen der technischen Informatik Wintersemester 28/9 Folien asierend auf F. Vahid und S. Werner Wintersemester 28/9

Review - Bit Storage Using an SR Latch Does the circuit to the right, with cross-coupled NOR gates, do what we want? Yes! How did someone come up with that circuit? Maye just trial and error, a it of insight... S (set) R (reset) SR latch Q S= t S= t S= t S= t Recall NOR Q Q Q Q X R= R= R= R= S R t Q Wintersemester 28/9 2

Review - Level-Sensitive D Latch SR latch requires careful design to ensure SR= never occurs D S S D latch D latch relieves designer of that urden Inserted inverter ensures R always opposite of S C R R Q D C S R D Q C Q D latch symol Q Wintersemester 28/9 3

Review - D Flip-Flop Flip-flop: Bit storage that stores on clock edge One design possiility master-servant Clk = master enaled, loads D, appears at Qm. Servant disaled. Clk = Master disaled, Qm stays same. Servant latch enaled, loads Qm, appears at Qs. Thus, value at D (and hence at Qm) when Clk changes from to gets stored into servant D latch D Dm Qm Cm master Clk D latch Ds Cs D flip-flop Clk Qs Qs Q D/Dm Q Cm Qm/Ds servant Cs Qs Wintersemester 28/9 4

Review - Basic Register Typically, we store multi-it items e.g., storing a 4-it inary numer Register: multiple flip-flops sharing clock signal From this point, we ll use registers for it storage No need to think of latches or flip-flops But now you know what s inside a register I3 I2 I I 4-it register D Q D Q D Q D Q I3 I2 I I reg(4) Q3 Q2 Q Q Q3 Q2 Q Q Wintersemester 28/9 5

Finite-State Machines (FSMs) and Controllers Want sequential circuit with particular ehavior over time Example: Laser timer Pushing utton causes x= for exactly 3 clock cycles Precisely-timed laser pulse How? Let s try three flip-flops = gets stored in first D flipflop Then 2nd flip-flop on next cycle, then 3rd flip-flop on next OR the three flip-flop outputs, so x should e for three cycles Controller x laser patient D Q D Q D Q Bad jo what if utton pressed a second time during those 3 cycles? x Wintersemester 28/9 6

Need a Better Way to Design Sequential Circuits Also ad ecause of ad-hoc design process How create other sequential circuits? Need A way to capture desired sequential ehavior A way to convert such ehavior to a sequential circuit Like we had for designing cominational circuits Step : Capture ehavior Step 2: Convert to circuit Step Capture the function 2A: Create equations 2B: Implement as a gateased circuit Description Create a truth tale or equations, whichever is most natural for the given prolem, to descrie the desired ehavior of each output of the cominational logic. This sustep is only necessary if you captured the function using a truth tale instead of equations. Create an equation for each output y ORing all the minterms for that output. Simplify the equations if desired. For each output, create a circuit corresponding to the output s equation. (Sharing gates among multiple outputs is OK optionally.) Wintersemester 28/9 7

Capturing Sequential Circuit Behavior as FSM Finite-State Machine (FSM) Descries desired ehavior of sequential circuit Akin to Boolean equations for cominational ehavior List states, and transitions among states Example: Toggle x every clock cycle Two states: Lo (x=), and Hi (x=) Transition from Lo to Hi, or Hi to Lo, on rising clock edge (^) Arrow points to initial state (when circuit first starts) state Outputs: Wintersemester 28/9 x Lo Hi Lo Hi Lo Hi Lo Hi cycle cycle 2 cycle 3 cycle 4 Lo Outputs: x x= ^ x= Lo Hi ^ Hi Lo Hi 8

Definitionen Schaltnetz (cominational circuit): Verknüpfung mehrerer Eingangsvarialen ohne Rückkopplung des Ergenisses Schaltwerk (sequential circuit): Mindestens ein Ausgang ist von vorherigem Zustand der Schaltung ahängig (Rückkopplung) Speicher Beispiel: Zustandsautomat (Finite-State Machine), auch: endlicher Automat Formale Betrachtung: Ermöglicht Synthese von Schaltwerken Modell eines Verhaltens, estehend aus Zuständen, Zustandsüergängen und Aktionen Grafische Darstellung üer Zustandsgraphen Wintersemester 28/9 9

FSM Example: Three Cycles High System Want,,,,,,,,... For one clock cycle each Capture as FSM Four states:, first, second, third Transition on rising clock edge to next state Outputs: x x= ^ x= ^ x= ^ x= Off On On2 On3 ^ State Off On On2 On3 Off On On2 On3 Off Outputs : x Wintersemester 28/9

Three-Cycles High System with Button Input Four states Wait in Off while is ( *^) When is (*^), transition to On Sets x= Next two clock edges, transition to On2, then On3 x= for three cycles after utton pressed Inputs: State Inputs: x= Off Off *^ x= On ^ Outputs: x '*^ x= On2 ^ ^ x= On3 Off Off Off Off On On2 On3 Off Outputs: x Wintersemester 28/9

FSM Simplification: Rising Clock Edges Implicit Every edge ANDed with rising clock edge What if we wanted a transition without a rising edge? We don t consider such asynchronous FSMs less common, and advanced topic Only consider synchronous FSMs rising edge on every transition Inputs: ; Outputs: x x= Off *^ x= ^ On Inputs: ; Outputs: x x= Off * ^ x= On2 ^ ^ x= On3 Note: Transition with no associated condition thus transitions to next state on next clock cycle x= On x= On2 x= On3 Wintersemester 28/9 2

FSM Definition FSM consists of Set of states Ex: {Off, On, On2, On3} Set of inputs, set of outputs Ex: Inputs: {}, Outputs: {x} Initial state Ex: Off Set of transitions Each with condition Descries next states Ex: Has 5 transitions Set of actions Sets outputs in each state Ex: x=, x=, x=, and x= Inputs: ; Outputs: x x= Off x= On x= On2 x= On3 We often draw FSM graphically, known as state diagram Can also use tale (state tale), or textual languages Wintersemester 28/9 3

FSM Example: Secure Car Key Many new car keys include tiny computer chip When key turned, car s computer (under engine hood) requests identifier from key Key transmits identifier Else, computer doesn t start car FSM Wait until computer requests ID (a=) Transmit ID (in this case, ) r= Inputs: a; Outputs: r Wait a a K K2 K3 K4 r= r= r= r= Wintersemester 28/9 4

FSM Example: Secure Car Key (cont.) Nice feature of FSM Can evaluate output ehavior for different input sequence Timing diagrams show states and output values for different input waveforms r= Wait a a Inputs: a; K K2 K3 K4 r= r= r= r= Q: Determine states and r value for given input waveform: Outputs: r Inputs a State Wait Wait K K2 K3 K4 Wait Wait Inputs a State Wait Wait K K2 K3 K4 Wait K Outputs r Outputs r Wintersemester 28/9 5

Ex: Earlier Flight-Attendant Call Button Previously uilt using SR latch, then D flip-flop Capture desired it storage ehavior using FSM instead Clear and precise description of desired ehavior We ll later convert to a circuit Call utton Cancel utton Inputs: Call, Cncl Bit Storage Outputs: L Blue light Call' L= Call L= LightOff LightOn Cncl*Call' (Cncl*Call')' Wintersemester 28/9 6

How To Capture Desired Behavior as FSM List states Give meaningful names, show initial state Optionally add some transitions if they help Create transitions For each state, define all possile transitions leaving that state. Refine the FSM Execute the FSM mentally and make any needed improvements. Wintersemester 28/9 7

FSM Capture Example: Code Detector Unlock door (u=) only when uttons pressed in sequence: start, then red, lue, green, red Input from each utton: s, r, g, Also, output a indicates that some colored utton pressed Capture as FSM List states Some transitions included Start Red Green Blue Wait Wait for start utton u= s s' Start u= ar Red u= s r g a Wait for first colored utton Code detector a ag ar Blue Green u= u= u Door lock Inputs: s,r,g,,a Outputs: u Red2 u= Wintersemester 28/9 8

FSM Capture Example: Code Detector Capture as FSM List states Create transitions Start Red Green Blue s r g a Code detector u Door lock Wait Inputs: s,r,g,,a Outputs: u u= s u= ar Start a' s' ar' Red u= a Blue ag Green ar Red2 u= u= u= Wintersemester 28/9 9

FSM Capture Example: Code Detector Capture as FSM List states Create transitions Repeat for remaining states Refine FSM Mentally execute Works for normal sequence Check unusual cases What happens if all colored uttons pressed at once? Door opens! Change conditions: other uttons NOT pressed also u= s u= ar Wait Start Red u= a' s' Start Red Green Blue Wintersemester 28/9 s r g a Code detector ar' a' ag' ar' u Door lock Inputs: s,r,g,,a Outputs: u a ag ar Blue Green Red2 a' a' a' u= u= u= 2

FSM Capture Example: Code Detector Start Red Green Blue s r g a Code detector u Door lock u= s Wait Start u= ar'g' Red u= a' s' a(r'g')' a(r'g')' a(gr'')' a(r'g')' Inputs: s,r,g,,a Outputs: u ar'g' agr'' ar'g' Blue Green Red2 a' a' a' u= u= u= Wintersemester 28/9 2

Controller Design Converting FSM to sequential circuit Circuit called controller (Steuerwerk) Standard controller architecture State register stores encoding of current state Cominational logic computes outputs and next state from inputs and current state Rising clock edge takes controller to next state I FSM inputs General form Controller Cominational logic S m m-it state register m O FSM outputs N Wintersemester 28/9 22

Controller Design Process Step : Capture ehavior Step 2: Convert to circuit Step Capture the FSM 2A: Set up architecture 2B: Encode the states 2C: Fill in the truth tale 2D: Implement cominational logic Description Create an FSM that descries the desired ehavior of the controller. Use state register of appropriate width and cominational logic. The logic s inputs are the state register its and the FSM inputs; outputs are next state its and the FSM outputs. Assign unique inary numer (encoding) to each state. Usually use fewest its, assign encoding to each state y counting up in inary. Translate FSM to truth tale for cominational logic such that the logic will generate the outputs and next state signals for the given FSM. Implement the cominational logic using any method. Wintersemester 28/9 23

Controller Design: Laser Timer Example Step : Capture the FSM Already done Step 2A: Set up architecture 2-it state register (for 4 states) Input, output x Next state signals n, n Step 2B: Encode the states Any encoding with each state unique will work Inputs: ; Outputs: x x= Off FSM inputs x= x= x= On On2 On3 Cominational logic s s n n x FSM outputs a State register Wintersemester 28/9 24

Controller Design: Laser Timer Example (contd) Step 2C: Fill in truth tale Inputs: ; Outputs: x x= Off x= x= x= On On2 On3 FSM inputs Cominational logic s s n n x FSM outputs State register Wintersemester 28/9 25

Controller Design: Laser Timer Example (contd) Step 2D: Implement cominational logic FSM inputs Cominational logic s s n n x FSM outputs State register x = s + s (note that x= if s= or s=) n = s s + s s + ss + ss n = s s + ss n = s s + ss + ss n = s s + ss Wintersemester 28/9 26

Controller Design: Laser Timer Example (contd) Step 2D: Implement cominational logic (cont) FSM inputs Cominational Logic Cominational logic s s n n x FSM outputs x n State register n s s State register x = s + s n = s s + ss n = s s + ss Wintersemester 28/9 27

Understanding the Controller s Behavior x= Off x= x= x= On On2 On3 x= Off x= x= x= On On2 On3 x= Off x= x= x= On On2 On3 s s x n n s s x n n s s x n n State= State= State= Inputs: Outputs: x Wintersemester 28/9 28

Controller Example: Button Press Synchronizer cycle cycle2 cycle3 cycle4 i Button press synchronizer controller o Inputs: i Outputs: o Want simple sequential circuit that converts utton press to single cycle duration, regardless of length of time that utton was actually pressed We assumed such an ideal utton press signal in earlier example, like the utton in the laser timer controller Wintersemester 28/9 29

Controller Example: Button Press Synchronizer (contd) FSM inputs: i; FSM outputs: o i i i A B i C i i o= o= o= Step : Capture FSM FSM inputs: i; FSM outputs: o i i i i i i o= o= o= Step 2B: Encode states A B FSM inputs C unused Cominational logic Inputs Outputs s i s i Cominational logic s n n s State register o o n n FSM outputs Step 2C: Fill in truth tale Step 2A: Set up architecture n = s si + ssi n = s s i o = s si + s si = ss i Cominational logic s s State register Step 2D: Implement cominational logic o n n Wintersemester 28/9 3

Controller Example: Sequence Generator Want generate sequence,,,, (repeat) Each value for one clock cycle Common, e.g., to create pattern in 4 lights, or control magnets of a stepper motor Inputs: none; Outputs: w,x,y,z wxyz= wxyz= A B wxyz= D Step : Create FSM C wxyz= Step 2C: Fill in truth tale Cominational logic s s State register n n Step 2A: Set up architecture w = s x = ss y = s s z = s n = s xor s n = s Wintersemester 28/9 w xy z s s State register Inputs: none; Outputs: w,x,y,z wxyz= wxyz= A B wxyz= D C wxyz= Step 2B: Encode states Step 2D: Implement cominational logic n w x y z n 3

Controller Example: Secure Car Key Step Wait r= a Inputs: a; Outputs: r a K K2 K3 K4 r= r= r= r= a (from earlier example) r Step 2A Cominational logic s2 s s State register n2 n n Inputs: a; Outputs: r Step 2B r= a a r= r= r= r= We ll omit Step 2D Wintersemester 28/9 Step 2C 32

Converting a Circuit to FSM (Reverse Engineering) x What does this circuit do? s s State register Work ackwards n n y z 2D: Circuit to eqns y=s z = ss n=(s xor s)x n=(s *s )x 2C: Truth tale 2B: (Un)encode states Pick any state names you want 2A: Set up arch already done Wintersemester 28/9 : FSM (get from tale) x A D A yz= D yz= D yz= Outputs:y, z B C B yz= C yz= Inputs: x; Outputs:y, z x A B yz= x x x x C states with outputs and transitions states states with outputs yz= yz= 33

Moore vs. Mealy FSMs Moore Mealy FSM consists of state register and logic More detailed view Next state logic function of present state and FSM inputs Output logic If depends on present state only Moore FSM If depends in present state and FSM inputs Mealy FSM Wintersemester 28/9 34

Mealy FSMs may have fewer states Moore Inputs: enough (it) Outputs: d, clear (it) Mealy Inputs: enough (it) Outputs: d, clear (it) /d=, clear= Init Wait enough Init Wait d= clear= enough Disp enough enough/d= d= Inputs: enough State: I W W D I Inputs: enough State: I W W I Outputs: clear d Outputs: clear d Soda dispenser example: Initialize, wait until enough, dispense Moore: 3 states; Mealy: 2 states Wintersemester 28/9 35

Mealy vs. Moore Q: Which is Moore, and which is Mealy? A: Mealy on left, Moore on right Mealy outputs on arcs, meaning outputs are function of state AND INPUTS Moore outputs in states, meaning outputs are function of state only Inputs: ; Outputs: s, s, p Time /ss=, p= /ss=, p= Alarm /ss=, p= /ss=, p= Date /ss=, p= /ss=, p= Stpwch /ss=, p= /ss=, p= Mealy Inputs: ; Outputs: s, s, p Time ss=, p= S2 ss=, p= Alarm ss=, p= S4 ss=, p= Date ss=, p= S6 ss=, p= Stpwch ss=, p= S8 ss=, p= Moore Wintersemester 28/9 36

Mealy vs. Moore Tradeoff Mealy outputs change mid-cycle if input changes Note earlier soda dispenser example Mealy had fewer states, ut output d not for full cycle Represents a type of tradeoff Moore Inputs: enough (it) Outputs: d, clear (it) Init d= clear= Inputs: enough State: Outputs: clear d I Wait enough W W D enough I Disp d= Wintersemester 28/9 Inputs: enough (it) Outputs: d, clear (it) Init Inputs: enough State: Outputs: clear /d=, clear= d Wait I enough enough/d= W W I Mealy 37

Implementing a Mealy FSM Straightforward Convert to state tale Derive equations for each output Key difference from Moore: External outputs (d, clear) may have different value in same state, depending on input values Inputs: enough (it) Outputs: d, clear (it) / d=, clear= Init Wait enough /d= enough/d= Wintersemester 28/9 38

More on Flip-Flops and Controllers Non-ideal flip-flop ehavior Can t change flip-flop input too close to clock edge Setup time: time D must e stale efore edge Else, stale value not present at internal latch Hold time: time D must e held stale after edge Else, new value doesn t have time to loop around and stailize in internal latch D D setup time Setup time violation D C S D latch Q C D S u 2 hold time u R Q R Q 3 4 7 Leads to oscillation! Grundlagen Q der Technische 5 6 Informatik Wintersemester 28/9 39

Initial State of a Controller All our FSMs had initial state But our sequential circuits did not Can accomplish using flip-flops with reset/set inputs Shown circuit initializes flip-flops to Designer must ensure resetcontroller input is during power up of circuit By electronic circuit design Controller with reset to initial state (assuming state Off was encoded as ). reset controller Inputs: x; Outputs: x= Off x= On State register x= On2 D Q D Q R Cominational logic Q s s S Q n n x= x On3 Wintersemester 28/9 4

Glitching Glitch: Temporary values on outputs that appear soon after input changes, efore stale new output values Designer must determine whether glitching outputs may pose a prolem If so, may consider adding flip-flops to outputs Delays output y one clock cycle, ut may e OK Called registered output Cominational logic s s State register x n n D flip-flop xr Laser timer controller with flip-flop to prevent glitches on x from unintentionally turning on laser Wintersemester 28/9 4

Was haen Sie heute gelernt? Zustandsautomat (FSM) Bildungsvorschrift zur Erstellung eines Models, welches das sequentielle Verhalten des Zustandsautomaten aildet Technik zur Üerführung des Models eines Zustandsautomaten in eine digitale Schaltung Wintersemester 28/9 42