DIGITAL SYSTEM DESIGN

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Transcription:

DIGITAL SYSTEM DESIGN

Buildig Block Circuit Rather tha buildig ytem at the gate level, ofte digital ytem are cotructed from higher level, but till baic, buildig block circuit. Multiplexer, decoder, flip-flop, regiter, ad couter are example of buildig block, which are ubcircuit from which complex circuit ca be cotructed. For may larger ytem, the circuitry required ca ofte be divided ito two Sub-ytem: the datapath circuit; ad the cotrol circuit. The datapath circuit i ued to tore ad maipulate data ad to trafer data from oe part of the ytem to aother. Datapath circuit ca comprie of buildig block uch a regiter, hift regiter, couter, multiplexer, decoder, etc.

Buildig Block Circuit The cotrol circuit, uually a FSM, cotrol the operatio of the datapath circuit. I may applicatio, it i ueful to be able to prevet the data tored i a flip-flop from chagig whe a active clock edge occur. A imple example of the diviio of the data path ad the cotrol path ca be illutrated uig a flip-flop with a eable iput. The data path coit of the flip-flop ad it iput, ad the cotrol path coit of the eable iput. The two path exit idepedetly of each other with the eable (cotrol path) cotrollig the flow of the data ito the flip-flop. It i alo ueful to be able to ihibit the hiftig operatio i a hift regiter by uig a eable iput.

Algorithmic State Machie (ASM) chart State diagram are ot coveiet to decribe the behavior of large tate machie ASM chart are ued to decribe large machie It i a type of flow chart Repreet tate traitio Repreet geerated output for a ASM ASM chart have three type of elemet State box Deciio box Coditioal output box

Elemet ued i ASM chart State ame Output igal or actio (Moore type) (Fale) Coditio (True) expreio ()S (a) State box (b) Deciio box Coditioal output or actio (Mealy type)

ASM chart for a imple FSM Reet A B w C w z w

State Diagram ad it correpodig ASM chart Reet Reet w = z = A w = z = A B w = z = w = z =!" B #"!"

Deig Example: A Bit-Coutig Circuit Uig the cocept of the ASM ad the eparate data ad cotrol circuit we ca implemet fairly complex ytem. Suppoe we wih to cout the umber of bit i a regiter that have the value. Aume that the value A i tored i a regiter that ca hift it cotet i the left to-right directio. Peudo-code for the bit couter. B=; while A do if a = the B=B+; Ed if; Right-hift A ; Ed while;

ASM chart for the peudo-code. : iput igal that idicate if A ha bee loaded We ca aume that the ame clock igal cotrol the chage i the tate of the machie ad chage i A ad B. Therefore i tate S2, the deciio box which tet whether A=, occur imultaeouly with the box that check the value of a. If A=, the the FSM will chage to tate S3 o the ext clock edge (thi alo hift A, which ha o effect becaue A i already ). O the other had, if A=, the the FSM doe ot chage to S3 but remai i S2. At the ame time A i hifted, ad B i icremeted if a ha the value. Load A B B + S S2 Reet B Shift right A A =? a S3 Doe

A Bit-Coutig Circuit (data-path) For the data-path circuit a hift regiter which hift left to- right i required to implemet A. It mut have the parallel load capability ad a eable iput ice hiftig hould occur oly i tate S2. I additio, a couter i eeded for B, ad it eed a parallel-load capability to iitialize the cout to i tate S. LA EA Clock w L E Data Shift A LB EB L E log 2 Couter log 2 z a B

ASM chart for the bit couter cotrol circuit Data log 2 Reet w LA L EA E Clock Shift A LB EB L E Couter log 2 S LB z a B S2 EA S3 Doe EB z : A i ready z: = whe A = (filled it) a

ASM chart for the bit couter cotrol circuit Data log 2 Reet w LA L EA E Clock Shift A LB EB L E Couter log 2 EA,LA S EB,LB z a B S2 S3 EA Doe EB z a

Shift-Ad-Add Multiplier Decimal 3 3 3 43 Biary A: Multiplicad B: Multiplier P = Product Maual method A algorithm for multiplicatio. P = ; for i = to do if b i = the P = P + A ; ed if; Left-hift A ; ed for;

ASM chart for the multiplier Reet S Load A Load B P P = ; for i = to do if b i = the P = P + A ; ed if; Left-hift A ; ed for; S2 Shift left A, Shift right B S3 Doe P P + A B =? b ASM chart for the multiplier.

Datapath circuit for the multiplier. LA DataA LB DataB EA L E Shift-left regiter EB L E Shift-right regiter Clock A 2 B + Sum 2 Pel DataP 2 2 z b EP E Regiter 2 P

ASM chart for the multiplier cotrol circuit. Reet S Pel = EP S2 S3 Pel = EA EB Doe EP z b

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