equentielle chaltelemente Grundlagen der technischen Informatik Folien basierend auf F. Vahid und. Werner
Review - Ranges for logical values Low: signal must be smaller than the upper border of the Low range High: signal must be higher than the lower border of the High range these two areas are separated by a third area (thus U L,max U H,min ) so that a corrupted logical signal might be recognized U H,max U H,min Range for logical Logic values undefined U L,max U L,min Range for logical 2
Review - How to calculate t R and t F? U out 9% % t R t F t To calculate t R and t F measure the actual times for the signal having % and 9% of the actual voltage. t R =t(u=.9 U max ) t (U=. U max ) t F =t(u=. U max ) t (U=.9 U max ) Keep in mind: not neccessarily t F = t R 3
Review - Dynamic power consumption Voltage (Volt, V) Current (Ampere, A) Energy Water pressure (bar) Water quantity per second (liter/s) Amount of Water C L 4
Introduction equential circuit Output depends not just on present inputs (as in combinational circuit), but on past sequence of inputs tores bits, also known as having state imple example: a circuit that counts up in binary Today, we will: Design a new building block, a flip-flop, to store one bit Combine flip-flops to build multi-bit storage register a b a b Combinational digital circuit equential digital circuit Must know sequence of past inputs to know output F? F 5
toring One Bit Flip-Flops Example Requiring Bit torage Flight attendant call Press call: light turns on tays on after released Press cancel: light turns off tays off after released Logic gate circuit to implement this? Cancel Doesn t work. = when =, but doesn t stay when returns to Need some form of feedback in the circuit Cancel Bit torage Blue light. pressed light turns on Cancel Bit torage Blue light 2. released light stays on Cancel Bit torage Blue light 3. Cancel pressed light turns off 6
First attempt at Bit torage Need some sort of feedback Does circuit on the right do what we want? No: Once becomes (when =), stays forever no value of can bring back to t t t t t t t 7
Bit torage Using an R Latch Does the circuit to the right, with cross-coupled NOR gates, do what we want? Yes! How did someone come up with that circuit? Maybe just trial and error, a bit of insight... (set) R (reset) R latch = / = / = / = / Recall NOR X R= R= R= R= R / 8
Truth table of a R Latch R n n+ Functionality Both inputs are, => the state stores n The reset input is, => the FF is set to. The set input is, => the FF is set to X The FF s behaviour can not be X predicted (set) R (reset) R latch Characteristic Equation: nn+ = + RR nn 9
Example Using R Latch for Bit torage R latch can serve as bit storage in previous example of flight-attendant call =: sets to stays even after = Cancel=: resets to Cancel Bit torage Blue light Blue light But, there s a problem... Cancel R
Problem with R Latch Problem If = and R= simultaneously, we don t know what value will take = R= t = R= t = R= t R t may oscillate. Then, because one path will be slightly longer than the other, will eventually settle to or but we don t know which. Known as a race condition. t
Problem with R Latch Designer might try to avoid problem using external circuit Circuit should prevent R from ever being But can occur due to different path delays External circuit R latch Cancel Cncl Assume ns delay per gate. The longer path from to R than from to causes R= for short time could be long enough to cause oscillation R Cncl R 2 ns R = 2
Problem with R Latch Glitch can also cause undesired set or reset External circuit R latch Cncl Cancel Cncl uppose this wire has 4 ns delay R R 4 ns R = (undesired glitch) 3
olution: Level-ensitive R Latch Add enable input C and R only allowed to change when C= Ensure circuit in front of R never sets R= (e.g., see next slide), except briefly due to path delays et C= after time for and R to be stable When C becomes, the stable and R value passes through the two AND gates to the R latch s R inputs. C R Level-sensitive R latch C R R Level-sensitive R latch symbol 4
olution: Level-ensitive R Latch Cncl Clk C R Level-sensitive R latch R Cncl R C Glitch on R (or ) doesn t affect R (or ) R Correct values when enabled 5
Level-ensitive D Latch R latch requires careful design to ensure R= never occurs D D latch D latch relieves designer of that burden Inserted inverter ensures R always opposite of C R R D C R D C D latch symbol 6
Problem with Level-ensitive D Latch D latch still has problem (as does R latch) When C=, through how many latches will a signal travel? Depends on how long C= Clk_A signal may travel through multiple latches Clk_B signal may travel through fewer latches Y??? D D2 2 D3 3 D4 4 C C2 C3 C4 Clk Clk_A Clk_B 7
D Flip-Flop Flip-flop: Bit storage that stores on clock edge One design possibility master-servant Clk = master enabled, loads D, appears at m. ervant disabled. Clk = Master disabled, m stays same. ervant latch enabled, loads m, appears at s. Thus, value at D (and hence at m) when Clk changes from to gets stored into servant D latch D Dm m Cm master Clk D latch Ds Cs D flip-flop Clk s s D/Dm Cm m/ds servant Cs s Note: Hundreds of different flipflop designs 8 exist
D Flip-Flop olves problem of not knowing through how many latches a signal travels when C= In figure below, signal travels through exactly one flip-flop for Clk_A or Clk_B Why? Because on rising edge of Clk, all four flip-flops are loaded simultaneously then all four no longer pay attention to their input, until the next rising edge. Doesn t matter how long Clk is. Y D D2 2 D3 3 D4 4 Two latches inside each flip-flop Clk Clk_A Clk_B 9
D Flip-Flop D The triangle means edgetriggered clock input ymbol for rising-edge triggered D flip-flop rising edges Clk D ymbol for falling-edge triggered D flip-flop Clk falling edges Internal design: Just invert servant clock rather than master 2
D Latch vs. D Flip-Flop Latch is level-sensitive tores D when C= Flip-flop is edge triggered tores D when C changes from to aying level-sensitive latch or edge-triggered flip-flop is redundant Comparing behavior of latch and flip-flop: Clk 2 D (D latch) 3 (D flip-flop) 9 4 7 5 6 8 Latch follows D while Clk is Flip-flop only loads D during Clk rising edge 2
Clock ignal Flip-flop Clk inputs typically connect to one clock signal Coming from an oscillator component Generates periodic pulsing signal Below: "Period" = 2 ns, "Frequency" = /2 ns = 5 MHz "Cycle" is duration of period (2 ns); below shows 3.5 cycles Osc. Clk Clk Time: ns ns 2 ns 3 ns 4 ns 5 ns 6 ns Period/Freq shortcut: Remember ns GHz Freq. GHz GHz GHz MHz MHz Period. ns. ns ns ns ns 22
Flight-Attendant Button Using D Flip-Flop D flip-flop will store bit Inputs are, Cancel, and present value of D flip-flop, Truth table shown below Cancel Cncl Comb. Circuit D Clk D L Blue light Preserve value: if =, make D=; if =, make D= Cancel -- make D= -- make D= Cancel Cancel Clk D Blue light Let s give priority to -- make D= Circuit derived from truth table, using Chapter 2 combinational logic design process 23
Bit torage ummary R latch (set) R (reset) Feature: = sets to, R= resets to. Problem: R= yields undefined, other glitches may set/reset inadvertently. Level-sensitive R latch C R R Feature: and R only have effect when C=. An external circuit can prevent R= when C=. Problem: avoiding R= can be a burden. D C R R D latch Feature: R can t be. Problem: C= for too long will propagate new values through too many latches; for too short may not result in the bit being stored. D Clk D latch Dm m Cm master D flip-flop D latch Ds s Cs s servant Feature: Only loads D value present at rising clock edge, so values can't propagate to other flip-flops during same clock cycle. Tradeoff: uses more gates internally, and requires more external gates than R but transistors today are more plentiful and cheaper. We considered increasingly better bit storage until we arrived at the robust D flip-flop bit storage 24
Basic Register Typically, we store multi-bit items e.g., storing a 4-bit binary number Register: multiple flip-flops sharing clock signal From this point, we ll use registers for bit storage No need to think of latches or flip-flops But now you know what s inside a register I3 I2 I I 4-bit register D D D D I3 I2 I I reg(4) clk 3 2 3 2 25
Example Using Registers: Temperature Display Temperature history display ensor outputs temperature as 5-bit binary number Timer pulses C every hour Record temperature on each pulse, display last three recorded values Present hour ago 2 hours ago 24 2 8 Temperature sensor x4 x3 x2 x x a4 Display Display a3 a2 a a b4 b3 b2 b b TemperatureHistorytorage Display c4 c3 c2 c c timer C 26
Example Using Registers: Temperature Display Use three 5-bit registers 24 2 8 C x4 x3 x2 x x I4 I3 I2 I I Ra 4 3 2 a4 a3 a2 a a I4 I3 I2 I I Rb 4 3 2 b4 b3 b2 b b I4 I3 I2 I I Rc 4 3 2 c4 c3 c2 c c TemperatureHistorytorage x4...x 5 8 2 2 2 22 24 24 24 25 25 26 26 26 27 27 27 27 Note that registers only loaded on rising clock edges C Ra Rb 8 2 8 24 2 25 24 26 25 27 26 Rc 8 2 24 25 27
Other FlipFlop/Latch Types JK Latch JK FlipFlop T FlipFlop JK Latch JK Latch Less important these days D-FlipFlop and derivates dominate https://www.electronics-tutorials.ws/sequential/seq_2.html T-FlipFlop https://www.wikipedia.com 28
Other FlipFlop/Latch Types JK Latch Prevents that = and R= by AND3 and opposite values of and / R Latch CLK J K n+ Functionality X X n No change n No change et Reset Toggle 29
Other FlipFlop/Latch Types JK FlipFlop 3
Was haben ie heute gelernt? equentielle chaltung R Latch und D Latch D FlipFlop Register JK Latch / FlipFlop 3